blob: 62cc98910a7f62427dd98566ee8bb99dcde9e367 [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay85b53972018-03-12 10:46:10 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay85b53972018-03-12 10:46:10 +01004 */
Patrick Delaunayba779402020-11-06 19:01:29 +01005
6#define LOG_CATEGORY LOGC_ARCH
7
Patrick Delaunay85b53972018-03-12 10:46:10 +01008#include <clk.h>
Simon Glass1d91ba72019-11-14 12:57:37 -07009#include <cpu_func.h>
Patrick Delaunay82168e82018-05-17 14:50:46 +020010#include <debug_uart.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060011#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Patrick Delaunayc9468742021-05-07 14:50:35 +020014#include <lmb.h>
Patrick Delaunayf3674a42018-05-17 15:24:07 +020015#include <misc.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060016#include <spl.h>
Patrick Delaunay3fa644b2024-01-15 15:05:51 +010017#include <asm/cache.h>
Patrick Delaunay85b53972018-03-12 10:46:10 +010018#include <asm/io.h>
19#include <asm/arch/stm32.h>
Patrick Delaunay01e3afe2018-03-19 19:09:21 +010020#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060021#include <asm/global_data.h>
Patrick Delaunayf3674a42018-05-17 15:24:07 +020022#include <dm/device.h>
Patrick Delaunayc5d15652018-03-20 10:54:53 +010023#include <dm/uclass.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060024#include <linux/bitops.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060025#include <linux/printk.h>
Patrick Delaunay85b53972018-03-12 10:46:10 +010026
Patrick Delaunay8e6985b2020-04-30 16:30:20 +020027/*
28 * early TLB into the .data section so that it not get cleared
29 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
30 */
31u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
32
Patrick Delaunay18660a62019-02-27 17:01:12 +010033u32 get_bootmode(void)
34{
35 /* read bootmode from TAMP backup register */
36 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
37 TAMP_BOOT_MODE_SHIFT;
Patrick Delaunayc5d15652018-03-20 10:54:53 +010038}
39
Igor Opaniuk100e0ec2023-11-06 11:41:52 +010040u32 get_bootauth(void)
41{
42 /* read boot auth status and partition from TAMP backup register */
43 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_AUTH_MASK) >>
44 TAMP_BOOT_AUTH_SHIFT;
45}
46
Patrick Delaunayc5d15652018-03-20 10:54:53 +010047/*
Patrick Delaunay4ad5a122021-02-05 13:53:33 +010048 * weak function overidde: set the DDR/SYSRAM executable before to enable the
49 * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
50 */
51void dram_bank_mmu_setup(int bank)
52{
53 struct bd_info *bd = gd->bd;
54 int i;
55 phys_addr_t start;
56 phys_size_t size;
Patrick Delaunayc9468742021-05-07 14:50:35 +020057 bool use_lmb = false;
58 enum dcache_option option;
Patrick Delaunay4ad5a122021-02-05 13:53:33 +010059
Simon Glass85ed77d2024-09-29 19:49:46 -060060 if (IS_ENABLED(CONFIG_XPL_BUILD)) {
Patrick Delaunay123687c2022-05-20 18:24:46 +020061/* STM32_SYSRAM_BASE exist only when SPL is supported */
62#ifdef CONFIG_SPL
Patrick Delaunay4ad5a122021-02-05 13:53:33 +010063 start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
64 size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
Patrick Delaunay123687c2022-05-20 18:24:46 +020065#endif
Patrick Delaunay4ad5a122021-02-05 13:53:33 +010066 } else if (gd->flags & GD_FLG_RELOC) {
67 /* bd->bi_dram is available only after relocation */
68 start = bd->bi_dram[bank].start;
69 size = bd->bi_dram[bank].size;
Patrick Delaunayc9468742021-05-07 14:50:35 +020070 use_lmb = true;
Patrick Delaunay4ad5a122021-02-05 13:53:33 +010071 } else {
72 /* mark cacheable and executable the beggining of the DDR */
73 start = STM32_DDR_BASE;
74 size = CONFIG_DDR_CACHEABLE_SIZE;
75 }
76
77 for (i = start >> MMU_SECTION_SHIFT;
78 i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
Patrick Delaunayc9468742021-05-07 14:50:35 +020079 i++) {
80 option = DCACHE_DEFAULT_OPTION;
Sughosh Ganu291bf9c2024-08-26 17:29:18 +053081 if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP))
Patrick Delaunayc9468742021-05-07 14:50:35 +020082 option = 0; /* INVALID ENTRY in TLB */
83 set_section_dcache(i, option);
84 }
Patrick Delaunay4ad5a122021-02-05 13:53:33 +010085}
86/*
Patrick Delaunay8e6985b2020-04-30 16:30:20 +020087 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
88 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
89 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
90 */
91static void early_enable_caches(void)
92{
93 /* I-cache is already enabled in start.S: cpu_init_cp15 */
94
95 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
96 return;
97
Bhupesh Sharma58af3fb2023-08-22 13:21:11 +053098#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
Patrice Chotard18a87162021-02-24 13:53:27 +010099 gd->arch.tlb_size = PGTABLE_SIZE;
100 gd->arch.tlb_addr = (unsigned long)&early_tlb;
Bhupesh Sharma58af3fb2023-08-22 13:21:11 +0530101#endif
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200102
Patrick Delaunay4ad5a122021-02-05 13:53:33 +0100103 /* enable MMU (default configuration) */
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200104 dcache_enable();
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200105}
106
107/*
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100108 * Early system init
109 */
Patrick Delaunay85b53972018-03-12 10:46:10 +0100110int arch_cpu_init(void)
111{
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200112 early_enable_caches();
113
Patrick Delaunay85b53972018-03-12 10:46:10 +0100114 /* early armv7 timer init: needed for polling */
115 timer_init();
116
Patrick Delaunaye4bdd542022-05-20 18:24:42 +0200117 return 0;
118}
119
120/* weak function for SOC specific initialization */
121__weak void stm32mp_cpu_init(void)
122{
123}
124
125int mach_cpu_init(void)
126{
127 u32 boot_mode;
128
129 stm32mp_cpu_init();
Patrick Delaunay82168e82018-05-17 14:50:46 +0200130
Patrick Delaunay82168e82018-05-17 14:50:46 +0200131 boot_mode = get_bootmode();
132
Patrick Delaunay29b2e2e2021-02-25 13:37:01 +0100133 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
134 (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
Patrick Delaunay82168e82018-05-17 14:50:46 +0200135 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
Simon Glass85ed77d2024-09-29 19:49:46 -0600136 else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD))
Patrick Delaunay82168e82018-05-17 14:50:46 +0200137 debug_uart_init();
Patrick Delaunay85b53972018-03-12 10:46:10 +0100138
139 return 0;
140}
141
Patrick Delaunay58e95532018-03-19 19:09:20 +0100142void enable_caches(void)
143{
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200144 /* I-cache is already enabled in start.S: icache_enable() not needed */
145
Patrick Delaunaye880ea62024-10-11 17:31:49 +0200146 /* keep D-cache configuration done before relocation, wait arch_early_init_r*/
147}
148
149int arch_early_init_r(void)
150{
Patrick Delaunay8e6985b2020-04-30 16:30:20 +0200151 /* deactivate the data cache, early enabled in arch_cpu_init() */
152 dcache_disable();
153 /*
154 * update MMU after relocation and enable the data cache
155 * warning: the TLB location udpated in board_f.c::reserve_mmu
156 */
Patrick Delaunay58e95532018-03-19 19:09:20 +0100157 dcache_enable();
Patrick Delaunaye880ea62024-10-11 17:31:49 +0200158
159 return 0;
Patrick Delaunay58e95532018-03-19 19:09:20 +0100160}
161
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100162static void setup_boot_mode(void)
163{
Patrick Delaunay18660a62019-02-27 17:01:12 +0100164 const u32 serial_addr[] = {
165 STM32_USART1_BASE,
166 STM32_USART2_BASE,
167 STM32_USART3_BASE,
168 STM32_UART4_BASE,
169 STM32_UART5_BASE,
170 STM32_USART6_BASE,
171 STM32_UART7_BASE,
172 STM32_UART8_BASE
173 };
Patrick Delaunay5c2f6d72021-07-06 17:19:45 +0200174 const u32 sdmmc_addr[] = {
175 STM32_SDMMC1_BASE,
176 STM32_SDMMC2_BASE,
177 STM32_SDMMC3_BASE
178 };
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100179 char cmd[60];
180 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
181 u32 boot_mode =
182 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
Patrick Delaunay1b03eb02019-06-21 15:26:39 +0200183 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100184 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
Patrick Delaunay18660a62019-02-27 17:01:12 +0100185 struct udevice *dev;
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100186
Patrick Delaunayba779402020-11-06 19:01:29 +0100187 log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
188 __func__, boot_ctx, boot_mode, instance, forced_mode);
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100189 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
190 case BOOT_SERIAL_UART:
Rasmus Villemoes6d83f3c2023-03-24 08:55:19 +0100191 if (instance >= ARRAY_SIZE(serial_addr))
Patrick Delaunay18660a62019-02-27 17:01:12 +0100192 break;
Patrick Delaunaye2592992021-02-25 13:37:03 +0100193 /* serial : search associated node in devicetree */
Patrick Delaunay18660a62019-02-27 17:01:12 +0100194 sprintf(cmd, "serial@%x", serial_addr[instance]);
Patrick Delaunaye2592992021-02-25 13:37:03 +0100195 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
Patrick Delaunay7540d872021-02-25 13:37:02 +0100196 /* restore console on error */
197 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
198 gd->flags &= ~(GD_FLG_SILENT |
199 GD_FLG_DISABLE_CONSOLE);
Patrick Delaunay643e4042021-04-06 09:27:39 +0200200 log_err("uart%d = %s not found in device tree!\n",
201 instance + 1, cmd);
Patrick Delaunay18660a62019-02-27 17:01:12 +0100202 break;
Patrick Delaunay7540d872021-02-25 13:37:02 +0100203 }
Patrick Delaunaye2592992021-02-25 13:37:03 +0100204 sprintf(cmd, "%d", dev_seq(dev));
Patrick Delaunay18660a62019-02-27 17:01:12 +0100205 env_set("boot_device", "serial");
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100206 env_set("boot_instance", cmd);
Patrick Delaunay18660a62019-02-27 17:01:12 +0100207
208 /* restore console on uart when not used */
Patrick Delaunay29b2e2e2021-02-25 13:37:01 +0100209 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
Patrick Delaunay18660a62019-02-27 17:01:12 +0100210 gd->flags &= ~(GD_FLG_SILENT |
211 GD_FLG_DISABLE_CONSOLE);
Patrick Delaunay643e4042021-04-06 09:27:39 +0200212 log_info("serial boot with console enabled!\n");
Patrick Delaunay18660a62019-02-27 17:01:12 +0100213 }
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100214 break;
215 case BOOT_SERIAL_USB:
216 env_set("boot_device", "usb");
217 env_set("boot_instance", "0");
218 break;
219 case BOOT_FLASH_SD:
220 case BOOT_FLASH_EMMC:
Rasmus Villemoes6d83f3c2023-03-24 08:55:19 +0100221 if (instance >= ARRAY_SIZE(sdmmc_addr))
Patrick Delaunay5c2f6d72021-07-06 17:19:45 +0200222 break;
223 /* search associated sdmmc node in devicetree */
224 sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
225 if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
226 printf("mmc%d = %s not found in device tree!\n",
227 instance, cmd);
228 break;
229 }
230 sprintf(cmd, "%d", dev_seq(dev));
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100231 env_set("boot_device", "mmc");
232 env_set("boot_instance", cmd);
233 break;
234 case BOOT_FLASH_NAND:
235 env_set("boot_device", "nand");
236 env_set("boot_instance", "0");
237 break;
Patrick Delaunayb5a7ca22020-03-18 09:22:52 +0100238 case BOOT_FLASH_SPINAND:
239 env_set("boot_device", "spi-nand");
240 env_set("boot_instance", "0");
241 break;
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100242 case BOOT_FLASH_NOR:
243 env_set("boot_device", "nor");
244 env_set("boot_instance", "0");
245 break;
246 default:
Patrick Delaunay02e91972021-07-08 10:53:56 +0200247 env_set("boot_device", "invalid");
248 env_set("boot_instance", "");
249 log_err("unexpected boot mode = %x\n", boot_mode);
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100250 break;
251 }
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100252
253 switch (forced_mode) {
254 case BOOT_FASTBOOT:
Patrick Delaunay643e4042021-04-06 09:27:39 +0200255 log_info("Enter fastboot!\n");
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100256 env_set("preboot", "env set preboot; fastboot 0");
257 break;
258 case BOOT_STM32PROG:
259 env_set("boot_device", "usb");
260 env_set("boot_instance", "0");
261 break;
262 case BOOT_UMS_MMC0:
263 case BOOT_UMS_MMC1:
264 case BOOT_UMS_MMC2:
Patrick Delaunay643e4042021-04-06 09:27:39 +0200265 log_info("Enter UMS!\n");
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100266 instance = forced_mode - BOOT_UMS_MMC0;
267 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
268 env_set("preboot", cmd);
269 break;
270 case BOOT_RECOVERY:
271 env_set("preboot", "env set preboot; run altbootcmd");
272 break;
273 case BOOT_NORMAL:
274 break;
275 default:
Patrick Delaunayba779402020-11-06 19:01:29 +0100276 log_debug("unexpected forced boot mode = %x\n", forced_mode);
Patrick Delaunay008d3c32019-02-27 17:01:20 +0100277 break;
278 }
279
280 /* clear TAMP for next reboot */
281 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200282}
283
Patrick Delaunaye4bdd542022-05-20 18:24:42 +0200284__weak void stm32mp_misc_init(void)
Marek Vasut0eda28c2021-03-31 14:15:09 +0200285{
Igor Opaniuk100e0ec2023-11-06 11:41:52 +0100286}
287
288static int setup_boot_auth_info(void)
289{
290 char buf[10];
291 u32 bootauth = get_bootauth();
292
293 snprintf(buf, sizeof(buf), "%d", bootauth >> 4);
294 env_set("boot_auth", buf);
295
296 snprintf(buf, sizeof(buf), "%d", bootauth &
297 (u32)TAMP_BOOT_PARTITION_MASK);
298 env_set("boot_part", buf);
299
300 return 0;
Marek Vasut0eda28c2021-03-31 14:15:09 +0200301}
302
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100303int arch_misc_init(void)
304{
Igor Opaniuk100e0ec2023-11-06 11:41:52 +0100305 setup_boot_auth_info();
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100306 setup_boot_mode();
Patrick Delaunayf3674a42018-05-17 15:24:07 +0200307 setup_mac_address();
308 setup_serial_number();
Patrick Delaunaye4bdd542022-05-20 18:24:42 +0200309 stm32mp_misc_init();
Patrick Delaunayc5d15652018-03-20 10:54:53 +0100310
311 return 0;
312}
Marek Vasutefdedcb2023-01-12 18:58:40 +0100313
314/*
315 * Without forcing the ".data" section, this would get saved in ".bss". BSS
316 * will be cleared soon after, so it's not suitable.
317 */
318static uintptr_t rom_api_table __section(".data");
319static uintptr_t nt_fw_dtb __section(".data");
320
321/*
322 * The ROM gives us the API location in r0 when starting. This is only available
323 * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save
324 * the FDT address provided by TF-A in r2 at boot time. This function is called
325 * from start.S
326 */
327void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
328 unsigned long r3)
329{
330 if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY))
331 rom_api_table = r0;
332
333 if (IS_ENABLED(CONFIG_TFABOOT))
334 nt_fw_dtb = r2;
335
336 save_boot_params_ret();
337}
338
339uintptr_t get_stm32mp_rom_api_table(void)
340{
341 return rom_api_table;
342}
343
344uintptr_t get_stm32mp_bl2_dtb(void)
345{
346 return nt_fw_dtb;
347}
Marek Vasut7cf2c332023-01-12 18:58:41 +0100348
Simon Glass85ed77d2024-09-29 19:49:46 -0600349#ifdef CONFIG_XPL_BUILD
Marek Vasut7cf2c332023-01-12 18:58:41 +0100350void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
351{
352 typedef void __noreturn (*image_entry_stm32_t)(u32 romapi);
353 uintptr_t romapi = get_stm32mp_rom_api_table();
354
355 image_entry_stm32_t image_entry =
356 (image_entry_stm32_t)spl_image->entry_point;
357
358 printf("image entry point: 0x%lx\n", spl_image->entry_point);
359 image_entry(romapi);
360}
361#endif