Tom Rini | 8b0c8a1 | 2018-05-06 18:27:01 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 4 | */ |
Patrick Delaunay | ba77940 | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 5 | |
| 6 | #define LOG_CATEGORY LOGC_ARCH |
| 7 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 8 | #include <common.h> |
| 9 | #include <clk.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 10 | #include <cpu_func.h> |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 11 | #include <debug_uart.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 12 | #include <env.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 14 | #include <log.h> |
Patrick Delaunay | c946874 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 15 | #include <lmb.h> |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 16 | #include <misc.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 17 | #include <net.h> |
Simon Glass | bdd5f81 | 2023-09-14 18:21:46 -0600 | [diff] [blame^] | 18 | #include <spl.h> |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 19 | #include <asm/io.h> |
| 20 | #include <asm/arch/stm32.h> |
Patrick Delaunay | 01e3afe | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 21 | #include <asm/arch/sys_proto.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 22 | #include <asm/global_data.h> |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 23 | #include <dm/device.h> |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 24 | #include <dm/uclass.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 25 | #include <linux/bitops.h> |
Simon Glass | bdd5f81 | 2023-09-14 18:21:46 -0600 | [diff] [blame^] | 26 | #include <linux/printk.h> |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 27 | |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 28 | /* |
| 29 | * early TLB into the .data section so that it not get cleared |
| 30 | * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) |
| 31 | */ |
| 32 | u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); |
| 33 | |
Patrick Delaunay | c946874 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 34 | struct lmb lmb; |
| 35 | |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 36 | u32 get_bootmode(void) |
| 37 | { |
| 38 | /* read bootmode from TAMP backup register */ |
| 39 | return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> |
| 40 | TAMP_BOOT_MODE_SHIFT; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 41 | } |
| 42 | |
| 43 | /* |
Patrick Delaunay | 4ad5a12 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 44 | * weak function overidde: set the DDR/SYSRAM executable before to enable the |
| 45 | * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) |
| 46 | */ |
| 47 | void dram_bank_mmu_setup(int bank) |
| 48 | { |
| 49 | struct bd_info *bd = gd->bd; |
| 50 | int i; |
| 51 | phys_addr_t start; |
| 52 | phys_size_t size; |
Patrick Delaunay | c946874 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 53 | bool use_lmb = false; |
| 54 | enum dcache_option option; |
Patrick Delaunay | 4ad5a12 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 55 | |
| 56 | if (IS_ENABLED(CONFIG_SPL_BUILD)) { |
Patrick Delaunay | 123687c | 2022-05-20 18:24:46 +0200 | [diff] [blame] | 57 | /* STM32_SYSRAM_BASE exist only when SPL is supported */ |
| 58 | #ifdef CONFIG_SPL |
Patrick Delaunay | 4ad5a12 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 59 | start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); |
| 60 | size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); |
Patrick Delaunay | 123687c | 2022-05-20 18:24:46 +0200 | [diff] [blame] | 61 | #endif |
Patrick Delaunay | 4ad5a12 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 62 | } else if (gd->flags & GD_FLG_RELOC) { |
| 63 | /* bd->bi_dram is available only after relocation */ |
| 64 | start = bd->bi_dram[bank].start; |
| 65 | size = bd->bi_dram[bank].size; |
Patrick Delaunay | c946874 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 66 | use_lmb = true; |
Patrick Delaunay | 4ad5a12 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 67 | } else { |
| 68 | /* mark cacheable and executable the beggining of the DDR */ |
| 69 | start = STM32_DDR_BASE; |
| 70 | size = CONFIG_DDR_CACHEABLE_SIZE; |
| 71 | } |
| 72 | |
| 73 | for (i = start >> MMU_SECTION_SHIFT; |
| 74 | i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); |
Patrick Delaunay | c946874 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 75 | i++) { |
| 76 | option = DCACHE_DEFAULT_OPTION; |
| 77 | if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP)) |
| 78 | option = 0; /* INVALID ENTRY in TLB */ |
| 79 | set_section_dcache(i, option); |
| 80 | } |
Patrick Delaunay | 4ad5a12 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 81 | } |
| 82 | /* |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 83 | * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage |
| 84 | * MMU/TLB is updated in enable_caches() for U-Boot after relocation |
| 85 | * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 |
| 86 | */ |
| 87 | static void early_enable_caches(void) |
| 88 | { |
| 89 | /* I-cache is already enabled in start.S: cpu_init_cp15 */ |
| 90 | |
| 91 | if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) |
| 92 | return; |
| 93 | |
Patrice Chotard | 18a8716 | 2021-02-24 13:53:27 +0100 | [diff] [blame] | 94 | if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { |
| 95 | gd->arch.tlb_size = PGTABLE_SIZE; |
| 96 | gd->arch.tlb_addr = (unsigned long)&early_tlb; |
| 97 | } |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 98 | |
Patrick Delaunay | 4ad5a12 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 99 | /* enable MMU (default configuration) */ |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 100 | dcache_enable(); |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | /* |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 104 | * Early system init |
| 105 | */ |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 106 | int arch_cpu_init(void) |
| 107 | { |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 108 | early_enable_caches(); |
| 109 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 110 | /* early armv7 timer init: needed for polling */ |
| 111 | timer_init(); |
| 112 | |
Patrick Delaunay | e4bdd54 | 2022-05-20 18:24:42 +0200 | [diff] [blame] | 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | /* weak function for SOC specific initialization */ |
| 117 | __weak void stm32mp_cpu_init(void) |
| 118 | { |
| 119 | } |
| 120 | |
| 121 | int mach_cpu_init(void) |
| 122 | { |
| 123 | u32 boot_mode; |
| 124 | |
| 125 | stm32mp_cpu_init(); |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 126 | |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 127 | boot_mode = get_bootmode(); |
| 128 | |
Patrick Delaunay | 29b2e2e | 2021-02-25 13:37:01 +0100 | [diff] [blame] | 129 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && |
| 130 | (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 131 | gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; |
Patrick Delaunay | d8299de | 2021-10-11 09:52:51 +0200 | [diff] [blame] | 132 | else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 133 | debug_uart_init(); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 134 | |
| 135 | return 0; |
| 136 | } |
| 137 | |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 138 | void enable_caches(void) |
| 139 | { |
Patrick Delaunay | c946874 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 140 | /* parse device tree when data cache is still activated */ |
| 141 | lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); |
| 142 | |
Patrick Delaunay | 8e6985b | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 143 | /* I-cache is already enabled in start.S: icache_enable() not needed */ |
| 144 | |
| 145 | /* deactivate the data cache, early enabled in arch_cpu_init() */ |
| 146 | dcache_disable(); |
| 147 | /* |
| 148 | * update MMU after relocation and enable the data cache |
| 149 | * warning: the TLB location udpated in board_f.c::reserve_mmu |
| 150 | */ |
Patrick Delaunay | 58e9553 | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 151 | dcache_enable(); |
| 152 | } |
| 153 | |
Patrick Delaunay | d8299de | 2021-10-11 09:52:51 +0200 | [diff] [blame] | 154 | /* used when CONFIG_DISPLAY_CPUINFO is activated */ |
Patrick Delaunay | 3e738f2 | 2020-02-12 19:37:43 +0100 | [diff] [blame] | 155 | int print_cpuinfo(void) |
| 156 | { |
| 157 | char name[SOC_NAME_SIZE]; |
| 158 | |
| 159 | get_soc_name(name); |
| 160 | printf("CPU: %s\n", name); |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 161 | |
| 162 | return 0; |
| 163 | } |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 164 | |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 165 | static void setup_boot_mode(void) |
| 166 | { |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 167 | const u32 serial_addr[] = { |
| 168 | STM32_USART1_BASE, |
| 169 | STM32_USART2_BASE, |
| 170 | STM32_USART3_BASE, |
| 171 | STM32_UART4_BASE, |
| 172 | STM32_UART5_BASE, |
| 173 | STM32_USART6_BASE, |
| 174 | STM32_UART7_BASE, |
| 175 | STM32_UART8_BASE |
| 176 | }; |
Patrick Delaunay | 5c2f6d7 | 2021-07-06 17:19:45 +0200 | [diff] [blame] | 177 | const u32 sdmmc_addr[] = { |
| 178 | STM32_SDMMC1_BASE, |
| 179 | STM32_SDMMC2_BASE, |
| 180 | STM32_SDMMC3_BASE |
| 181 | }; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 182 | char cmd[60]; |
| 183 | u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); |
| 184 | u32 boot_mode = |
| 185 | (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; |
Patrick Delaunay | 1b03eb0 | 2019-06-21 15:26:39 +0200 | [diff] [blame] | 186 | unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 187 | u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 188 | struct udevice *dev; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 189 | |
Patrick Delaunay | ba77940 | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 190 | log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", |
| 191 | __func__, boot_ctx, boot_mode, instance, forced_mode); |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 192 | switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { |
| 193 | case BOOT_SERIAL_UART: |
Rasmus Villemoes | 6d83f3c | 2023-03-24 08:55:19 +0100 | [diff] [blame] | 194 | if (instance >= ARRAY_SIZE(serial_addr)) |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 195 | break; |
Patrick Delaunay | e259299 | 2021-02-25 13:37:03 +0100 | [diff] [blame] | 196 | /* serial : search associated node in devicetree */ |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 197 | sprintf(cmd, "serial@%x", serial_addr[instance]); |
Patrick Delaunay | e259299 | 2021-02-25 13:37:03 +0100 | [diff] [blame] | 198 | if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { |
Patrick Delaunay | 7540d87 | 2021-02-25 13:37:02 +0100 | [diff] [blame] | 199 | /* restore console on error */ |
| 200 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) |
| 201 | gd->flags &= ~(GD_FLG_SILENT | |
| 202 | GD_FLG_DISABLE_CONSOLE); |
Patrick Delaunay | 643e404 | 2021-04-06 09:27:39 +0200 | [diff] [blame] | 203 | log_err("uart%d = %s not found in device tree!\n", |
| 204 | instance + 1, cmd); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 205 | break; |
Patrick Delaunay | 7540d87 | 2021-02-25 13:37:02 +0100 | [diff] [blame] | 206 | } |
Patrick Delaunay | e259299 | 2021-02-25 13:37:03 +0100 | [diff] [blame] | 207 | sprintf(cmd, "%d", dev_seq(dev)); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 208 | env_set("boot_device", "serial"); |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 209 | env_set("boot_instance", cmd); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 210 | |
| 211 | /* restore console on uart when not used */ |
Patrick Delaunay | 29b2e2e | 2021-02-25 13:37:01 +0100 | [diff] [blame] | 212 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 213 | gd->flags &= ~(GD_FLG_SILENT | |
| 214 | GD_FLG_DISABLE_CONSOLE); |
Patrick Delaunay | 643e404 | 2021-04-06 09:27:39 +0200 | [diff] [blame] | 215 | log_info("serial boot with console enabled!\n"); |
Patrick Delaunay | 18660a6 | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 216 | } |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 217 | break; |
| 218 | case BOOT_SERIAL_USB: |
| 219 | env_set("boot_device", "usb"); |
| 220 | env_set("boot_instance", "0"); |
| 221 | break; |
| 222 | case BOOT_FLASH_SD: |
| 223 | case BOOT_FLASH_EMMC: |
Rasmus Villemoes | 6d83f3c | 2023-03-24 08:55:19 +0100 | [diff] [blame] | 224 | if (instance >= ARRAY_SIZE(sdmmc_addr)) |
Patrick Delaunay | 5c2f6d7 | 2021-07-06 17:19:45 +0200 | [diff] [blame] | 225 | break; |
| 226 | /* search associated sdmmc node in devicetree */ |
| 227 | sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); |
| 228 | if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) { |
| 229 | printf("mmc%d = %s not found in device tree!\n", |
| 230 | instance, cmd); |
| 231 | break; |
| 232 | } |
| 233 | sprintf(cmd, "%d", dev_seq(dev)); |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 234 | env_set("boot_device", "mmc"); |
| 235 | env_set("boot_instance", cmd); |
| 236 | break; |
| 237 | case BOOT_FLASH_NAND: |
| 238 | env_set("boot_device", "nand"); |
| 239 | env_set("boot_instance", "0"); |
| 240 | break; |
Patrick Delaunay | b5a7ca2 | 2020-03-18 09:22:52 +0100 | [diff] [blame] | 241 | case BOOT_FLASH_SPINAND: |
| 242 | env_set("boot_device", "spi-nand"); |
| 243 | env_set("boot_instance", "0"); |
| 244 | break; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 245 | case BOOT_FLASH_NOR: |
| 246 | env_set("boot_device", "nor"); |
| 247 | env_set("boot_instance", "0"); |
| 248 | break; |
| 249 | default: |
Patrick Delaunay | 02e9197 | 2021-07-08 10:53:56 +0200 | [diff] [blame] | 250 | env_set("boot_device", "invalid"); |
| 251 | env_set("boot_instance", ""); |
| 252 | log_err("unexpected boot mode = %x\n", boot_mode); |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 253 | break; |
| 254 | } |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 255 | |
| 256 | switch (forced_mode) { |
| 257 | case BOOT_FASTBOOT: |
Patrick Delaunay | 643e404 | 2021-04-06 09:27:39 +0200 | [diff] [blame] | 258 | log_info("Enter fastboot!\n"); |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 259 | env_set("preboot", "env set preboot; fastboot 0"); |
| 260 | break; |
| 261 | case BOOT_STM32PROG: |
| 262 | env_set("boot_device", "usb"); |
| 263 | env_set("boot_instance", "0"); |
| 264 | break; |
| 265 | case BOOT_UMS_MMC0: |
| 266 | case BOOT_UMS_MMC1: |
| 267 | case BOOT_UMS_MMC2: |
Patrick Delaunay | 643e404 | 2021-04-06 09:27:39 +0200 | [diff] [blame] | 268 | log_info("Enter UMS!\n"); |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 269 | instance = forced_mode - BOOT_UMS_MMC0; |
| 270 | sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); |
| 271 | env_set("preboot", cmd); |
| 272 | break; |
| 273 | case BOOT_RECOVERY: |
| 274 | env_set("preboot", "env set preboot; run altbootcmd"); |
| 275 | break; |
| 276 | case BOOT_NORMAL: |
| 277 | break; |
| 278 | default: |
Patrick Delaunay | ba77940 | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 279 | log_debug("unexpected forced boot mode = %x\n", forced_mode); |
Patrick Delaunay | 008d3c3 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 280 | break; |
| 281 | } |
| 282 | |
| 283 | /* clear TAMP for next reboot */ |
| 284 | clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 285 | } |
| 286 | |
| 287 | /* |
| 288 | * If there is no MAC address in the environment, then it will be initialized |
| 289 | * (silently) from the value in the OTP. |
| 290 | */ |
Marek Vasut | 187cae2 | 2019-12-18 16:52:19 +0100 | [diff] [blame] | 291 | __weak int setup_mac_address(void) |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 292 | { |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 293 | int ret; |
| 294 | int i; |
Patrick Delaunay | 6425f58 | 2022-05-20 18:24:47 +0200 | [diff] [blame] | 295 | u32 otp[3]; |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 296 | uchar enetaddr[6]; |
| 297 | struct udevice *dev; |
Patrick Delaunay | 6425f58 | 2022-05-20 18:24:47 +0200 | [diff] [blame] | 298 | int nb_eth, nb_otp, index; |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 299 | |
Patrick Delaunay | d8299de | 2021-10-11 09:52:51 +0200 | [diff] [blame] | 300 | if (!IS_ENABLED(CONFIG_NET)) |
| 301 | return 0; |
| 302 | |
Patrick Delaunay | 6425f58 | 2022-05-20 18:24:47 +0200 | [diff] [blame] | 303 | nb_eth = get_eth_nb(); |
| 304 | |
| 305 | /* 6 bytes for each MAC addr and 4 bytes for each OTP */ |
| 306 | nb_otp = DIV_ROUND_UP(6 * nb_eth, 4); |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 307 | |
| 308 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
Simon Glass | 65130cd | 2020-12-28 20:34:56 -0700 | [diff] [blame] | 309 | DM_DRIVER_GET(stm32mp_bsec), |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 310 | &dev); |
| 311 | if (ret) |
| 312 | return ret; |
| 313 | |
Patrick Delaunay | 6425f58 | 2022-05-20 18:24:47 +0200 | [diff] [blame] | 314 | ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp); |
Simon Glass | 587dc40 | 2018-11-06 15:21:39 -0700 | [diff] [blame] | 315 | if (ret < 0) |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 316 | return ret; |
| 317 | |
Patrick Delaunay | 6425f58 | 2022-05-20 18:24:47 +0200 | [diff] [blame] | 318 | for (index = 0; index < nb_eth; index++) { |
| 319 | /* MAC already in environment */ |
| 320 | if (eth_env_get_enetaddr_by_index("eth", index, enetaddr)) |
| 321 | continue; |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 322 | |
Patrick Delaunay | 6425f58 | 2022-05-20 18:24:47 +0200 | [diff] [blame] | 323 | for (i = 0; i < 6; i++) |
| 324 | enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index]; |
| 325 | |
| 326 | if (!is_valid_ethaddr(enetaddr)) { |
| 327 | log_err("invalid MAC address %d in OTP %pM\n", |
| 328 | index, enetaddr); |
| 329 | return -EINVAL; |
| 330 | } |
| 331 | log_debug("OTP MAC address %d = %pM\n", index, enetaddr); |
| 332 | ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr); |
| 333 | if (ret) { |
| 334 | log_err("Failed to set mac address %pM from OTP: %d\n", |
| 335 | enetaddr, ret); |
| 336 | return ret; |
| 337 | } |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 338 | } |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | static int setup_serial_number(void) |
| 344 | { |
| 345 | char serial_string[25]; |
| 346 | u32 otp[3] = {0, 0, 0 }; |
| 347 | struct udevice *dev; |
| 348 | int ret; |
| 349 | |
| 350 | if (env_get("serial#")) |
| 351 | return 0; |
| 352 | |
| 353 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
Simon Glass | 65130cd | 2020-12-28 20:34:56 -0700 | [diff] [blame] | 354 | DM_DRIVER_GET(stm32mp_bsec), |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 355 | &dev); |
| 356 | if (ret) |
| 357 | return ret; |
| 358 | |
Patrick Delaunay | 10263a5 | 2019-02-27 17:01:29 +0100 | [diff] [blame] | 359 | ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL), |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 360 | otp, sizeof(otp)); |
Simon Glass | 587dc40 | 2018-11-06 15:21:39 -0700 | [diff] [blame] | 361 | if (ret < 0) |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 362 | return ret; |
| 363 | |
Patrick Delaunay | af5564a | 2019-02-27 17:01:25 +0100 | [diff] [blame] | 364 | sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]); |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 365 | env_set("serial#", serial_string); |
| 366 | |
| 367 | return 0; |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 368 | } |
| 369 | |
Patrick Delaunay | e4bdd54 | 2022-05-20 18:24:42 +0200 | [diff] [blame] | 370 | __weak void stm32mp_misc_init(void) |
Marek Vasut | 0eda28c | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 371 | { |
Marek Vasut | 0eda28c | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 372 | } |
| 373 | |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 374 | int arch_misc_init(void) |
| 375 | { |
| 376 | setup_boot_mode(); |
Patrick Delaunay | f3674a4 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 377 | setup_mac_address(); |
| 378 | setup_serial_number(); |
Patrick Delaunay | e4bdd54 | 2022-05-20 18:24:42 +0200 | [diff] [blame] | 379 | stm32mp_misc_init(); |
Patrick Delaunay | c5d1565 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 380 | |
| 381 | return 0; |
| 382 | } |
Marek Vasut | efdedcb | 2023-01-12 18:58:40 +0100 | [diff] [blame] | 383 | |
| 384 | /* |
| 385 | * Without forcing the ".data" section, this would get saved in ".bss". BSS |
| 386 | * will be cleared soon after, so it's not suitable. |
| 387 | */ |
| 388 | static uintptr_t rom_api_table __section(".data"); |
| 389 | static uintptr_t nt_fw_dtb __section(".data"); |
| 390 | |
| 391 | /* |
| 392 | * The ROM gives us the API location in r0 when starting. This is only available |
| 393 | * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save |
| 394 | * the FDT address provided by TF-A in r2 at boot time. This function is called |
| 395 | * from start.S |
| 396 | */ |
| 397 | void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, |
| 398 | unsigned long r3) |
| 399 | { |
| 400 | if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY)) |
| 401 | rom_api_table = r0; |
| 402 | |
| 403 | if (IS_ENABLED(CONFIG_TFABOOT)) |
| 404 | nt_fw_dtb = r2; |
| 405 | |
| 406 | save_boot_params_ret(); |
| 407 | } |
| 408 | |
| 409 | uintptr_t get_stm32mp_rom_api_table(void) |
| 410 | { |
| 411 | return rom_api_table; |
| 412 | } |
| 413 | |
| 414 | uintptr_t get_stm32mp_bl2_dtb(void) |
| 415 | { |
| 416 | return nt_fw_dtb; |
| 417 | } |
Marek Vasut | 7cf2c33 | 2023-01-12 18:58:41 +0100 | [diff] [blame] | 418 | |
| 419 | #ifdef CONFIG_SPL_BUILD |
| 420 | void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) |
| 421 | { |
| 422 | typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); |
| 423 | uintptr_t romapi = get_stm32mp_rom_api_table(); |
| 424 | |
| 425 | image_entry_stm32_t image_entry = |
| 426 | (image_entry_stm32_t)spl_image->entry_point; |
| 427 | |
| 428 | printf("image entry point: 0x%lx\n", spl_image->entry_point); |
| 429 | image_entry(romapi); |
| 430 | } |
| 431 | #endif |