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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +03002/*
3 * board/renesas/silk/silk.c
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +03007 */
8
9#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -070010#include <cpu_func.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -060011#include <env.h>
Simon Glassf11478f2019-12-28 10:45:07 -070012#include <hang.h>
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030013#include <malloc.h>
Nobuhiro Iwamatsufafe6e92014-12-09 16:20:04 +090014#include <dm.h>
15#include <dm/platform_data/serial_sh.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060016#include <env_internal.h>
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030017#include <asm/processor.h>
18#include <asm/mach-types.h>
19#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090020#include <linux/errno.h>
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030021#include <asm/arch/sys_proto.h>
22#include <asm/gpio.h>
23#include <asm/arch/rmobile.h>
24#include <asm/arch/rcar-mstp.h>
25#include <asm/arch/mmc.h>
Vladimir Barinovc5951332015-02-24 18:55:46 +020026#include <asm/arch/sh_sdhi.h>
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030027#include <netdev.h>
28#include <miiphy.h>
29#include <i2c.h>
30#include <div64.h>
31#include "qos.h"
32
33DECLARE_GLOBAL_DATA_PTR;
34
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030035void s_init(void)
36{
37 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
38 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
39
40 /* Watchdog init */
41 writel(0xA5A5A500, &rwdt->rwtcsra);
42 writel(0xA5A5A500, &swdt->swtcsra);
43
44 /* QoS */
45 qos_init();
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030046}
47
Marek Vasut52e0ee32018-04-21 16:19:56 +020048#define TMU0_MSTP125 BIT(25)
49#define MMC0_MSTP315 BIT(15)
Vladimir Barinovc5951332015-02-24 18:55:46 +020050
51#define SD1CKCR 0xE6150078
Marek Vasut52e0ee32018-04-21 16:19:56 +020052#define SD_97500KHZ 0x7
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030053
54int board_early_init_f(void)
55{
56 /* TMU */
57 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
58
Marek Vasut52e0ee32018-04-21 16:19:56 +020059 /* Set SD1 to the 97.5MHz */
60 writel(SD_97500KHZ, SD1CKCR);
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030061
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030062 return 0;
63}
64
Marek Vasut52e0ee32018-04-21 16:19:56 +020065#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
66
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030067int board_init(void)
68{
69 /* adress of boot parameters */
70 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
71
Marek Vasut52e0ee32018-04-21 16:19:56 +020072 /* Force ethernet PHY out of reset */
73 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
74 gpio_direction_output(ETHERNET_PHY_RESET, 0);
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030075 mdelay(20);
Marek Vasut52e0ee32018-04-21 16:19:56 +020076 gpio_direction_output(ETHERNET_PHY_RESET, 1);
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030077 udelay(1);
78
79 return 0;
80}
81
Marek Vasut52e0ee32018-04-21 16:19:56 +020082int dram_init(void)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030083{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053084 if (fdtdec_setup_mem_size_base() != 0)
Marek Vasut52e0ee32018-04-21 16:19:56 +020085 return -EINVAL;
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030086
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030087 return 0;
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030088}
89
Marek Vasut52e0ee32018-04-21 16:19:56 +020090int dram_init_banksize(void)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030091{
Marek Vasut52e0ee32018-04-21 16:19:56 +020092 fdtdec_setup_memory_banksize();
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030093
Marek Vasut52e0ee32018-04-21 16:19:56 +020094 return 0;
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030095}
96
Marek Vasut52e0ee32018-04-21 16:19:56 +020097/* porter has KSZ8041RNLI */
98#define PHY_CONTROL1 0x1E
Marek Vasut9580a452019-03-30 07:05:09 +010099#define PHY_LED_MODE 0xC000
Marek Vasut52e0ee32018-04-21 16:19:56 +0200100#define PHY_LED_MODE_ACK 0x4000
101int board_phy_config(struct phy_device *phydev)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +0300102{
Marek Vasut52e0ee32018-04-21 16:19:56 +0200103 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
104 ret &= ~PHY_LED_MODE;
105 ret |= PHY_LED_MODE_ACK;
106 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +0300107
108 return 0;
109}
110
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +0300111void reset_cpu(ulong addr)
112{
Marek Vasut52e0ee32018-04-21 16:19:56 +0200113 struct udevice *dev;
114 const u8 pmic_bus = 1;
Marek Vasutfbea8812018-04-22 04:44:05 +0200115 const u8 pmic_addr = 0x5a;
Marek Vasut52e0ee32018-04-21 16:19:56 +0200116 u8 data;
117 int ret;
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +0300118
Marek Vasut52e0ee32018-04-21 16:19:56 +0200119 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
120 if (ret)
121 hang();
122
123 ret = dm_i2c_read(dev, 0x13, &data, 1);
124 if (ret)
125 hang();
126
127 data |= BIT(1);
128
129 ret = dm_i2c_write(dev, 0x13, &data, 1);
130 if (ret)
131 hang();
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +0300132}
Nobuhiro Iwamatsufafe6e92014-12-09 16:20:04 +0900133
Marek Vasut52e0ee32018-04-21 16:19:56 +0200134enum env_location env_get_location(enum env_operation op, int prio)
135{
136 const u32 load_magic = 0xb33fc0de;
Nobuhiro Iwamatsufafe6e92014-12-09 16:20:04 +0900137
Marek Vasut52e0ee32018-04-21 16:19:56 +0200138 /* Block environment access if loaded using JTAG */
139 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
140 (op != ENVOP_INIT))
141 return ENVL_UNKNOWN;
142
143 if (prio)
144 return ENVL_UNKNOWN;
145
146 return ENVL_SPI_FLASH;
147}