blob: f3ac8c75831ee7fe3c5e17b49b70ced8b8332ffe [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01004 */
5
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01006#define LOG_CATEGORY UCLASS_CLK
7
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01008#include <common.h>
9#include <clk-uclass.h>
10#include <div64.h>
11#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010014#include <regmap.h>
15#include <spl.h>
16#include <syscon.h>
Simon Glass495a5dc2019-11-14 12:57:30 -070017#include <time.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070018#include <vsprintf.h>
Patrick Delaunay885bdc22020-05-25 12:19:44 +020019#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060020#include <asm/global_data.h>
Patrick Delaunay30cd91e2020-11-06 19:01:45 +010021#include <dm/device_compat.h>
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010022#include <dt-bindings/clock/stm32mp1-clks.h>
Patrick Delaunayf11398e2018-03-12 10:46:16 +010023#include <dt-bindings/clock/stm32mp1-clksrc.h>
Patrick Delaunay30cd91e2020-11-06 19:01:45 +010024#include <linux/bitops.h>
25#include <linux/io.h>
26#include <linux/iopoll.h>
Patrick Delaunayf11398e2018-03-12 10:46:16 +010027
Patrick Delaunaya77c6ed2019-07-30 19:16:55 +020028DECLARE_GLOBAL_DATA_PTR;
29
Patrick Delaunay72a57622021-10-11 09:52:50 +020030#if defined(CONFIG_SPL_BUILD)
Patrick Delaunayf11398e2018-03-12 10:46:16 +010031/* activate clock tree initialization in the driver */
32#define STM32MP1_CLOCK_TREE_INIT
33#endif
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010034
35#define MAX_HSI_HZ 64000000
36
Patrick Delaunayf11398e2018-03-12 10:46:16 +010037/* TIMEOUT */
38#define TIMEOUT_200MS 200000
39#define TIMEOUT_1S 1000000
40
Patrick Delaunaybf7d9442018-03-20 11:41:25 +010041/* STGEN registers */
42#define STGENC_CNTCR 0x00
43#define STGENC_CNTSR 0x04
44#define STGENC_CNTCVL 0x08
45#define STGENC_CNTCVU 0x0C
46#define STGENC_CNTFID0 0x20
47
48#define STGENC_CNTCR_EN BIT(0)
49
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010050/* RCC registers */
51#define RCC_OCENSETR 0x0C
52#define RCC_OCENCLRR 0x10
53#define RCC_HSICFGR 0x18
54#define RCC_MPCKSELR 0x20
55#define RCC_ASSCKSELR 0x24
56#define RCC_RCK12SELR 0x28
57#define RCC_MPCKDIVR 0x2C
58#define RCC_AXIDIVR 0x30
59#define RCC_APB4DIVR 0x3C
60#define RCC_APB5DIVR 0x40
61#define RCC_RTCDIVR 0x44
62#define RCC_MSSCKSELR 0x48
63#define RCC_PLL1CR 0x80
64#define RCC_PLL1CFGR1 0x84
65#define RCC_PLL1CFGR2 0x88
66#define RCC_PLL1FRACR 0x8C
67#define RCC_PLL1CSGR 0x90
68#define RCC_PLL2CR 0x94
69#define RCC_PLL2CFGR1 0x98
70#define RCC_PLL2CFGR2 0x9C
71#define RCC_PLL2FRACR 0xA0
72#define RCC_PLL2CSGR 0xA4
73#define RCC_I2C46CKSELR 0xC0
Patrick Delaunaydcd705e2021-07-09 14:24:34 +020074#define RCC_SPI6CKSELR 0xC4
Anatolij Gustschinb62c75d2023-09-29 13:34:37 +020075#define RCC_UART1CKSELR 0xC8
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010076#define RCC_CPERCKSELR 0xD0
77#define RCC_STGENCKSELR 0xD4
78#define RCC_DDRITFCR 0xD8
79#define RCC_BDCR 0x140
80#define RCC_RDLSICR 0x144
81#define RCC_MP_APB4ENSETR 0x200
82#define RCC_MP_APB5ENSETR 0x208
83#define RCC_MP_AHB5ENSETR 0x210
84#define RCC_MP_AHB6ENSETR 0x218
85#define RCC_OCRDYR 0x808
86#define RCC_DBGCFGR 0x80C
87#define RCC_RCK3SELR 0x820
88#define RCC_RCK4SELR 0x824
89#define RCC_MCUDIVR 0x830
90#define RCC_APB1DIVR 0x834
91#define RCC_APB2DIVR 0x838
92#define RCC_APB3DIVR 0x83C
93#define RCC_PLL3CR 0x880
94#define RCC_PLL3CFGR1 0x884
95#define RCC_PLL3CFGR2 0x888
96#define RCC_PLL3FRACR 0x88C
97#define RCC_PLL3CSGR 0x890
98#define RCC_PLL4CR 0x894
99#define RCC_PLL4CFGR1 0x898
100#define RCC_PLL4CFGR2 0x89C
101#define RCC_PLL4FRACR 0x8A0
102#define RCC_PLL4CSGR 0x8A4
103#define RCC_I2C12CKSELR 0x8C0
104#define RCC_I2C35CKSELR 0x8C4
Patrice Chotard08ca06b2019-04-30 18:08:27 +0200105#define RCC_SPI2S1CKSELR 0x8D8
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200106#define RCC_SPI2S23CKSELR 0x8DC
Patrick Delaunay0b859a02020-03-09 14:59:23 +0100107#define RCC_SPI45CKSELR 0x8E0
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100108#define RCC_UART6CKSELR 0x8E4
109#define RCC_UART24CKSELR 0x8E8
110#define RCC_UART35CKSELR 0x8EC
111#define RCC_UART78CKSELR 0x8F0
112#define RCC_SDMMC12CKSELR 0x8F4
113#define RCC_SDMMC3CKSELR 0x8F8
114#define RCC_ETHCKSELR 0x8FC
115#define RCC_QSPICKSELR 0x900
116#define RCC_FMCCKSELR 0x904
117#define RCC_USBCKSELR 0x91C
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200118#define RCC_DSICKSELR 0x924
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200119#define RCC_ADCCKSELR 0x928
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100120#define RCC_MP_APB1ENSETR 0xA00
121#define RCC_MP_APB2ENSETR 0XA08
Fabrice Gasnier4cb3b532018-04-26 17:00:47 +0200122#define RCC_MP_APB3ENSETR 0xA10
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100123#define RCC_MP_AHB2ENSETR 0xA18
Benjamin Gaignard32470812018-11-27 13:49:51 +0100124#define RCC_MP_AHB3ENSETR 0xA20
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100125#define RCC_MP_AHB4ENSETR 0xA28
126
127/* used for most of SELR register */
128#define RCC_SELR_SRC_MASK GENMASK(2, 0)
129#define RCC_SELR_SRCRDY BIT(31)
130
131/* Values of RCC_MPCKSELR register */
132#define RCC_MPCKSELR_HSI 0
133#define RCC_MPCKSELR_HSE 1
134#define RCC_MPCKSELR_PLL 2
135#define RCC_MPCKSELR_PLL_MPUDIV 3
136
137/* Values of RCC_ASSCKSELR register */
138#define RCC_ASSCKSELR_HSI 0
139#define RCC_ASSCKSELR_HSE 1
140#define RCC_ASSCKSELR_PLL 2
141
142/* Values of RCC_MSSCKSELR register */
143#define RCC_MSSCKSELR_HSI 0
144#define RCC_MSSCKSELR_HSE 1
145#define RCC_MSSCKSELR_CSI 2
146#define RCC_MSSCKSELR_PLL 3
147
148/* Values of RCC_CPERCKSELR register */
149#define RCC_CPERCKSELR_HSI 0
150#define RCC_CPERCKSELR_CSI 1
151#define RCC_CPERCKSELR_HSE 2
152
153/* used for most of DIVR register : max div for RTC */
154#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
155#define RCC_DIVR_DIVRDY BIT(31)
156
157/* Masks for specific DIVR registers */
158#define RCC_APBXDIV_MASK GENMASK(2, 0)
159#define RCC_MPUDIV_MASK GENMASK(2, 0)
160#define RCC_AXIDIV_MASK GENMASK(2, 0)
161#define RCC_MCUDIV_MASK GENMASK(3, 0)
162
163/* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
164#define RCC_MP_ENCLRR_OFFSET 4
165
166/* Fields of RCC_BDCR register */
167#define RCC_BDCR_LSEON BIT(0)
168#define RCC_BDCR_LSEBYP BIT(1)
169#define RCC_BDCR_LSERDY BIT(2)
Patrick Delaunay80cb5682018-07-16 10:41:46 +0200170#define RCC_BDCR_DIGBYP BIT(3)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100171#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
172#define RCC_BDCR_LSEDRV_SHIFT 4
173#define RCC_BDCR_LSECSSON BIT(8)
174#define RCC_BDCR_RTCCKEN BIT(20)
175#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
176#define RCC_BDCR_RTCSRC_SHIFT 16
177
178/* Fields of RCC_RDLSICR register */
179#define RCC_RDLSICR_LSION BIT(0)
180#define RCC_RDLSICR_LSIRDY BIT(1)
181
182/* used for ALL PLLNCR registers */
183#define RCC_PLLNCR_PLLON BIT(0)
184#define RCC_PLLNCR_PLLRDY BIT(1)
Patrick Delaunay9a6ce2a2019-01-30 13:07:06 +0100185#define RCC_PLLNCR_SSCG_CTRL BIT(2)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100186#define RCC_PLLNCR_DIVPEN BIT(4)
187#define RCC_PLLNCR_DIVQEN BIT(5)
188#define RCC_PLLNCR_DIVREN BIT(6)
189#define RCC_PLLNCR_DIVEN_SHIFT 4
190
191/* used for ALL PLLNCFGR1 registers */
192#define RCC_PLLNCFGR1_DIVM_SHIFT 16
193#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
194#define RCC_PLLNCFGR1_DIVN_SHIFT 0
195#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
196/* only for PLL3 and PLL4 */
197#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
198#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
199
Patrick Delaunaya7c0fd62018-07-16 10:41:41 +0200200/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
201#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100202#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
Patrick Delaunaya7c0fd62018-07-16 10:41:41 +0200203#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100204#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
Patrick Delaunaya7c0fd62018-07-16 10:41:41 +0200205#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100206#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
Patrick Delaunaya7c0fd62018-07-16 10:41:41 +0200207#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100208#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
209
210/* used for ALL PLLNFRACR registers */
211#define RCC_PLLNFRACR_FRACV_SHIFT 3
212#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
213#define RCC_PLLNFRACR_FRACLE BIT(16)
214
215/* used for ALL PLLNCSGR registers */
216#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
217#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
218#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
219#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
220#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
221#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
222
223/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
224#define RCC_OCENR_HSION BIT(0)
225#define RCC_OCENR_CSION BIT(4)
Patrick Delaunay80cb5682018-07-16 10:41:46 +0200226#define RCC_OCENR_DIGBYP BIT(7)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100227#define RCC_OCENR_HSEON BIT(8)
228#define RCC_OCENR_HSEBYP BIT(10)
229#define RCC_OCENR_HSECSSON BIT(11)
230
231/* Fields of RCC_OCRDYR register */
232#define RCC_OCRDYR_HSIRDY BIT(0)
233#define RCC_OCRDYR_HSIDIVRDY BIT(2)
234#define RCC_OCRDYR_CSIRDY BIT(4)
235#define RCC_OCRDYR_HSERDY BIT(8)
236
237/* Fields of DDRITFCR register */
238#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
239#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
240#define RCC_DDRITFCR_DDRCKMOD_SSR 0
241
242/* Fields of RCC_HSICFGR register */
243#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
244
245/* used for MCO related operations */
246#define RCC_MCOCFG_MCOON BIT(12)
247#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
248#define RCC_MCOCFG_MCODIV_SHIFT 4
249#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
250
251enum stm32mp1_parent_id {
252/*
253 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
Etienne Carriere55a78142021-02-24 11:19:42 +0100254 * they are used as index in osc_clk[] as clock reference
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100255 */
256 _HSI,
257 _HSE,
258 _CSI,
259 _LSI,
260 _LSE,
261 _I2S_CKIN,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100262 NB_OSC,
263
264/* other parent source */
265 _HSI_KER = NB_OSC,
266 _HSE_KER,
267 _HSE_KER_DIV2,
268 _CSI_KER,
269 _PLL1_P,
270 _PLL1_Q,
271 _PLL1_R,
272 _PLL2_P,
273 _PLL2_Q,
274 _PLL2_R,
275 _PLL3_P,
276 _PLL3_Q,
277 _PLL3_R,
278 _PLL4_P,
279 _PLL4_Q,
280 _PLL4_R,
281 _ACLK,
282 _PCLK1,
283 _PCLK2,
284 _PCLK3,
285 _PCLK4,
286 _PCLK5,
287 _HCLK6,
288 _HCLK2,
289 _CK_PER,
290 _CK_MPU,
291 _CK_MCU,
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200292 _DSI_PHY,
Patrick Delaunay7b726532019-01-30 13:07:00 +0100293 _USB_PHY_48,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100294 _PARENT_NB,
295 _UNKNOWN_ID = 0xff,
296};
297
298enum stm32mp1_parent_sel {
299 _I2C12_SEL,
300 _I2C35_SEL,
301 _I2C46_SEL,
302 _UART6_SEL,
303 _UART24_SEL,
304 _UART35_SEL,
305 _UART78_SEL,
306 _SDMMC12_SEL,
307 _SDMMC3_SEL,
308 _ETH_SEL,
309 _QSPI_SEL,
310 _FMC_SEL,
311 _USBPHY_SEL,
312 _USBO_SEL,
313 _STGEN_SEL,
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200314 _DSI_SEL,
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200315 _ADC12_SEL,
Patrice Chotard08ca06b2019-04-30 18:08:27 +0200316 _SPI1_SEL,
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200317 _SPI23_SEL,
Patrick Delaunay0b859a02020-03-09 14:59:23 +0100318 _SPI45_SEL,
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200319 _SPI6_SEL,
Patrick Delaunay03d87aa2019-07-11 12:03:37 +0200320 _RTC_SEL,
Anatolij Gustschinb62c75d2023-09-29 13:34:37 +0200321 _UART1_SEL,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100322 _PARENT_SEL_NB,
323 _UNKNOWN_SEL = 0xff,
324};
325
326enum stm32mp1_pll_id {
327 _PLL1,
328 _PLL2,
329 _PLL3,
330 _PLL4,
331 _PLL_NB
332};
333
334enum stm32mp1_div_id {
335 _DIV_P,
336 _DIV_Q,
337 _DIV_R,
338 _DIV_NB,
339};
340
341enum stm32mp1_clksrc_id {
342 CLKSRC_MPU,
343 CLKSRC_AXI,
344 CLKSRC_MCU,
345 CLKSRC_PLL12,
346 CLKSRC_PLL3,
347 CLKSRC_PLL4,
348 CLKSRC_RTC,
349 CLKSRC_MCO1,
350 CLKSRC_MCO2,
351 CLKSRC_NB
352};
353
354enum stm32mp1_clkdiv_id {
355 CLKDIV_MPU,
356 CLKDIV_AXI,
357 CLKDIV_MCU,
358 CLKDIV_APB1,
359 CLKDIV_APB2,
360 CLKDIV_APB3,
361 CLKDIV_APB4,
362 CLKDIV_APB5,
363 CLKDIV_RTC,
364 CLKDIV_MCO1,
365 CLKDIV_MCO2,
366 CLKDIV_NB
367};
368
369enum stm32mp1_pllcfg {
370 PLLCFG_M,
371 PLLCFG_N,
372 PLLCFG_P,
373 PLLCFG_Q,
374 PLLCFG_R,
375 PLLCFG_O,
376 PLLCFG_NB
377};
378
379enum stm32mp1_pllcsg {
380 PLLCSG_MOD_PER,
381 PLLCSG_INC_STEP,
382 PLLCSG_SSCG_MODE,
383 PLLCSG_NB
384};
385
386enum stm32mp1_plltype {
387 PLL_800,
388 PLL_1600,
389 PLL_TYPE_NB
390};
391
392struct stm32mp1_pll {
393 u8 refclk_min;
394 u8 refclk_max;
395 u8 divn_max;
396};
397
398struct stm32mp1_clk_gate {
399 u16 offset;
400 u8 bit;
401 u8 index;
402 u8 set_clr;
403 u8 sel;
404 u8 fixed;
405};
406
407struct stm32mp1_clk_sel {
408 u16 offset;
409 u8 src;
410 u8 msk;
411 u8 nb_parent;
412 const u8 *parent;
413};
414
415#define REFCLK_SIZE 4
416struct stm32mp1_clk_pll {
417 enum stm32mp1_plltype plltype;
418 u16 rckxselr;
419 u16 pllxcfgr1;
420 u16 pllxcfgr2;
421 u16 pllxfracr;
422 u16 pllxcr;
423 u16 pllxcsgr;
424 u8 refclk[REFCLK_SIZE];
425};
426
427struct stm32mp1_clk_data {
428 const struct stm32mp1_clk_gate *gate;
429 const struct stm32mp1_clk_sel *sel;
430 const struct stm32mp1_clk_pll *pll;
431 const int nb_gate;
432};
433
434struct stm32mp1_clk_priv {
435 fdt_addr_t base;
436 const struct stm32mp1_clk_data *data;
Etienne Carriere55a78142021-02-24 11:19:42 +0100437 struct clk osc_clk[NB_OSC];
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100438};
439
440#define STM32MP1_CLK(off, b, idx, s) \
441 { \
442 .offset = (off), \
443 .bit = (b), \
444 .index = (idx), \
445 .set_clr = 0, \
446 .sel = (s), \
447 .fixed = _UNKNOWN_ID, \
448 }
449
450#define STM32MP1_CLK_F(off, b, idx, f) \
451 { \
452 .offset = (off), \
453 .bit = (b), \
454 .index = (idx), \
455 .set_clr = 0, \
456 .sel = _UNKNOWN_SEL, \
457 .fixed = (f), \
458 }
459
460#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
461 { \
462 .offset = (off), \
463 .bit = (b), \
464 .index = (idx), \
465 .set_clr = 1, \
466 .sel = (s), \
467 .fixed = _UNKNOWN_ID, \
468 }
469
470#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
471 { \
472 .offset = (off), \
473 .bit = (b), \
474 .index = (idx), \
475 .set_clr = 1, \
476 .sel = _UNKNOWN_SEL, \
477 .fixed = (f), \
478 }
479
480#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
481 [(idx)] = { \
482 .offset = (off), \
483 .src = (s), \
484 .msk = (m), \
485 .parent = (p), \
486 .nb_parent = ARRAY_SIZE((p)) \
487 }
488
489#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
490 p1, p2, p3, p4) \
491 [(idx)] = { \
492 .plltype = (type), \
493 .rckxselr = (off1), \
494 .pllxcfgr1 = (off2), \
495 .pllxcfgr2 = (off3), \
496 .pllxfracr = (off4), \
497 .pllxcr = (off5), \
498 .pllxcsgr = (off6), \
499 .refclk[0] = (p1), \
500 .refclk[1] = (p2), \
501 .refclk[2] = (p3), \
502 .refclk[3] = (p4), \
503 }
504
505static const u8 stm32mp1_clks[][2] = {
506 {CK_PER, _CK_PER},
507 {CK_MPU, _CK_MPU},
508 {CK_AXI, _ACLK},
509 {CK_MCU, _CK_MCU},
510 {CK_HSE, _HSE},
511 {CK_CSI, _CSI},
512 {CK_LSI, _LSI},
513 {CK_LSE, _LSE},
514 {CK_HSI, _HSI},
515 {CK_HSE_DIV2, _HSE_KER_DIV2},
516};
517
518static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
519 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
520 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
521 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
522 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
523 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
524 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
525 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
526 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
527 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
528 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
529 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
530
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200531 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 11, SPI2_K, _SPI23_SEL),
532 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 12, SPI3_K, _SPI23_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100533 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
534 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
535 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
536 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
537 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
538 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
539 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
540 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
541 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
542 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
543
Patrice Chotard08ca06b2019-04-30 18:08:27 +0200544 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200545 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 9, SPI4_K, _SPI45_SEL),
Patrick Delaunay0b859a02020-03-09 14:59:23 +0100546 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100547 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
548
Fabrice Gasnier4cb3b532018-04-26 17:00:47 +0200549 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
Patrick Delaunayc7d146d2021-06-29 12:04:22 +0200550 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_SEL),
Fabrice Gasnier4cb3b532018-04-26 17:00:47 +0200551
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200552 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
553 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
554 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100555 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
556 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
557 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
558
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200559 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100560 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
Patrick Delaunay5c0ea512021-01-22 15:34:25 +0100561 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
Anatolij Gustschinb62c75d2023-09-29 13:34:37 +0200562 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
Patrick Delaunay03d87aa2019-07-11 12:03:37 +0200563 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
Patrick Delaunayd69d1742021-07-16 10:10:55 +0200564 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100565 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
566
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200567 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
568 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100569 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
570 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
571
Benjamin Gaignard32470812018-11-27 13:49:51 +0100572 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
Patrick Delaunay629f44f2019-01-30 13:07:01 +0100573 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
Benjamin Gaignard32470812018-11-27 13:49:51 +0100574
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100575 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
576 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
577 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
578 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
579 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
580 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
581 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
582 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
583 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
584 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
585 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
586
587 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
Sughosh Ganu1b725012019-12-28 23:58:28 +0530588 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100589
Patrick Delaunay5bfc8702019-05-17 15:08:42 +0200590 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100591 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
592 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100593 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
594 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
595 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
596 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
597 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
598 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
599
600 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
Patrick Delaunay03d87aa2019-07-11 12:03:37 +0200601
602 STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100603};
604
605static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
606static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
607static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
Anatolij Gustschinb62c75d2023-09-29 13:34:37 +0200608static const u8 uart1_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER,
609 _PLL4_Q, _HSE_KER};
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100610static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
611 _HSE_KER};
612static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
613 _HSE_KER};
614static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
615 _HSE_KER};
616static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
617 _HSE_KER};
618static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
619static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
620static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
621static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
622static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
623static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
624static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
625static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200626static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200627static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200628/* same parents for SPI1=RCC_SPI2S1CKSELR and SPI2&3 = RCC_SPI2S23CKSELR */
Patrice Chotard08ca06b2019-04-30 18:08:27 +0200629static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
630 _PLL3_R};
Patrick Delaunay0b859a02020-03-09 14:59:23 +0100631static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
632 _HSE_KER};
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200633static const u8 spi6_parents[] = {_PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER,
634 _HSE_KER, _PLL3_Q};
Patrick Delaunay03d87aa2019-07-11 12:03:37 +0200635static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100636
637static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
638 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
639 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
640 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
641 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
642 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
643 uart24_parents),
644 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
645 uart35_parents),
646 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
647 uart78_parents),
648 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
649 sdmmc12_parents),
650 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
651 sdmmc3_parents),
652 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
Patrick Delaunay95e7fbe2020-03-09 14:59:22 +0100653 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
654 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100655 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
656 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
657 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200658 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
Patrick Delaunay95e7fbe2020-03-09 14:59:22 +0100659 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
Patrice Chotard08ca06b2019-04-30 18:08:27 +0200660 STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200661 STM32MP1_CLK_PARENT(_SPI23_SEL, RCC_SPI2S23CKSELR, 0, 0x7, spi_parents),
Patrick Delaunay0b859a02020-03-09 14:59:23 +0100662 STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
Patrick Delaunaydcd705e2021-07-09 14:24:34 +0200663 STM32MP1_CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
Patrick Delaunay03d87aa2019-07-11 12:03:37 +0200664 STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
665 (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
666 rtc_parents),
Anatolij Gustschinb62c75d2023-09-29 13:34:37 +0200667 STM32MP1_CLK_PARENT(_UART1_SEL, RCC_UART1CKSELR, 0, 0x7, uart1_parents),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100668};
669
670#ifdef STM32MP1_CLOCK_TREE_INIT
Patrick Delaunay885bdc22020-05-25 12:19:44 +0200671
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100672/* define characteristic of PLL according type */
Patrick Delaunay885bdc22020-05-25 12:19:44 +0200673#define DIVM_MIN 0
674#define DIVM_MAX 63
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100675#define DIVN_MIN 24
Patrick Delaunay885bdc22020-05-25 12:19:44 +0200676#define DIVP_MIN 0
677#define DIVP_MAX 127
678#define FRAC_MAX 8192
679
680#define PLL1600_VCO_MIN 800000000
681#define PLL1600_VCO_MAX 1600000000
682
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100683static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
684 [PLL_800] = {
685 .refclk_min = 4,
686 .refclk_max = 16,
687 .divn_max = 99,
688 },
689 [PLL_1600] = {
690 .refclk_min = 8,
691 .refclk_max = 16,
692 .divn_max = 199,
693 },
694};
695#endif /* STM32MP1_CLOCK_TREE_INIT */
696
697static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
698 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
699 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
700 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
701 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
702 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
703 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
704 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
705 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
706 STM32MP1_CLK_PLL(_PLL3, PLL_800,
707 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
708 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
709 _HSI, _HSE, _CSI, _UNKNOWN_ID),
710 STM32MP1_CLK_PLL(_PLL4, PLL_800,
711 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
712 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
713 _HSI, _HSE, _CSI, _I2S_CKIN),
714};
715
716/* Prescaler table lookups for clock computation */
717/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
718static const u8 stm32mp1_mcu_div[16] = {
719 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
720};
721
722/* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
723#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
724#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
725static const u8 stm32mp1_mpu_apbx_div[8] = {
726 0, 1, 2, 3, 4, 4, 4, 4
727};
728
729/* div = /1 /2 /3 /4 */
730static const u8 stm32mp1_axi_div[8] = {
731 1, 2, 3, 4, 4, 4, 4, 4
732};
733
Patrick Delaunaye8d836c2019-01-30 13:07:04 +0100734static const __maybe_unused
735char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100736 [_HSI] = "HSI",
737 [_HSE] = "HSE",
738 [_CSI] = "CSI",
739 [_LSI] = "LSI",
740 [_LSE] = "LSE",
741 [_I2S_CKIN] = "I2S_CKIN",
742 [_HSI_KER] = "HSI_KER",
743 [_HSE_KER] = "HSE_KER",
744 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
745 [_CSI_KER] = "CSI_KER",
746 [_PLL1_P] = "PLL1_P",
747 [_PLL1_Q] = "PLL1_Q",
748 [_PLL1_R] = "PLL1_R",
749 [_PLL2_P] = "PLL2_P",
750 [_PLL2_Q] = "PLL2_Q",
751 [_PLL2_R] = "PLL2_R",
752 [_PLL3_P] = "PLL3_P",
753 [_PLL3_Q] = "PLL3_Q",
754 [_PLL3_R] = "PLL3_R",
755 [_PLL4_P] = "PLL4_P",
756 [_PLL4_Q] = "PLL4_Q",
757 [_PLL4_R] = "PLL4_R",
758 [_ACLK] = "ACLK",
759 [_PCLK1] = "PCLK1",
760 [_PCLK2] = "PCLK2",
761 [_PCLK3] = "PCLK3",
762 [_PCLK4] = "PCLK4",
763 [_PCLK5] = "PCLK5",
764 [_HCLK6] = "KCLK6",
765 [_HCLK2] = "HCLK2",
766 [_CK_PER] = "CK_PER",
767 [_CK_MPU] = "CK_MPU",
768 [_CK_MCU] = "CK_MCU",
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200769 [_USB_PHY_48] = "USB_PHY_48",
770 [_DSI_PHY] = "DSI_PHY_PLL",
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100771};
772
Patrick Delaunaye8d836c2019-01-30 13:07:04 +0100773static const __maybe_unused
774char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100775 [_I2C12_SEL] = "I2C12",
776 [_I2C35_SEL] = "I2C35",
777 [_I2C46_SEL] = "I2C46",
778 [_UART6_SEL] = "UART6",
779 [_UART24_SEL] = "UART24",
780 [_UART35_SEL] = "UART35",
781 [_UART78_SEL] = "UART78",
782 [_SDMMC12_SEL] = "SDMMC12",
783 [_SDMMC3_SEL] = "SDMMC3",
784 [_ETH_SEL] = "ETH",
785 [_QSPI_SEL] = "QSPI",
786 [_FMC_SEL] = "FMC",
787 [_USBPHY_SEL] = "USBPHY",
788 [_USBO_SEL] = "USBO",
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200789 [_STGEN_SEL] = "STGEN",
790 [_DSI_SEL] = "DSI",
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200791 [_ADC12_SEL] = "ADC12",
Patrice Chotard08ca06b2019-04-30 18:08:27 +0200792 [_SPI1_SEL] = "SPI1",
Patrick Delaunay0b859a02020-03-09 14:59:23 +0100793 [_SPI45_SEL] = "SPI45",
Patrick Delaunay03d87aa2019-07-11 12:03:37 +0200794 [_RTC_SEL] = "RTC",
Anatolij Gustschinb62c75d2023-09-29 13:34:37 +0200795 [_UART1_SEL] = "UART1",
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100796};
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100797
798static const struct stm32mp1_clk_data stm32mp1_data = {
799 .gate = stm32mp1_clk_gate,
800 .sel = stm32mp1_clk_sel,
801 .pll = stm32mp1_clk_pll,
802 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
803};
804
805static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
806{
807 if (idx >= NB_OSC) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +0100808 log_debug("clk id %d not found\n", idx);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100809 return 0;
810 }
811
Etienne Carriere55a78142021-02-24 11:19:42 +0100812 return clk_get_rate(&priv->osc_clk[idx]);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100813}
814
815static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
816{
817 const struct stm32mp1_clk_gate *gate = priv->data->gate;
818 int i, nb_clks = priv->data->nb_gate;
819
820 for (i = 0; i < nb_clks; i++) {
821 if (gate[i].index == id)
822 break;
823 }
824
825 if (i == nb_clks) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +0100826 log_err("clk id %d not found\n", (u32)id);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100827 return -EINVAL;
828 }
829
830 return i;
831}
832
833static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
834 int i)
835{
836 const struct stm32mp1_clk_gate *gate = priv->data->gate;
837
838 if (gate[i].sel > _PARENT_SEL_NB) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +0100839 log_err("parents for clk id %d not found\n", i);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100840 return -EINVAL;
841 }
842
843 return gate[i].sel;
844}
845
846static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
847 int i)
848{
849 const struct stm32mp1_clk_gate *gate = priv->data->gate;
850
851 if (gate[i].fixed == _UNKNOWN_ID)
852 return -ENOENT;
853
854 return gate[i].fixed;
855}
856
857static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
858 unsigned long id)
859{
860 const struct stm32mp1_clk_sel *sel = priv->data->sel;
861 int i;
862 int s, p;
Patrick Delaunay942ee232019-06-21 15:26:48 +0200863 unsigned int idx;
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100864
Patrick Delaunay942ee232019-06-21 15:26:48 +0200865 for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
866 if (stm32mp1_clks[idx][0] == id)
867 return stm32mp1_clks[idx][1];
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100868
869 i = stm32mp1_clk_get_id(priv, id);
870 if (i < 0)
871 return i;
872
873 p = stm32mp1_clk_get_fixed_parent(priv, i);
874 if (p >= 0 && p < _PARENT_NB)
875 return p;
876
877 s = stm32mp1_clk_get_sel(priv, i);
878 if (s < 0)
879 return s;
880
881 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
882
883 if (p < sel[s].nb_parent) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +0100884 log_content("%s clock is the parent %s of clk id %d\n",
885 stm32mp1_clk_parent_name[sel[s].parent[p]],
886 stm32mp1_clk_parent_sel_name[s],
887 (u32)id);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100888 return sel[s].parent[p];
889 }
890
Patrick Delaunay4e183072023-06-23 15:05:16 +0200891 /* clock is DISABLED when the clock src is not in clk_parent[] range */
892 log_debug("no parents defined for clk id %d\n", (u32)id);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100893
894 return -EINVAL;
895}
896
Patrick Delaunay5327d372018-07-16 10:41:42 +0200897static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
898 int pll_id)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100899{
900 const struct stm32mp1_clk_pll *pll = priv->data->pll;
Patrick Delaunay5327d372018-07-16 10:41:42 +0200901 u32 selr;
902 int src;
903 ulong refclk;
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100904
Patrick Delaunay5327d372018-07-16 10:41:42 +0200905 /* Get current refclk */
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100906 selr = readl(priv->base + pll[pll_id].rckxselr);
Patrick Delaunay5327d372018-07-16 10:41:42 +0200907 src = selr & RCC_SELR_SRC_MASK;
908
909 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
Patrick Delaunay5327d372018-07-16 10:41:42 +0200910
911 return refclk;
912}
913
914/*
915 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
916 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
917 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
918 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
919 */
920static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
921 int pll_id)
922{
923 const struct stm32mp1_clk_pll *pll = priv->data->pll;
924 int divm, divn;
925 ulong refclk, fvco;
926 u32 cfgr1, fracr;
927
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100928 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100929 fracr = readl(priv->base + pll[pll_id].pllxfracr);
930
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100931 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
932 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100933
Patrick Delaunay5327d372018-07-16 10:41:42 +0200934 refclk = pll_get_fref_ck(priv, pll_id);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100935
Patrick Delaunay5327d372018-07-16 10:41:42 +0200936 /* with FRACV :
937 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100938 * without FRACV
Patrick Delaunay5327d372018-07-16 10:41:42 +0200939 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100940 */
941 if (fracr & RCC_PLLNFRACR_FRACLE) {
942 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
943 >> RCC_PLLNFRACR_FRACV_SHIFT;
Patrick Delaunay5327d372018-07-16 10:41:42 +0200944 fvco = (ulong)lldiv((unsigned long long)refclk *
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100945 (((divn + 1) << 13) + fracv),
Patrick Delaunay5327d372018-07-16 10:41:42 +0200946 ((unsigned long long)(divm + 1)) << 13);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100947 } else {
Patrick Delaunay5327d372018-07-16 10:41:42 +0200948 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100949 }
Patrick Delaunay5327d372018-07-16 10:41:42 +0200950
951 return fvco;
952}
953
954static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
955 int pll_id, int div_id)
956{
957 const struct stm32mp1_clk_pll *pll = priv->data->pll;
958 int divy;
959 ulong dfout;
960 u32 cfgr2;
961
Patrick Delaunay5327d372018-07-16 10:41:42 +0200962 if (div_id >= _DIV_NB)
963 return 0;
964
965 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
966 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
967
Patrick Delaunay5327d372018-07-16 10:41:42 +0200968 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100969
970 return dfout;
971}
972
Patrick Delaunay4a1b0832022-04-26 14:37:49 +0200973static ulong stm32mp1_clk_get_by_name(const char *name)
974{
975 struct clk clk;
976 struct udevice *dev = NULL;
977 ulong clock = 0;
978
979 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
980 if (clk_request(dev, &clk)) {
981 log_err("%s request", name);
982 } else {
983 clk.id = 0;
984 clock = clk_get_rate(&clk);
985 }
986 }
987
988 return clock;
989}
990
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100991static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
992{
993 u32 reg;
994 ulong clock = 0;
995
996 switch (p) {
997 case _CK_MPU:
998 /* MPU sub system */
999 reg = readl(priv->base + RCC_MPCKSELR);
1000 switch (reg & RCC_SELR_SRC_MASK) {
1001 case RCC_MPCKSELR_HSI:
1002 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1003 break;
1004 case RCC_MPCKSELR_HSE:
1005 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1006 break;
1007 case RCC_MPCKSELR_PLL:
1008 case RCC_MPCKSELR_PLL_MPUDIV:
1009 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
Lionel Debieve97289492020-04-24 15:47:57 +02001010 if ((reg & RCC_SELR_SRC_MASK) ==
1011 RCC_MPCKSELR_PLL_MPUDIV) {
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001012 reg = readl(priv->base + RCC_MPCKDIVR);
Lionel Debieve97289492020-04-24 15:47:57 +02001013 clock >>= stm32mp1_mpu_div[reg &
1014 RCC_MPUDIV_MASK];
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001015 }
1016 break;
1017 }
1018 break;
1019 /* AXI sub system */
1020 case _ACLK:
1021 case _HCLK2:
1022 case _HCLK6:
1023 case _PCLK4:
1024 case _PCLK5:
1025 reg = readl(priv->base + RCC_ASSCKSELR);
1026 switch (reg & RCC_SELR_SRC_MASK) {
1027 case RCC_ASSCKSELR_HSI:
1028 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1029 break;
1030 case RCC_ASSCKSELR_HSE:
1031 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1032 break;
1033 case RCC_ASSCKSELR_PLL:
1034 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
1035 break;
1036 }
1037
1038 /* System clock divider */
1039 reg = readl(priv->base + RCC_AXIDIVR);
1040 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
1041
1042 switch (p) {
1043 case _PCLK4:
1044 reg = readl(priv->base + RCC_APB4DIVR);
1045 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1046 break;
1047 case _PCLK5:
1048 reg = readl(priv->base + RCC_APB5DIVR);
1049 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1050 break;
1051 default:
1052 break;
1053 }
1054 break;
1055 /* MCU sub system */
1056 case _CK_MCU:
1057 case _PCLK1:
1058 case _PCLK2:
1059 case _PCLK3:
1060 reg = readl(priv->base + RCC_MSSCKSELR);
1061 switch (reg & RCC_SELR_SRC_MASK) {
1062 case RCC_MSSCKSELR_HSI:
1063 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1064 break;
1065 case RCC_MSSCKSELR_HSE:
1066 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1067 break;
1068 case RCC_MSSCKSELR_CSI:
1069 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1070 break;
1071 case RCC_MSSCKSELR_PLL:
1072 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
1073 break;
1074 }
1075
1076 /* MCU clock divider */
1077 reg = readl(priv->base + RCC_MCUDIVR);
1078 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1079
1080 switch (p) {
1081 case _PCLK1:
1082 reg = readl(priv->base + RCC_APB1DIVR);
1083 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1084 break;
1085 case _PCLK2:
1086 reg = readl(priv->base + RCC_APB2DIVR);
1087 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1088 break;
1089 case _PCLK3:
1090 reg = readl(priv->base + RCC_APB3DIVR);
1091 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1092 break;
1093 case _CK_MCU:
1094 default:
1095 break;
1096 }
1097 break;
1098 case _CK_PER:
1099 reg = readl(priv->base + RCC_CPERCKSELR);
1100 switch (reg & RCC_SELR_SRC_MASK) {
1101 case RCC_CPERCKSELR_HSI:
1102 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1103 break;
1104 case RCC_CPERCKSELR_HSE:
1105 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1106 break;
1107 case RCC_CPERCKSELR_CSI:
1108 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1109 break;
1110 }
1111 break;
1112 case _HSI:
1113 case _HSI_KER:
1114 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1115 break;
1116 case _CSI:
1117 case _CSI_KER:
1118 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1119 break;
1120 case _HSE:
1121 case _HSE_KER:
1122 case _HSE_KER_DIV2:
1123 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1124 if (p == _HSE_KER_DIV2)
1125 clock >>= 1;
1126 break;
1127 case _LSI:
1128 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1129 break;
1130 case _LSE:
1131 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1132 break;
1133 /* PLL */
1134 case _PLL1_P:
1135 case _PLL1_Q:
1136 case _PLL1_R:
1137 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1138 break;
1139 case _PLL2_P:
1140 case _PLL2_Q:
1141 case _PLL2_R:
1142 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1143 break;
1144 case _PLL3_P:
1145 case _PLL3_Q:
1146 case _PLL3_R:
1147 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1148 break;
1149 case _PLL4_P:
1150 case _PLL4_Q:
1151 case _PLL4_R:
1152 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1153 break;
1154 /* other */
1155 case _USB_PHY_48:
Patrick Delaunay4a1b0832022-04-26 14:37:49 +02001156 clock = stm32mp1_clk_get_by_name("ck_usbo_48m");
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001157 break;
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02001158 case _DSI_PHY:
Patrick Delaunay4a1b0832022-04-26 14:37:49 +02001159 clock = stm32mp1_clk_get_by_name("ck_dsi_phy");
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02001160 break;
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001161 default:
1162 break;
1163 }
1164
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001165 log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001166
1167 return clock;
1168}
1169
1170static int stm32mp1_clk_enable(struct clk *clk)
1171{
1172 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1173 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1174 int i = stm32mp1_clk_get_id(priv, clk->id);
1175
1176 if (i < 0)
1177 return i;
1178
1179 if (gate[i].set_clr)
1180 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1181 else
1182 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1183
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001184 dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001185
1186 return 0;
1187}
1188
1189static int stm32mp1_clk_disable(struct clk *clk)
1190{
1191 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1192 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1193 int i = stm32mp1_clk_get_id(priv, clk->id);
1194
1195 if (i < 0)
1196 return i;
1197
1198 if (gate[i].set_clr)
1199 writel(BIT(gate[i].bit),
1200 priv->base + gate[i].offset
1201 + RCC_MP_ENCLRR_OFFSET);
1202 else
1203 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1204
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001205 dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001206
1207 return 0;
1208}
1209
1210static ulong stm32mp1_clk_get_rate(struct clk *clk)
1211{
1212 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1213 int p = stm32mp1_clk_get_parent(priv, clk->id);
1214 ulong rate;
1215
1216 if (p < 0)
1217 return 0;
1218
1219 rate = stm32mp1_clk_get(priv, p);
1220
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001221 dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n",
1222 (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1223
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001224 return rate;
1225}
1226
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001227#ifdef STM32MP1_CLOCK_TREE_INIT
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001228
1229bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
1230{
1231 unsigned int id;
1232
1233 switch (opp_id) {
1234 case 1:
1235 case 2:
1236 id = opp_id;
1237 break;
1238 default:
1239 id = 1; /* default value */
1240 break;
1241 }
1242
1243 switch (cpu_type) {
1244 case CPU_STM32MP157Fxx:
1245 case CPU_STM32MP157Dxx:
1246 case CPU_STM32MP153Fxx:
1247 case CPU_STM32MP153Dxx:
1248 case CPU_STM32MP151Fxx:
1249 case CPU_STM32MP151Dxx:
1250 return true;
1251 default:
1252 return id == 1;
1253 }
1254}
1255
Patrick Delaunay3d1fe4e2020-05-25 12:19:45 +02001256__weak void board_vddcore_init(u32 voltage_mv)
1257{
1258}
1259
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001260/*
1261 * gets OPP parameters (frequency in KHz and voltage in mV) from
1262 * an OPP table subnode. Platform HW support capabilities are also checked.
1263 * Returns 0 on success and a negative FDT error code on failure.
1264 */
1265static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
1266 u32 *freq_khz, u32 *voltage_mv)
1267{
1268 u32 opp_hw;
1269 u64 read_freq_64;
1270 u32 read_voltage_32;
1271
1272 *freq_khz = 0;
1273 *voltage_mv = 0;
1274
1275 opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
1276 if (opp_hw)
1277 if (!stm32mp1_supports_opp(opp_hw, cpu_type))
1278 return -FDT_ERR_BADVALUE;
1279
1280 read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
1281 1000ULL;
1282 read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
1283 1000U;
1284
1285 if (!read_voltage_32 || !read_freq_64)
1286 return -FDT_ERR_NOTFOUND;
1287
1288 /* Frequency value expressed in KHz must fit on 32 bits */
1289 if (read_freq_64 > U32_MAX)
1290 return -FDT_ERR_BADVALUE;
1291
1292 /* Millivolt value must fit on 16 bits */
1293 if (read_voltage_32 > U16_MAX)
1294 return -FDT_ERR_BADVALUE;
1295
1296 *freq_khz = (u32)read_freq_64;
1297 *voltage_mv = read_voltage_32;
1298
1299 return 0;
1300}
1301
1302/*
1303 * parses OPP table in DT and finds the parameters for the
1304 * highest frequency supported by the HW platform.
1305 * Returns 0 on success and a negative FDT error code on failure.
1306 */
1307int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
1308{
1309 ofnode node, subnode;
1310 int ret;
1311 u32 freq = 0U, voltage = 0U;
1312 u32 cpu_type = get_cpu_type();
1313
1314 node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
1315 if (!ofnode_valid(node))
1316 return -FDT_ERR_NOTFOUND;
1317
1318 ofnode_for_each_subnode(subnode, node) {
1319 unsigned int read_freq;
1320 unsigned int read_voltage;
1321
1322 ret = stm32mp1_get_opp(cpu_type, subnode,
1323 &read_freq, &read_voltage);
1324 if (ret)
1325 continue;
1326
1327 if (read_freq > freq) {
1328 freq = read_freq;
1329 voltage = read_voltage;
1330 }
1331 }
1332
1333 if (!freq || !voltage)
1334 return -FDT_ERR_NOTFOUND;
1335
1336 *freq_hz = (u64)1000U * freq;
Patrick Delaunay3d1fe4e2020-05-25 12:19:45 +02001337 board_vddcore_init(voltage);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001338
1339 return 0;
1340}
1341
1342static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
1343 u32 *pllcfg, u32 *fracv)
1344{
1345 u32 post_divm;
1346 u32 input_freq;
1347 u64 output_freq;
1348 u64 freq;
1349 u64 vco;
1350 u32 divm, divn, divp, frac;
1351 int i, ret;
1352 u32 diff;
1353 u32 best_diff = U32_MAX;
1354
1355 /* PLL1 is 1600 */
1356 const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
1357 const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
1358 const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
1359
1360 ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
1361 if (ret) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001362 log_debug("PLL1 OPP configuration not found (%d).\n", ret);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001363 return ret;
1364 }
1365
1366 switch (clksrc) {
1367 case CLK_PLL12_HSI:
1368 input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
1369 break;
1370 case CLK_PLL12_HSE:
1371 input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
1372 break;
1373 default:
1374 return -EINTR;
1375 }
1376
1377 /* Following parameters have always the same value */
1378 pllcfg[PLLCFG_Q] = 0;
1379 pllcfg[PLLCFG_R] = 0;
1380 pllcfg[PLLCFG_O] = PQR(1, 0, 0);
1381
1382 for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
1383 post_divm = (u32)(input_freq / (divm + 1));
1384 if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
1385 continue;
1386
1387 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
1388 freq = output_freq * (divm + 1) * (divp + 1);
1389 divn = (u32)((freq / input_freq) - 1);
1390 if (divn < DIVN_MIN || divn > DIVN_MAX)
1391 continue;
1392
1393 frac = (u32)(((freq * FRAC_MAX) / input_freq) -
1394 ((divn + 1) * FRAC_MAX));
1395 /* 2 loops to refine the fractional part */
1396 for (i = 2; i != 0; i--) {
1397 if (frac > FRAC_MAX)
1398 break;
1399
1400 vco = (post_divm * (divn + 1)) +
1401 ((post_divm * (u64)frac) /
1402 FRAC_MAX);
1403 if (vco < (PLL1600_VCO_MIN / 2) ||
1404 vco > (PLL1600_VCO_MAX / 2)) {
1405 frac++;
1406 continue;
1407 }
1408 freq = vco / (divp + 1);
1409 if (output_freq < freq)
1410 diff = (u32)(freq - output_freq);
1411 else
1412 diff = (u32)(output_freq - freq);
1413 if (diff < best_diff) {
1414 pllcfg[PLLCFG_M] = divm;
1415 pllcfg[PLLCFG_N] = divn;
1416 pllcfg[PLLCFG_P] = divp;
1417 *fracv = frac;
1418
1419 if (diff == 0)
1420 return 0;
1421
1422 best_diff = diff;
1423 }
1424 frac++;
1425 }
1426 }
1427 }
1428
1429 if (best_diff == U32_MAX)
1430 return -1;
1431
1432 return 0;
1433}
1434
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001435static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1436 u32 mask_on)
1437{
1438 u32 address = rcc + offset;
1439
1440 if (enable)
1441 setbits_le32(address, mask_on);
1442 else
1443 clrbits_le32(address, mask_on);
1444}
1445
1446static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1447{
Patrick Delaunayf5aaa072019-01-30 13:07:02 +01001448 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001449}
1450
1451static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1452 u32 mask_rdy)
1453{
1454 u32 mask_test = 0;
1455 u32 address = rcc + offset;
1456 u32 val;
1457 int ret;
1458
1459 if (enable)
1460 mask_test = mask_rdy;
1461
1462 ret = readl_poll_timeout(address, val,
1463 (val & mask_rdy) == mask_test,
1464 TIMEOUT_1S);
1465
1466 if (ret)
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001467 log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1468 mask_rdy, address, enable, readl(address));
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001469
1470 return ret;
1471}
1472
Patrick Delaunay80cb5682018-07-16 10:41:46 +02001473static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
Patrick Delaunay5ba62a42020-01-28 10:44:15 +01001474 u32 lsedrv)
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001475{
1476 u32 value;
1477
Patrick Delaunay80cb5682018-07-16 10:41:46 +02001478 if (digbyp)
1479 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
1480
1481 if (bypass || digbyp)
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001482 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1483
1484 /*
1485 * warning: not recommended to switch directly from "high drive"
1486 * to "medium low drive", and vice-versa.
1487 */
1488 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1489 >> RCC_BDCR_LSEDRV_SHIFT;
1490
1491 while (value != lsedrv) {
1492 if (value > lsedrv)
1493 value--;
1494 else
1495 value++;
1496
1497 clrsetbits_le32(rcc + RCC_BDCR,
1498 RCC_BDCR_LSEDRV_MASK,
1499 value << RCC_BDCR_LSEDRV_SHIFT);
1500 }
1501
1502 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1503}
1504
1505static void stm32mp1_lse_wait(fdt_addr_t rcc)
1506{
1507 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1508}
1509
1510static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1511{
1512 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1513 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1514}
1515
Patrick Delaunay80cb5682018-07-16 10:41:46 +02001516static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001517{
Patrick Delaunay80cb5682018-07-16 10:41:46 +02001518 if (digbyp)
Patrick Delaunayf5aaa072019-01-30 13:07:02 +01001519 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
Patrick Delaunay80cb5682018-07-16 10:41:46 +02001520 if (bypass || digbyp)
Patrick Delaunayf5aaa072019-01-30 13:07:02 +01001521 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001522
1523 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1524 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1525
1526 if (css)
Patrick Delaunayf5aaa072019-01-30 13:07:02 +01001527 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001528}
1529
1530static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1531{
Patrick Delaunayf5aaa072019-01-30 13:07:02 +01001532 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001533 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1534}
1535
1536static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1537{
1538 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1539 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1540}
1541
1542static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1543{
1544 u32 address = rcc + RCC_OCRDYR;
1545 u32 val;
1546 int ret;
1547
1548 clrsetbits_le32(rcc + RCC_HSICFGR,
1549 RCC_HSICFGR_HSIDIV_MASK,
1550 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1551
1552 ret = readl_poll_timeout(address, val,
1553 val & RCC_OCRDYR_HSIDIVRDY,
1554 TIMEOUT_200MS);
1555 if (ret)
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001556 log_err("HSIDIV failed @ 0x%x: 0x%x\n",
1557 address, readl(address));
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001558
1559 return ret;
1560}
1561
1562static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1563{
1564 u8 hsidiv;
1565 u32 hsidivfreq = MAX_HSI_HZ;
1566
1567 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1568 hsidivfreq = hsidivfreq / 2)
1569 if (hsidivfreq == hsifreq)
1570 break;
1571
1572 if (hsidiv == 4) {
Etienne Carriere55a78142021-02-24 11:19:42 +01001573 log_err("hsi frequency invalid");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001574 return -1;
1575 }
1576
1577 if (hsidiv > 0)
1578 return stm32mp1_set_hsidiv(rcc, hsidiv);
1579
1580 return 0;
1581}
1582
1583static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1584{
1585 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1586
Patrick Delaunay9a6ce2a2019-01-30 13:07:06 +01001587 clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
1588 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1589 RCC_PLLNCR_DIVREN,
1590 RCC_PLLNCR_PLLON);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001591}
1592
1593static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1594{
1595 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1596 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1597 u32 val;
1598 int ret;
1599
1600 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1601 TIMEOUT_200MS);
1602
1603 if (ret) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001604 log_err("PLL%d start failed @ 0x%x: 0x%x\n",
1605 pll_id, pllxcr, readl(pllxcr));
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001606 return ret;
1607 }
1608
1609 /* start the requested output */
1610 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1611
1612 return 0;
1613}
1614
1615static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1616{
1617 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1618 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1619 u32 val;
1620
1621 /* stop all output */
1622 clrbits_le32(pllxcr,
1623 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1624
1625 /* stop PLL */
1626 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1627
1628 /* wait PLL stopped */
1629 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1630 TIMEOUT_200MS);
1631}
1632
1633static void pll_config_output(struct stm32mp1_clk_priv *priv,
1634 int pll_id, u32 *pllcfg)
1635{
1636 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1637 fdt_addr_t rcc = priv->base;
1638 u32 value;
1639
1640 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1641 & RCC_PLLNCFGR2_DIVP_MASK;
1642 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1643 & RCC_PLLNCFGR2_DIVQ_MASK;
1644 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1645 & RCC_PLLNCFGR2_DIVR_MASK;
1646 writel(value, rcc + pll[pll_id].pllxcfgr2);
1647}
1648
1649static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1650 u32 *pllcfg, u32 fracv)
1651{
1652 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1653 fdt_addr_t rcc = priv->base;
1654 enum stm32mp1_plltype type = pll[pll_id].plltype;
1655 int src;
1656 ulong refclk;
1657 u8 ifrge = 0;
1658 u32 value;
1659
1660 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1661
1662 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1663 (pllcfg[PLLCFG_M] + 1);
1664
1665 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1666 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001667 log_err("invalid refclk = %x\n", (u32)refclk);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001668 return -EINVAL;
1669 }
1670 if (type == PLL_800 && refclk >= 8000000)
1671 ifrge = 1;
1672
1673 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1674 & RCC_PLLNCFGR1_DIVN_MASK;
1675 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1676 & RCC_PLLNCFGR1_DIVM_MASK;
1677 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1678 & RCC_PLLNCFGR1_IFRGE_MASK;
1679 writel(value, rcc + pll[pll_id].pllxcfgr1);
1680
1681 /* fractional configuration: load sigma-delta modulator (SDM) */
1682
1683 /* Write into FRACV the new fractional value , and FRACLE to 0 */
1684 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1685 rcc + pll[pll_id].pllxfracr);
1686
1687 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1688 setbits_le32(rcc + pll[pll_id].pllxfracr,
1689 RCC_PLLNFRACR_FRACLE);
1690
1691 pll_config_output(priv, pll_id, pllcfg);
1692
1693 return 0;
1694}
1695
1696static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1697{
1698 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1699 u32 pllxcsg;
1700
1701 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1702 RCC_PLLNCSGR_MOD_PER_MASK) |
1703 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1704 RCC_PLLNCSGR_INC_STEP_MASK) |
1705 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1706 RCC_PLLNCSGR_SSCG_MODE_MASK);
1707
1708 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
Patrick Delaunay9a6ce2a2019-01-30 13:07:06 +01001709
1710 setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001711}
1712
Patrick Delaunay854c59e2019-04-18 17:32:48 +02001713static __maybe_unused int pll_set_rate(struct udevice *dev,
1714 int pll_id,
1715 int div_id,
1716 unsigned long clk_rate)
1717{
1718 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1719 unsigned int pllcfg[PLLCFG_NB];
1720 ofnode plloff;
1721 char name[12];
1722 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1723 enum stm32mp1_plltype type = pll[pll_id].plltype;
1724 int divm, divn, divy;
1725 int ret;
1726 ulong fck_ref;
1727 u32 fracv;
1728 u64 value;
1729
1730 if (div_id > _DIV_NB)
1731 return -EINVAL;
1732
1733 sprintf(name, "st,pll@%d", pll_id);
1734 plloff = dev_read_subnode(dev, name);
1735 if (!ofnode_valid(plloff))
1736 return -FDT_ERR_NOTFOUND;
1737
1738 ret = ofnode_read_u32_array(plloff, "cfg",
1739 pllcfg, PLLCFG_NB);
1740 if (ret < 0)
1741 return -FDT_ERR_NOTFOUND;
1742
1743 fck_ref = pll_get_fref_ck(priv, pll_id);
1744
1745 divm = pllcfg[PLLCFG_M];
1746 /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
1747 divy = pllcfg[PLLCFG_P + div_id];
1748
1749 /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
1750 * So same final result than PLL2 et 4
1751 * with FRACV
1752 * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
1753 * / (DIVy + 1) * (DIVM + 1)
1754 * value = (DIVN + 1) * 2^13 + FRACV / 2^13
1755 * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
1756 */
1757 value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
1758 value = lldiv(value, fck_ref);
1759
1760 divn = (value >> 13) - 1;
1761 if (divn < DIVN_MIN ||
1762 divn > stm32mp1_pll[type].divn_max) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001763 dev_err(dev, "divn invalid = %d", divn);
Patrick Delaunay854c59e2019-04-18 17:32:48 +02001764 return -EINVAL;
1765 }
1766 fracv = value - ((divn + 1) << 13);
1767 pllcfg[PLLCFG_N] = divn;
1768
1769 /* reconfigure PLL */
1770 pll_stop(priv, pll_id);
1771 pll_config(priv, pll_id, pllcfg, fracv);
1772 pll_start(priv, pll_id);
1773 pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
1774
1775 return 0;
1776}
1777
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001778static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1779{
1780 u32 address = priv->base + (clksrc >> 4);
1781 u32 val;
1782 int ret;
1783
1784 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1785 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1786 TIMEOUT_200MS);
1787 if (ret)
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001788 log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1789 clksrc, address, readl(address));
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001790
1791 return ret;
1792}
1793
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001794static void stgen_config(struct stm32mp1_clk_priv *priv)
1795{
1796 int p;
1797 u32 stgenc, cntfid0;
1798 ulong rate;
1799
Patrick Delaunay82b88ef2019-07-05 17:20:11 +02001800 stgenc = STM32_STGEN_BASE;
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001801 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1802 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1803 rate = stm32mp1_clk_get(priv, p);
1804
1805 if (cntfid0 != rate) {
Patrick Delaunay45e5da52019-01-30 13:07:03 +01001806 u64 counter;
1807
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001808 log_debug("System Generic Counter (STGEN) update\n");
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001809 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
Patrick Delaunay45e5da52019-01-30 13:07:03 +01001810 counter = (u64)readl(stgenc + STGENC_CNTCVL);
1811 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
1812 counter = lldiv(counter * (u64)rate, cntfid0);
1813 writel((u32)counter, stgenc + STGENC_CNTCVL);
1814 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001815 writel(rate, stgenc + STGENC_CNTFID0);
1816 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1817
1818 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1819
1820 /* need to update gd->arch.timer_rate_hz with new frequency */
1821 timer_init();
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001822 }
1823}
1824
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001825static int set_clkdiv(unsigned int clkdiv, u32 address)
1826{
1827 u32 val;
1828 int ret;
1829
1830 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1831 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1832 TIMEOUT_200MS);
1833 if (ret)
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001834 log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1835 clkdiv, address, readl(address));
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001836
1837 return ret;
1838}
1839
1840static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1841 u32 clksrc, u32 clkdiv)
1842{
1843 u32 address = priv->base + (clksrc >> 4);
1844
1845 /*
1846 * binding clksrc : bit15-4 offset
1847 * bit3: disable
1848 * bit2-0: MCOSEL[2:0]
1849 */
1850 if (clksrc & 0x8) {
1851 clrbits_le32(address, RCC_MCOCFG_MCOON);
1852 } else {
1853 clrsetbits_le32(address,
1854 RCC_MCOCFG_MCOSRC_MASK,
1855 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1856 clrsetbits_le32(address,
1857 RCC_MCOCFG_MCODIV_MASK,
1858 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1859 setbits_le32(address, RCC_MCOCFG_MCOON);
1860 }
1861}
1862
1863static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1864 unsigned int clksrc,
1865 int lse_css)
1866{
1867 u32 address = priv->base + RCC_BDCR;
1868
1869 if (readl(address) & RCC_BDCR_RTCCKEN)
1870 goto skip_rtc;
1871
1872 if (clksrc == CLK_RTC_DISABLED)
1873 goto skip_rtc;
1874
1875 clrsetbits_le32(address,
1876 RCC_BDCR_RTCSRC_MASK,
1877 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1878
1879 setbits_le32(address, RCC_BDCR_RTCCKEN);
1880
1881skip_rtc:
1882 if (lse_css)
1883 setbits_le32(address, RCC_BDCR_LSECSSON);
1884}
1885
1886static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1887{
1888 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1889 u32 value = pkcs & 0xF;
1890 u32 mask = 0xF;
1891
1892 if (pkcs & BIT(31)) {
1893 mask <<= 4;
1894 value <<= 4;
1895 }
1896 clrsetbits_le32(address, mask, value);
1897}
1898
1899static int stm32mp1_clktree(struct udevice *dev)
1900{
1901 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1902 fdt_addr_t rcc = priv->base;
1903 unsigned int clksrc[CLKSRC_NB];
1904 unsigned int clkdiv[CLKDIV_NB];
1905 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001906 unsigned int pllfracv[_PLL_NB];
1907 unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
1908 bool pllcfg_valid[_PLL_NB];
1909 bool pllcsg_set[_PLL_NB];
1910 int ret;
1911 int i, len;
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001912 int lse_css = 0;
1913 const u32 *pkcs_cell;
1914
1915 /* check mandatory field */
1916 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1917 if (ret < 0) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001918 dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001919 return -FDT_ERR_NOTFOUND;
1920 }
1921
1922 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1923 if (ret < 0) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001924 dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001925 return -FDT_ERR_NOTFOUND;
1926 }
1927
1928 /* check mandatory field in each pll */
1929 for (i = 0; i < _PLL_NB; i++) {
1930 char name[12];
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001931 ofnode node;
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001932
1933 sprintf(name, "st,pll@%d", i);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001934 node = dev_read_subnode(dev, name);
1935 pllcfg_valid[i] = ofnode_valid(node);
1936 pllcsg_set[i] = false;
1937 if (pllcfg_valid[i]) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001938 dev_dbg(dev, "DT for PLL %d @ %s\n", i, name);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001939 ret = ofnode_read_u32_array(node, "cfg",
1940 pllcfg[i], PLLCFG_NB);
1941 if (ret < 0) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001942 dev_dbg(dev, "field cfg invalid: error %d\n", ret);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001943 return -FDT_ERR_NOTFOUND;
1944 }
1945 pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
1946
1947 ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
1948 PLLCSG_NB);
1949 if (!ret) {
1950 pllcsg_set[i] = true;
1951 } else if (ret != -FDT_ERR_NOTFOUND) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001952 dev_dbg(dev, "invalid csg node for pll@%d res=%d\n",
1953 i, ret);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001954 return ret;
1955 }
1956 } else if (i == _PLL1) {
1957 /* use OPP for PLL1 for A7 CPU */
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001958 dev_dbg(dev, "DT for PLL %d with OPP\n", i);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001959 ret = stm32mp1_pll1_opp(priv,
1960 clksrc[CLKSRC_PLL12],
1961 pllcfg[i],
1962 &pllfracv[i]);
1963 if (ret) {
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001964 dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02001965 return ret;
1966 }
1967 pllcfg_valid[i] = true;
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001968 }
1969 }
1970
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001971 dev_dbg(dev, "configuration MCO\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001972 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1973 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1974
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01001975 dev_dbg(dev, "switch ON osillator\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001976 /*
1977 * switch ON oscillator found in device-tree,
1978 * HSI already ON after bootrom
1979 */
Etienne Carriere55a78142021-02-24 11:19:42 +01001980 if (clk_valid(&priv->osc_clk[_LSI]))
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001981 stm32mp1_lsi_set(rcc, 1);
1982
Etienne Carriere55a78142021-02-24 11:19:42 +01001983 if (clk_valid(&priv->osc_clk[_LSE])) {
Patrick Delaunay5ba62a42020-01-28 10:44:15 +01001984 int bypass, digbyp;
1985 u32 lsedrv;
Etienne Carriere55a78142021-02-24 11:19:42 +01001986 struct udevice *dev = priv->osc_clk[_LSE].dev;
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001987
1988 bypass = dev_read_bool(dev, "st,bypass");
Patrick Delaunay80cb5682018-07-16 10:41:46 +02001989 digbyp = dev_read_bool(dev, "st,digbypass");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001990 lse_css = dev_read_bool(dev, "st,css");
1991 lsedrv = dev_read_u32_default(dev, "st,drive",
1992 LSEDRV_MEDIUM_HIGH);
1993
Patrick Delaunay80cb5682018-07-16 10:41:46 +02001994 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001995 }
1996
Etienne Carriere55a78142021-02-24 11:19:42 +01001997 if (clk_valid(&priv->osc_clk[_HSE])) {
Patrick Delaunay80cb5682018-07-16 10:41:46 +02001998 int bypass, digbyp, css;
Etienne Carriere55a78142021-02-24 11:19:42 +01001999 struct udevice *dev = priv->osc_clk[_HSE].dev;
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002000
2001 bypass = dev_read_bool(dev, "st,bypass");
Patrick Delaunay80cb5682018-07-16 10:41:46 +02002002 digbyp = dev_read_bool(dev, "st,digbypass");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002003 css = dev_read_bool(dev, "st,css");
2004
Patrick Delaunay80cb5682018-07-16 10:41:46 +02002005 stm32mp1_hse_enable(rcc, bypass, digbyp, css);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002006 }
2007 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
2008 * => switch on CSI even if node is not present in device tree
2009 */
2010 stm32mp1_csi_set(rcc, 1);
2011
2012 /* come back to HSI */
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002013 dev_dbg(dev, "come back to HSI\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002014 set_clksrc(priv, CLK_MPU_HSI);
2015 set_clksrc(priv, CLK_AXI_HSI);
2016 set_clksrc(priv, CLK_MCU_HSI);
2017
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002018 dev_dbg(dev, "pll stop\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002019 for (i = 0; i < _PLL_NB; i++)
2020 pll_stop(priv, i);
2021
2022 /* configure HSIDIV */
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002023 dev_dbg(dev, "configure HSIDIV\n");
Etienne Carriere55a78142021-02-24 11:19:42 +01002024 if (clk_valid(&priv->osc_clk[_HSI])) {
2025 stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI]));
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01002026 stgen_config(priv);
2027 }
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002028
2029 /* select DIV */
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002030 dev_dbg(dev, "select DIV\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002031 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
2032 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
2033 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
2034 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
2035 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
2036 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
2037 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
2038 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
2039 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
2040
2041 /* no ready bit for RTC */
2042 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
2043
2044 /* configure PLLs source */
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002045 dev_dbg(dev, "configure PLLs source\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002046 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
2047 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
2048 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
2049
2050 /* configure and start PLLs */
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002051 dev_dbg(dev, "configure PLLs\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002052 for (i = 0; i < _PLL_NB; i++) {
Patrick Delaunay885bdc22020-05-25 12:19:44 +02002053 if (!pllcfg_valid[i])
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002054 continue;
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002055 dev_dbg(dev, "configure PLL %d\n", i);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02002056 pll_config(priv, i, pllcfg[i], pllfracv[i]);
2057 if (pllcsg_set[i])
2058 pll_csg(priv, i, pllcsg[i]);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002059 pll_start(priv, i);
2060 }
2061
2062 /* wait and start PLLs ouptut when ready */
2063 for (i = 0; i < _PLL_NB; i++) {
Patrick Delaunay885bdc22020-05-25 12:19:44 +02002064 if (!pllcfg_valid[i])
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002065 continue;
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002066 dev_dbg(dev, "output PLL %d\n", i);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002067 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
2068 }
2069
2070 /* wait LSE ready before to use it */
Etienne Carriere55a78142021-02-24 11:19:42 +01002071 if (clk_valid(&priv->osc_clk[_LSE]))
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002072 stm32mp1_lse_wait(rcc);
2073
2074 /* configure with expected clock source */
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002075 dev_dbg(dev, "CLKSRC\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002076 set_clksrc(priv, clksrc[CLKSRC_MPU]);
2077 set_clksrc(priv, clksrc[CLKSRC_AXI]);
2078 set_clksrc(priv, clksrc[CLKSRC_MCU]);
2079 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
2080
2081 /* configure PKCK */
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002082 dev_dbg(dev, "PKCK\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002083 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
2084 if (pkcs_cell) {
2085 bool ckper_disabled = false;
2086
2087 for (i = 0; i < len / sizeof(u32); i++) {
2088 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
2089
2090 if (pkcs == CLK_CKPER_DISABLED) {
2091 ckper_disabled = true;
2092 continue;
2093 }
2094 pkcs_config(priv, pkcs);
2095 }
2096 /* CKPER is source for some peripheral clock
2097 * (FMC-NAND / QPSI-NOR) and switching source is allowed
2098 * only if previous clock is still ON
2099 * => deactivated CKPER only after switching clock
2100 */
2101 if (ckper_disabled)
2102 pkcs_config(priv, CLK_CKPER_DISABLED);
2103 }
2104
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01002105 /* STGEN clock source can change with CLK_STGEN_XXX */
2106 stgen_config(priv);
2107
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002108 dev_dbg(dev, "oscillator off\n");
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002109 /* switch OFF HSI if not found in device-tree */
Etienne Carriere55a78142021-02-24 11:19:42 +01002110 if (!clk_valid(&priv->osc_clk[_HSI]))
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002111 stm32mp1_hsi_set(rcc, 0);
2112
2113 /* Software Self-Refresh mode (SSR) during DDR initilialization */
2114 clrsetbits_le32(priv->base + RCC_DDRITFCR,
2115 RCC_DDRITFCR_DDRCKMOD_MASK,
2116 RCC_DDRITFCR_DDRCKMOD_SSR <<
2117 RCC_DDRITFCR_DDRCKMOD_SHIFT);
2118
2119 return 0;
2120}
2121#endif /* STM32MP1_CLOCK_TREE_INIT */
2122
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02002123static int pll_set_output_rate(struct udevice *dev,
2124 int pll_id,
2125 int div_id,
2126 unsigned long clk_rate)
2127{
2128 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2129 const struct stm32mp1_clk_pll *pll = priv->data->pll;
2130 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
2131 int div;
2132 ulong fvco;
2133
2134 if (div_id > _DIV_NB)
2135 return -EINVAL;
2136
2137 fvco = pll_get_fvco(priv, pll_id);
2138
2139 if (fvco <= clk_rate)
2140 div = 1;
2141 else
2142 div = DIV_ROUND_UP(fvco, clk_rate);
2143
2144 if (div > 128)
2145 div = 128;
2146
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02002147 /* stop the requested output */
2148 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2149 /* change divider */
2150 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
2151 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
2152 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
2153 /* start the requested output */
2154 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
2155
2156 return 0;
2157}
2158
2159static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
2160{
2161 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
2162 int p;
2163
2164 switch (clk->id) {
Patrick Delaunay854c59e2019-04-18 17:32:48 +02002165#if defined(STM32MP1_CLOCK_TREE_INIT) && \
2166 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2167 case DDRPHYC:
2168 break;
2169#endif
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02002170 case LTDC_PX:
2171 case DSI_PX:
2172 break;
2173 default:
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002174 dev_err(clk->dev, "Set of clk %ld not supported", clk->id);
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02002175 return -EINVAL;
2176 }
2177
2178 p = stm32mp1_clk_get_parent(priv, clk->id);
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002179 dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]);
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02002180 if (p < 0)
2181 return -EINVAL;
2182
2183 switch (p) {
Patrick Delaunay854c59e2019-04-18 17:32:48 +02002184#if defined(STM32MP1_CLOCK_TREE_INIT) && \
2185 defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
2186 case _PLL2_R: /* DDRPHYC */
2187 {
2188 /* only for change DDR clock in interactive mode */
2189 ulong result;
2190
2191 set_clksrc(priv, CLK_AXI_HSI);
2192 result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
2193 set_clksrc(priv, CLK_AXI_PLL2P);
2194 return result;
2195 }
2196#endif
Patrick Delaunaya06a4562019-07-30 19:16:54 +02002197
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02002198 case _PLL4_Q:
2199 /* for LTDC_PX and DSI_PX case */
2200 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
2201 }
2202
2203 return -EINVAL;
2204}
2205
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002206static void stm32mp1_osc_init(struct udevice *dev)
2207{
2208 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2209 int i;
2210 const char *name[NB_OSC] = {
Etienne Carriere55a78142021-02-24 11:19:42 +01002211 [_LSI] = "lsi",
2212 [_LSE] = "lse",
2213 [_HSI] = "hsi",
2214 [_HSE] = "hse",
2215 [_CSI] = "csi",
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002216 [_I2S_CKIN] = "i2s_ckin",
Patrick Delaunay7b726532019-01-30 13:07:00 +01002217 };
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002218
2219 for (i = 0; i < NB_OSC; i++) {
Etienne Carriere55a78142021-02-24 11:19:42 +01002220 if (clk_get_by_name(dev, name[i], &priv->osc_clk[i]))
Marek Vasut8dfc4072022-04-22 12:40:39 +02002221 dev_dbg(dev, "No source clock \"%s\"\n", name[i]);
Etienne Carriere55a78142021-02-24 11:19:42 +01002222 else
2223 dev_dbg(dev, "%s clock rate: %luHz\n",
2224 name[i], clk_get_rate(&priv->osc_clk[i]));
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002225 }
2226}
2227
Patrick Delaunaye8d836c2019-01-30 13:07:04 +01002228static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
2229{
2230 char buf[32];
2231 int i, s, p;
2232
2233 printf("Clocks:\n");
2234 for (i = 0; i < _PARENT_NB; i++) {
2235 printf("- %s : %s MHz\n",
2236 stm32mp1_clk_parent_name[i],
2237 strmhz(buf, stm32mp1_clk_get(priv, i)));
2238 }
2239 printf("Source Clocks:\n");
2240 for (i = 0; i < _PARENT_SEL_NB; i++) {
2241 p = (readl(priv->base + priv->data->sel[i].offset) >>
2242 priv->data->sel[i].src) & priv->data->sel[i].msk;
2243 if (p < priv->data->sel[i].nb_parent) {
2244 s = priv->data->sel[i].parent[p];
2245 printf("- %s(%d) => parent %s(%d)\n",
2246 stm32mp1_clk_parent_sel_name[i], i,
2247 stm32mp1_clk_parent_name[s], s);
2248 } else {
2249 printf("- %s(%d) => parent index %d is invalid\n",
2250 stm32mp1_clk_parent_sel_name[i], i, p);
2251 }
2252 }
2253}
2254
2255#ifdef CONFIG_CMD_CLK
2256int soc_clk_dump(void)
2257{
2258 struct udevice *dev;
2259 struct stm32mp1_clk_priv *priv;
2260 int ret;
2261
2262 ret = uclass_get_device_by_driver(UCLASS_CLK,
Simon Glass65130cd2020-12-28 20:34:56 -07002263 DM_DRIVER_GET(stm32mp1_clock),
Patrick Delaunaye8d836c2019-01-30 13:07:04 +01002264 &dev);
2265 if (ret)
2266 return ret;
2267
2268 priv = dev_get_priv(dev);
2269
2270 stm32mp1_clk_dump(priv);
2271
2272 return 0;
2273}
2274#endif
2275
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002276static int stm32mp1_clk_probe(struct udevice *dev)
2277{
2278 int result = 0;
2279 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
2280
2281 priv->base = dev_read_addr(dev->parent);
2282 if (priv->base == FDT_ADDR_T_NONE)
2283 return -EINVAL;
2284
2285 priv->data = (void *)&stm32mp1_data;
2286
2287 if (!priv->data->gate || !priv->data->sel ||
2288 !priv->data->pll)
2289 return -EINVAL;
2290
2291 stm32mp1_osc_init(dev);
2292
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002293#ifdef STM32MP1_CLOCK_TREE_INIT
2294 /* clock tree init is done only one time, before relocation */
2295 if (!(gd->flags & GD_FLG_RELOC))
2296 result = stm32mp1_clktree(dev);
Patrick Delaunay885bdc22020-05-25 12:19:44 +02002297 if (result)
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002298 dev_err(dev, "clock tree initialization failed (%d)\n", result);
Patrick Delaunayf11398e2018-03-12 10:46:16 +01002299#endif
2300
Patrick Delaunaye8d836c2019-01-30 13:07:04 +01002301#ifndef CONFIG_SPL_BUILD
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002302#if defined(VERBOSE_DEBUG)
Patrick Delaunaye8d836c2019-01-30 13:07:04 +01002303 /* display debug information for probe after relocation */
2304 if (gd->flags & GD_FLG_RELOC)
2305 stm32mp1_clk_dump(priv);
2306#endif
2307
Patrick Delaunaya77c6ed2019-07-30 19:16:55 +02002308 gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
2309 gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
2310 /* DDRPHYC father */
2311 gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
Patrick Delaunaye8d836c2019-01-30 13:07:04 +01002312#if defined(CONFIG_DISPLAY_CPUINFO)
2313 if (gd->flags & GD_FLG_RELOC) {
2314 char buf[32];
2315
Patrick Delaunay30cd91e2020-11-06 19:01:45 +01002316 log_info("Clocks:\n");
2317 log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
2318 log_info("- MCU : %s MHz\n",
2319 strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
2320 log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
2321 log_info("- PER : %s MHz\n",
2322 strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
2323 log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
Patrick Delaunaye8d836c2019-01-30 13:07:04 +01002324 }
2325#endif /* CONFIG_DISPLAY_CPUINFO */
2326#endif
2327
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002328 return result;
2329}
2330
2331static const struct clk_ops stm32mp1_clk_ops = {
2332 .enable = stm32mp1_clk_enable,
2333 .disable = stm32mp1_clk_disable,
2334 .get_rate = stm32mp1_clk_get_rate,
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02002335 .set_rate = stm32mp1_clk_set_rate,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002336};
2337
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002338U_BOOT_DRIVER(stm32mp1_clock) = {
2339 .name = "stm32mp1_clk",
2340 .id = UCLASS_CLK,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002341 .ops = &stm32mp1_clk_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -07002342 .priv_auto = sizeof(struct stm32mp1_clk_priv),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002343 .probe = stm32mp1_clk_probe,
2344};