blob: 05dc93a1df1c78c3528608dc180020a5259c492f [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01004 */
5
6#include <common.h>
7#include <clk-uclass.h>
8#include <div64.h>
9#include <dm.h>
10#include <regmap.h>
11#include <spl.h>
12#include <syscon.h>
13#include <linux/io.h>
Patrick Delaunayf11398e2018-03-12 10:46:16 +010014#include <linux/iopoll.h>
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010015#include <dt-bindings/clock/stm32mp1-clks.h>
Patrick Delaunayf11398e2018-03-12 10:46:16 +010016#include <dt-bindings/clock/stm32mp1-clksrc.h>
17
18#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
19/* activate clock tree initialization in the driver */
20#define STM32MP1_CLOCK_TREE_INIT
21#endif
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010022
23#define MAX_HSI_HZ 64000000
24
Patrick Delaunayf11398e2018-03-12 10:46:16 +010025/* TIMEOUT */
26#define TIMEOUT_200MS 200000
27#define TIMEOUT_1S 1000000
28
Patrick Delaunaybf7d9442018-03-20 11:41:25 +010029/* STGEN registers */
30#define STGENC_CNTCR 0x00
31#define STGENC_CNTSR 0x04
32#define STGENC_CNTCVL 0x08
33#define STGENC_CNTCVU 0x0C
34#define STGENC_CNTFID0 0x20
35
36#define STGENC_CNTCR_EN BIT(0)
37
Patrick Delaunaye6ab6272018-03-12 10:46:15 +010038/* RCC registers */
39#define RCC_OCENSETR 0x0C
40#define RCC_OCENCLRR 0x10
41#define RCC_HSICFGR 0x18
42#define RCC_MPCKSELR 0x20
43#define RCC_ASSCKSELR 0x24
44#define RCC_RCK12SELR 0x28
45#define RCC_MPCKDIVR 0x2C
46#define RCC_AXIDIVR 0x30
47#define RCC_APB4DIVR 0x3C
48#define RCC_APB5DIVR 0x40
49#define RCC_RTCDIVR 0x44
50#define RCC_MSSCKSELR 0x48
51#define RCC_PLL1CR 0x80
52#define RCC_PLL1CFGR1 0x84
53#define RCC_PLL1CFGR2 0x88
54#define RCC_PLL1FRACR 0x8C
55#define RCC_PLL1CSGR 0x90
56#define RCC_PLL2CR 0x94
57#define RCC_PLL2CFGR1 0x98
58#define RCC_PLL2CFGR2 0x9C
59#define RCC_PLL2FRACR 0xA0
60#define RCC_PLL2CSGR 0xA4
61#define RCC_I2C46CKSELR 0xC0
62#define RCC_CPERCKSELR 0xD0
63#define RCC_STGENCKSELR 0xD4
64#define RCC_DDRITFCR 0xD8
65#define RCC_BDCR 0x140
66#define RCC_RDLSICR 0x144
67#define RCC_MP_APB4ENSETR 0x200
68#define RCC_MP_APB5ENSETR 0x208
69#define RCC_MP_AHB5ENSETR 0x210
70#define RCC_MP_AHB6ENSETR 0x218
71#define RCC_OCRDYR 0x808
72#define RCC_DBGCFGR 0x80C
73#define RCC_RCK3SELR 0x820
74#define RCC_RCK4SELR 0x824
75#define RCC_MCUDIVR 0x830
76#define RCC_APB1DIVR 0x834
77#define RCC_APB2DIVR 0x838
78#define RCC_APB3DIVR 0x83C
79#define RCC_PLL3CR 0x880
80#define RCC_PLL3CFGR1 0x884
81#define RCC_PLL3CFGR2 0x888
82#define RCC_PLL3FRACR 0x88C
83#define RCC_PLL3CSGR 0x890
84#define RCC_PLL4CR 0x894
85#define RCC_PLL4CFGR1 0x898
86#define RCC_PLL4CFGR2 0x89C
87#define RCC_PLL4FRACR 0x8A0
88#define RCC_PLL4CSGR 0x8A4
89#define RCC_I2C12CKSELR 0x8C0
90#define RCC_I2C35CKSELR 0x8C4
91#define RCC_UART6CKSELR 0x8E4
92#define RCC_UART24CKSELR 0x8E8
93#define RCC_UART35CKSELR 0x8EC
94#define RCC_UART78CKSELR 0x8F0
95#define RCC_SDMMC12CKSELR 0x8F4
96#define RCC_SDMMC3CKSELR 0x8F8
97#define RCC_ETHCKSELR 0x8FC
98#define RCC_QSPICKSELR 0x900
99#define RCC_FMCCKSELR 0x904
100#define RCC_USBCKSELR 0x91C
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200101#define RCC_DSICKSELR 0x924
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200102#define RCC_ADCCKSELR 0x928
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100103#define RCC_MP_APB1ENSETR 0xA00
104#define RCC_MP_APB2ENSETR 0XA08
Fabrice Gasnier4cb3b532018-04-26 17:00:47 +0200105#define RCC_MP_APB3ENSETR 0xA10
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100106#define RCC_MP_AHB2ENSETR 0xA18
107#define RCC_MP_AHB4ENSETR 0xA28
108
109/* used for most of SELR register */
110#define RCC_SELR_SRC_MASK GENMASK(2, 0)
111#define RCC_SELR_SRCRDY BIT(31)
112
113/* Values of RCC_MPCKSELR register */
114#define RCC_MPCKSELR_HSI 0
115#define RCC_MPCKSELR_HSE 1
116#define RCC_MPCKSELR_PLL 2
117#define RCC_MPCKSELR_PLL_MPUDIV 3
118
119/* Values of RCC_ASSCKSELR register */
120#define RCC_ASSCKSELR_HSI 0
121#define RCC_ASSCKSELR_HSE 1
122#define RCC_ASSCKSELR_PLL 2
123
124/* Values of RCC_MSSCKSELR register */
125#define RCC_MSSCKSELR_HSI 0
126#define RCC_MSSCKSELR_HSE 1
127#define RCC_MSSCKSELR_CSI 2
128#define RCC_MSSCKSELR_PLL 3
129
130/* Values of RCC_CPERCKSELR register */
131#define RCC_CPERCKSELR_HSI 0
132#define RCC_CPERCKSELR_CSI 1
133#define RCC_CPERCKSELR_HSE 2
134
135/* used for most of DIVR register : max div for RTC */
136#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
137#define RCC_DIVR_DIVRDY BIT(31)
138
139/* Masks for specific DIVR registers */
140#define RCC_APBXDIV_MASK GENMASK(2, 0)
141#define RCC_MPUDIV_MASK GENMASK(2, 0)
142#define RCC_AXIDIV_MASK GENMASK(2, 0)
143#define RCC_MCUDIV_MASK GENMASK(3, 0)
144
145/* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
146#define RCC_MP_ENCLRR_OFFSET 4
147
148/* Fields of RCC_BDCR register */
149#define RCC_BDCR_LSEON BIT(0)
150#define RCC_BDCR_LSEBYP BIT(1)
151#define RCC_BDCR_LSERDY BIT(2)
152#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
153#define RCC_BDCR_LSEDRV_SHIFT 4
154#define RCC_BDCR_LSECSSON BIT(8)
155#define RCC_BDCR_RTCCKEN BIT(20)
156#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
157#define RCC_BDCR_RTCSRC_SHIFT 16
158
159/* Fields of RCC_RDLSICR register */
160#define RCC_RDLSICR_LSION BIT(0)
161#define RCC_RDLSICR_LSIRDY BIT(1)
162
163/* used for ALL PLLNCR registers */
164#define RCC_PLLNCR_PLLON BIT(0)
165#define RCC_PLLNCR_PLLRDY BIT(1)
166#define RCC_PLLNCR_DIVPEN BIT(4)
167#define RCC_PLLNCR_DIVQEN BIT(5)
168#define RCC_PLLNCR_DIVREN BIT(6)
169#define RCC_PLLNCR_DIVEN_SHIFT 4
170
171/* used for ALL PLLNCFGR1 registers */
172#define RCC_PLLNCFGR1_DIVM_SHIFT 16
173#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
174#define RCC_PLLNCFGR1_DIVN_SHIFT 0
175#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
176/* only for PLL3 and PLL4 */
177#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
178#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
179
Patrick Delaunaya7c0fd62018-07-16 10:41:41 +0200180/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
181#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100182#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
Patrick Delaunaya7c0fd62018-07-16 10:41:41 +0200183#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100184#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
Patrick Delaunaya7c0fd62018-07-16 10:41:41 +0200185#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100186#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
Patrick Delaunaya7c0fd62018-07-16 10:41:41 +0200187#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100188#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
189
190/* used for ALL PLLNFRACR registers */
191#define RCC_PLLNFRACR_FRACV_SHIFT 3
192#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
193#define RCC_PLLNFRACR_FRACLE BIT(16)
194
195/* used for ALL PLLNCSGR registers */
196#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
197#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
198#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
199#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
200#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
201#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
202
203/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
204#define RCC_OCENR_HSION BIT(0)
205#define RCC_OCENR_CSION BIT(4)
206#define RCC_OCENR_HSEON BIT(8)
207#define RCC_OCENR_HSEBYP BIT(10)
208#define RCC_OCENR_HSECSSON BIT(11)
209
210/* Fields of RCC_OCRDYR register */
211#define RCC_OCRDYR_HSIRDY BIT(0)
212#define RCC_OCRDYR_HSIDIVRDY BIT(2)
213#define RCC_OCRDYR_CSIRDY BIT(4)
214#define RCC_OCRDYR_HSERDY BIT(8)
215
216/* Fields of DDRITFCR register */
217#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
218#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
219#define RCC_DDRITFCR_DDRCKMOD_SSR 0
220
221/* Fields of RCC_HSICFGR register */
222#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
223
224/* used for MCO related operations */
225#define RCC_MCOCFG_MCOON BIT(12)
226#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
227#define RCC_MCOCFG_MCODIV_SHIFT 4
228#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
229
230enum stm32mp1_parent_id {
231/*
232 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
233 * they are used as index in osc[] as entry point
234 */
235 _HSI,
236 _HSE,
237 _CSI,
238 _LSI,
239 _LSE,
240 _I2S_CKIN,
241 _USB_PHY_48,
242 NB_OSC,
243
244/* other parent source */
245 _HSI_KER = NB_OSC,
246 _HSE_KER,
247 _HSE_KER_DIV2,
248 _CSI_KER,
249 _PLL1_P,
250 _PLL1_Q,
251 _PLL1_R,
252 _PLL2_P,
253 _PLL2_Q,
254 _PLL2_R,
255 _PLL3_P,
256 _PLL3_Q,
257 _PLL3_R,
258 _PLL4_P,
259 _PLL4_Q,
260 _PLL4_R,
261 _ACLK,
262 _PCLK1,
263 _PCLK2,
264 _PCLK3,
265 _PCLK4,
266 _PCLK5,
267 _HCLK6,
268 _HCLK2,
269 _CK_PER,
270 _CK_MPU,
271 _CK_MCU,
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200272 _DSI_PHY,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100273 _PARENT_NB,
274 _UNKNOWN_ID = 0xff,
275};
276
277enum stm32mp1_parent_sel {
278 _I2C12_SEL,
279 _I2C35_SEL,
280 _I2C46_SEL,
281 _UART6_SEL,
282 _UART24_SEL,
283 _UART35_SEL,
284 _UART78_SEL,
285 _SDMMC12_SEL,
286 _SDMMC3_SEL,
287 _ETH_SEL,
288 _QSPI_SEL,
289 _FMC_SEL,
290 _USBPHY_SEL,
291 _USBO_SEL,
292 _STGEN_SEL,
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200293 _DSI_SEL,
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200294 _ADC12_SEL,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100295 _PARENT_SEL_NB,
296 _UNKNOWN_SEL = 0xff,
297};
298
299enum stm32mp1_pll_id {
300 _PLL1,
301 _PLL2,
302 _PLL3,
303 _PLL4,
304 _PLL_NB
305};
306
307enum stm32mp1_div_id {
308 _DIV_P,
309 _DIV_Q,
310 _DIV_R,
311 _DIV_NB,
312};
313
314enum stm32mp1_clksrc_id {
315 CLKSRC_MPU,
316 CLKSRC_AXI,
317 CLKSRC_MCU,
318 CLKSRC_PLL12,
319 CLKSRC_PLL3,
320 CLKSRC_PLL4,
321 CLKSRC_RTC,
322 CLKSRC_MCO1,
323 CLKSRC_MCO2,
324 CLKSRC_NB
325};
326
327enum stm32mp1_clkdiv_id {
328 CLKDIV_MPU,
329 CLKDIV_AXI,
330 CLKDIV_MCU,
331 CLKDIV_APB1,
332 CLKDIV_APB2,
333 CLKDIV_APB3,
334 CLKDIV_APB4,
335 CLKDIV_APB5,
336 CLKDIV_RTC,
337 CLKDIV_MCO1,
338 CLKDIV_MCO2,
339 CLKDIV_NB
340};
341
342enum stm32mp1_pllcfg {
343 PLLCFG_M,
344 PLLCFG_N,
345 PLLCFG_P,
346 PLLCFG_Q,
347 PLLCFG_R,
348 PLLCFG_O,
349 PLLCFG_NB
350};
351
352enum stm32mp1_pllcsg {
353 PLLCSG_MOD_PER,
354 PLLCSG_INC_STEP,
355 PLLCSG_SSCG_MODE,
356 PLLCSG_NB
357};
358
359enum stm32mp1_plltype {
360 PLL_800,
361 PLL_1600,
362 PLL_TYPE_NB
363};
364
365struct stm32mp1_pll {
366 u8 refclk_min;
367 u8 refclk_max;
368 u8 divn_max;
369};
370
371struct stm32mp1_clk_gate {
372 u16 offset;
373 u8 bit;
374 u8 index;
375 u8 set_clr;
376 u8 sel;
377 u8 fixed;
378};
379
380struct stm32mp1_clk_sel {
381 u16 offset;
382 u8 src;
383 u8 msk;
384 u8 nb_parent;
385 const u8 *parent;
386};
387
388#define REFCLK_SIZE 4
389struct stm32mp1_clk_pll {
390 enum stm32mp1_plltype plltype;
391 u16 rckxselr;
392 u16 pllxcfgr1;
393 u16 pllxcfgr2;
394 u16 pllxfracr;
395 u16 pllxcr;
396 u16 pllxcsgr;
397 u8 refclk[REFCLK_SIZE];
398};
399
400struct stm32mp1_clk_data {
401 const struct stm32mp1_clk_gate *gate;
402 const struct stm32mp1_clk_sel *sel;
403 const struct stm32mp1_clk_pll *pll;
404 const int nb_gate;
405};
406
407struct stm32mp1_clk_priv {
408 fdt_addr_t base;
409 const struct stm32mp1_clk_data *data;
410 ulong osc[NB_OSC];
411 struct udevice *osc_dev[NB_OSC];
412};
413
414#define STM32MP1_CLK(off, b, idx, s) \
415 { \
416 .offset = (off), \
417 .bit = (b), \
418 .index = (idx), \
419 .set_clr = 0, \
420 .sel = (s), \
421 .fixed = _UNKNOWN_ID, \
422 }
423
424#define STM32MP1_CLK_F(off, b, idx, f) \
425 { \
426 .offset = (off), \
427 .bit = (b), \
428 .index = (idx), \
429 .set_clr = 0, \
430 .sel = _UNKNOWN_SEL, \
431 .fixed = (f), \
432 }
433
434#define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
435 { \
436 .offset = (off), \
437 .bit = (b), \
438 .index = (idx), \
439 .set_clr = 1, \
440 .sel = (s), \
441 .fixed = _UNKNOWN_ID, \
442 }
443
444#define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
445 { \
446 .offset = (off), \
447 .bit = (b), \
448 .index = (idx), \
449 .set_clr = 1, \
450 .sel = _UNKNOWN_SEL, \
451 .fixed = (f), \
452 }
453
454#define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
455 [(idx)] = { \
456 .offset = (off), \
457 .src = (s), \
458 .msk = (m), \
459 .parent = (p), \
460 .nb_parent = ARRAY_SIZE((p)) \
461 }
462
463#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
464 p1, p2, p3, p4) \
465 [(idx)] = { \
466 .plltype = (type), \
467 .rckxselr = (off1), \
468 .pllxcfgr1 = (off2), \
469 .pllxcfgr2 = (off3), \
470 .pllxfracr = (off4), \
471 .pllxcr = (off5), \
472 .pllxcsgr = (off6), \
473 .refclk[0] = (p1), \
474 .refclk[1] = (p2), \
475 .refclk[2] = (p3), \
476 .refclk[3] = (p4), \
477 }
478
479static const u8 stm32mp1_clks[][2] = {
480 {CK_PER, _CK_PER},
481 {CK_MPU, _CK_MPU},
482 {CK_AXI, _ACLK},
483 {CK_MCU, _CK_MCU},
484 {CK_HSE, _HSE},
485 {CK_CSI, _CSI},
486 {CK_LSI, _LSI},
487 {CK_LSE, _LSE},
488 {CK_HSI, _HSI},
489 {CK_HSE_DIV2, _HSE_KER_DIV2},
490};
491
492static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
493 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
494 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
495 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
496 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
497 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
498 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
499 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
500 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
501 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
502 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
503 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
504
505 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
506 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
507 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
508 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
509 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
510 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
511 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
512 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
513 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
514 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
515
516 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
517
Fabrice Gasnier4cb3b532018-04-26 17:00:47 +0200518 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
519
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200520 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
521 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
522 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100523 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
524 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
525 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
526
527 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
528 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
529
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200530 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
531 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100532 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
533 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
534
535 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
536 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
537 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
538 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
539 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
540 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
541 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
542 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
543 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
545 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
546
547 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
548
Patrick Delaunayeffe2b42018-07-16 10:41:44 +0200549 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100550 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
551 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100552 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
553 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
554 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
555 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
556 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
557 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
558
559 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
560};
561
562static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
563static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
564static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
565static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
566 _HSE_KER};
567static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
568 _HSE_KER};
569static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
570 _HSE_KER};
571static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
572 _HSE_KER};
573static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
574static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
575static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
576static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
577static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
578static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
579static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
580static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200581static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200582static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100583
584static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
585 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
586 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
587 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
588 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
589 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
590 uart24_parents),
591 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
592 uart35_parents),
593 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
594 uart78_parents),
595 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
596 sdmmc12_parents),
597 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
598 sdmmc3_parents),
599 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
600 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
601 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
602 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
603 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
604 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200605 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200606 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100607};
608
609#ifdef STM32MP1_CLOCK_TREE_INIT
610/* define characteristic of PLL according type */
611#define DIVN_MIN 24
612static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
613 [PLL_800] = {
614 .refclk_min = 4,
615 .refclk_max = 16,
616 .divn_max = 99,
617 },
618 [PLL_1600] = {
619 .refclk_min = 8,
620 .refclk_max = 16,
621 .divn_max = 199,
622 },
623};
624#endif /* STM32MP1_CLOCK_TREE_INIT */
625
626static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
627 STM32MP1_CLK_PLL(_PLL1, PLL_1600,
628 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
629 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
630 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
631 STM32MP1_CLK_PLL(_PLL2, PLL_1600,
632 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
633 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
634 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
635 STM32MP1_CLK_PLL(_PLL3, PLL_800,
636 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
637 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
638 _HSI, _HSE, _CSI, _UNKNOWN_ID),
639 STM32MP1_CLK_PLL(_PLL4, PLL_800,
640 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
641 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
642 _HSI, _HSE, _CSI, _I2S_CKIN),
643};
644
645/* Prescaler table lookups for clock computation */
646/* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
647static const u8 stm32mp1_mcu_div[16] = {
648 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
649};
650
651/* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
652#define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
653#define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
654static const u8 stm32mp1_mpu_apbx_div[8] = {
655 0, 1, 2, 3, 4, 4, 4, 4
656};
657
658/* div = /1 /2 /3 /4 */
659static const u8 stm32mp1_axi_div[8] = {
660 1, 2, 3, 4, 4, 4, 4, 4
661};
662
663#ifdef DEBUG
664static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
665 [_HSI] = "HSI",
666 [_HSE] = "HSE",
667 [_CSI] = "CSI",
668 [_LSI] = "LSI",
669 [_LSE] = "LSE",
670 [_I2S_CKIN] = "I2S_CKIN",
671 [_HSI_KER] = "HSI_KER",
672 [_HSE_KER] = "HSE_KER",
673 [_HSE_KER_DIV2] = "HSE_KER_DIV2",
674 [_CSI_KER] = "CSI_KER",
675 [_PLL1_P] = "PLL1_P",
676 [_PLL1_Q] = "PLL1_Q",
677 [_PLL1_R] = "PLL1_R",
678 [_PLL2_P] = "PLL2_P",
679 [_PLL2_Q] = "PLL2_Q",
680 [_PLL2_R] = "PLL2_R",
681 [_PLL3_P] = "PLL3_P",
682 [_PLL3_Q] = "PLL3_Q",
683 [_PLL3_R] = "PLL3_R",
684 [_PLL4_P] = "PLL4_P",
685 [_PLL4_Q] = "PLL4_Q",
686 [_PLL4_R] = "PLL4_R",
687 [_ACLK] = "ACLK",
688 [_PCLK1] = "PCLK1",
689 [_PCLK2] = "PCLK2",
690 [_PCLK3] = "PCLK3",
691 [_PCLK4] = "PCLK4",
692 [_PCLK5] = "PCLK5",
693 [_HCLK6] = "KCLK6",
694 [_HCLK2] = "HCLK2",
695 [_CK_PER] = "CK_PER",
696 [_CK_MPU] = "CK_MPU",
697 [_CK_MCU] = "CK_MCU",
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200698 [_USB_PHY_48] = "USB_PHY_48",
699 [_DSI_PHY] = "DSI_PHY_PLL",
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100700};
701
702static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
703 [_I2C12_SEL] = "I2C12",
704 [_I2C35_SEL] = "I2C35",
705 [_I2C46_SEL] = "I2C46",
706 [_UART6_SEL] = "UART6",
707 [_UART24_SEL] = "UART24",
708 [_UART35_SEL] = "UART35",
709 [_UART78_SEL] = "UART78",
710 [_SDMMC12_SEL] = "SDMMC12",
711 [_SDMMC3_SEL] = "SDMMC3",
712 [_ETH_SEL] = "ETH",
713 [_QSPI_SEL] = "QSPI",
714 [_FMC_SEL] = "FMC",
715 [_USBPHY_SEL] = "USBPHY",
716 [_USBO_SEL] = "USBO",
Patrick Delaunay8314d2c2018-07-16 10:41:43 +0200717 [_STGEN_SEL] = "STGEN",
718 [_DSI_SEL] = "DSI",
Patrick Delaunay201f0d52018-07-16 10:41:45 +0200719 [_ADC12_SEL] = "ADC12",
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100720};
721#endif
722
723static const struct stm32mp1_clk_data stm32mp1_data = {
724 .gate = stm32mp1_clk_gate,
725 .sel = stm32mp1_clk_sel,
726 .pll = stm32mp1_clk_pll,
727 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
728};
729
730static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
731{
732 if (idx >= NB_OSC) {
733 debug("%s: clk id %d not found\n", __func__, idx);
734 return 0;
735 }
736
737 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
738 (u32)priv->osc[idx], priv->osc[idx] / 1000);
739
740 return priv->osc[idx];
741}
742
743static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
744{
745 const struct stm32mp1_clk_gate *gate = priv->data->gate;
746 int i, nb_clks = priv->data->nb_gate;
747
748 for (i = 0; i < nb_clks; i++) {
749 if (gate[i].index == id)
750 break;
751 }
752
753 if (i == nb_clks) {
754 printf("%s: clk id %d not found\n", __func__, (u32)id);
755 return -EINVAL;
756 }
757
758 return i;
759}
760
761static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
762 int i)
763{
764 const struct stm32mp1_clk_gate *gate = priv->data->gate;
765
766 if (gate[i].sel > _PARENT_SEL_NB) {
767 printf("%s: parents for clk id %d not found\n",
768 __func__, i);
769 return -EINVAL;
770 }
771
772 return gate[i].sel;
773}
774
775static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
776 int i)
777{
778 const struct stm32mp1_clk_gate *gate = priv->data->gate;
779
780 if (gate[i].fixed == _UNKNOWN_ID)
781 return -ENOENT;
782
783 return gate[i].fixed;
784}
785
786static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
787 unsigned long id)
788{
789 const struct stm32mp1_clk_sel *sel = priv->data->sel;
790 int i;
791 int s, p;
792
793 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++)
794 if (stm32mp1_clks[i][0] == id)
795 return stm32mp1_clks[i][1];
796
797 i = stm32mp1_clk_get_id(priv, id);
798 if (i < 0)
799 return i;
800
801 p = stm32mp1_clk_get_fixed_parent(priv, i);
802 if (p >= 0 && p < _PARENT_NB)
803 return p;
804
805 s = stm32mp1_clk_get_sel(priv, i);
806 if (s < 0)
807 return s;
808
809 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
810
811 if (p < sel[s].nb_parent) {
812#ifdef DEBUG
813 debug("%s: %s clock is the parent %s of clk id %d\n", __func__,
814 stm32mp1_clk_parent_name[sel[s].parent[p]],
815 stm32mp1_clk_parent_sel_name[s],
816 (u32)id);
817#endif
818 return sel[s].parent[p];
819 }
820
821 pr_err("%s: no parents defined for clk id %d\n",
822 __func__, (u32)id);
823
824 return -EINVAL;
825}
826
Patrick Delaunay5327d372018-07-16 10:41:42 +0200827static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
828 int pll_id)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100829{
830 const struct stm32mp1_clk_pll *pll = priv->data->pll;
Patrick Delaunay5327d372018-07-16 10:41:42 +0200831 u32 selr;
832 int src;
833 ulong refclk;
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100834
Patrick Delaunay5327d372018-07-16 10:41:42 +0200835 /* Get current refclk */
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100836 selr = readl(priv->base + pll[pll_id].rckxselr);
Patrick Delaunay5327d372018-07-16 10:41:42 +0200837 src = selr & RCC_SELR_SRC_MASK;
838
839 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
840 debug("PLL%d : selr=%x refclk = %d kHz\n",
841 pll_id, selr, (u32)(refclk / 1000));
842
843 return refclk;
844}
845
846/*
847 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
848 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
849 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
850 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
851 */
852static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
853 int pll_id)
854{
855 const struct stm32mp1_clk_pll *pll = priv->data->pll;
856 int divm, divn;
857 ulong refclk, fvco;
858 u32 cfgr1, fracr;
859
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100860 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100861 fracr = readl(priv->base + pll[pll_id].pllxfracr);
862
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100863 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
864 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100865
Patrick Delaunay5327d372018-07-16 10:41:42 +0200866 debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
867 pll_id, cfgr1, fracr, divn, divm);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100868
Patrick Delaunay5327d372018-07-16 10:41:42 +0200869 refclk = pll_get_fref_ck(priv, pll_id);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100870
Patrick Delaunay5327d372018-07-16 10:41:42 +0200871 /* with FRACV :
872 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100873 * without FRACV
Patrick Delaunay5327d372018-07-16 10:41:42 +0200874 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100875 */
876 if (fracr & RCC_PLLNFRACR_FRACLE) {
877 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
878 >> RCC_PLLNFRACR_FRACV_SHIFT;
Patrick Delaunay5327d372018-07-16 10:41:42 +0200879 fvco = (ulong)lldiv((unsigned long long)refclk *
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100880 (((divn + 1) << 13) + fracv),
Patrick Delaunay5327d372018-07-16 10:41:42 +0200881 ((unsigned long long)(divm + 1)) << 13);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100882 } else {
Patrick Delaunay5327d372018-07-16 10:41:42 +0200883 fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100884 }
Patrick Delaunay5327d372018-07-16 10:41:42 +0200885 debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
886
887 return fvco;
888}
889
890static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
891 int pll_id, int div_id)
892{
893 const struct stm32mp1_clk_pll *pll = priv->data->pll;
894 int divy;
895 ulong dfout;
896 u32 cfgr2;
897
898 debug("%s(%d, %d)\n", __func__, pll_id, div_id);
899 if (div_id >= _DIV_NB)
900 return 0;
901
902 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
903 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
904
905 debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
906
907 dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100908 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
909
910 return dfout;
911}
912
913static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
914{
915 u32 reg;
916 ulong clock = 0;
917
918 switch (p) {
919 case _CK_MPU:
920 /* MPU sub system */
921 reg = readl(priv->base + RCC_MPCKSELR);
922 switch (reg & RCC_SELR_SRC_MASK) {
923 case RCC_MPCKSELR_HSI:
924 clock = stm32mp1_clk_get_fixed(priv, _HSI);
925 break;
926 case RCC_MPCKSELR_HSE:
927 clock = stm32mp1_clk_get_fixed(priv, _HSE);
928 break;
929 case RCC_MPCKSELR_PLL:
930 case RCC_MPCKSELR_PLL_MPUDIV:
931 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
932 if (p == RCC_MPCKSELR_PLL_MPUDIV) {
933 reg = readl(priv->base + RCC_MPCKDIVR);
934 clock /= stm32mp1_mpu_div[reg &
935 RCC_MPUDIV_MASK];
936 }
937 break;
938 }
939 break;
940 /* AXI sub system */
941 case _ACLK:
942 case _HCLK2:
943 case _HCLK6:
944 case _PCLK4:
945 case _PCLK5:
946 reg = readl(priv->base + RCC_ASSCKSELR);
947 switch (reg & RCC_SELR_SRC_MASK) {
948 case RCC_ASSCKSELR_HSI:
949 clock = stm32mp1_clk_get_fixed(priv, _HSI);
950 break;
951 case RCC_ASSCKSELR_HSE:
952 clock = stm32mp1_clk_get_fixed(priv, _HSE);
953 break;
954 case RCC_ASSCKSELR_PLL:
955 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
956 break;
957 }
958
959 /* System clock divider */
960 reg = readl(priv->base + RCC_AXIDIVR);
961 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
962
963 switch (p) {
964 case _PCLK4:
965 reg = readl(priv->base + RCC_APB4DIVR);
966 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
967 break;
968 case _PCLK5:
969 reg = readl(priv->base + RCC_APB5DIVR);
970 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
971 break;
972 default:
973 break;
974 }
975 break;
976 /* MCU sub system */
977 case _CK_MCU:
978 case _PCLK1:
979 case _PCLK2:
980 case _PCLK3:
981 reg = readl(priv->base + RCC_MSSCKSELR);
982 switch (reg & RCC_SELR_SRC_MASK) {
983 case RCC_MSSCKSELR_HSI:
984 clock = stm32mp1_clk_get_fixed(priv, _HSI);
985 break;
986 case RCC_MSSCKSELR_HSE:
987 clock = stm32mp1_clk_get_fixed(priv, _HSE);
988 break;
989 case RCC_MSSCKSELR_CSI:
990 clock = stm32mp1_clk_get_fixed(priv, _CSI);
991 break;
992 case RCC_MSSCKSELR_PLL:
993 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
994 break;
995 }
996
997 /* MCU clock divider */
998 reg = readl(priv->base + RCC_MCUDIVR);
999 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
1000
1001 switch (p) {
1002 case _PCLK1:
1003 reg = readl(priv->base + RCC_APB1DIVR);
1004 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1005 break;
1006 case _PCLK2:
1007 reg = readl(priv->base + RCC_APB2DIVR);
1008 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1009 break;
1010 case _PCLK3:
1011 reg = readl(priv->base + RCC_APB3DIVR);
1012 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
1013 break;
1014 case _CK_MCU:
1015 default:
1016 break;
1017 }
1018 break;
1019 case _CK_PER:
1020 reg = readl(priv->base + RCC_CPERCKSELR);
1021 switch (reg & RCC_SELR_SRC_MASK) {
1022 case RCC_CPERCKSELR_HSI:
1023 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1024 break;
1025 case RCC_CPERCKSELR_HSE:
1026 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1027 break;
1028 case RCC_CPERCKSELR_CSI:
1029 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1030 break;
1031 }
1032 break;
1033 case _HSI:
1034 case _HSI_KER:
1035 clock = stm32mp1_clk_get_fixed(priv, _HSI);
1036 break;
1037 case _CSI:
1038 case _CSI_KER:
1039 clock = stm32mp1_clk_get_fixed(priv, _CSI);
1040 break;
1041 case _HSE:
1042 case _HSE_KER:
1043 case _HSE_KER_DIV2:
1044 clock = stm32mp1_clk_get_fixed(priv, _HSE);
1045 if (p == _HSE_KER_DIV2)
1046 clock >>= 1;
1047 break;
1048 case _LSI:
1049 clock = stm32mp1_clk_get_fixed(priv, _LSI);
1050 break;
1051 case _LSE:
1052 clock = stm32mp1_clk_get_fixed(priv, _LSE);
1053 break;
1054 /* PLL */
1055 case _PLL1_P:
1056 case _PLL1_Q:
1057 case _PLL1_R:
1058 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
1059 break;
1060 case _PLL2_P:
1061 case _PLL2_Q:
1062 case _PLL2_R:
1063 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
1064 break;
1065 case _PLL3_P:
1066 case _PLL3_Q:
1067 case _PLL3_R:
1068 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
1069 break;
1070 case _PLL4_P:
1071 case _PLL4_Q:
1072 case _PLL4_R:
1073 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
1074 break;
1075 /* other */
1076 case _USB_PHY_48:
1077 clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
1078 break;
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02001079 case _DSI_PHY:
1080 {
1081 struct clk clk;
1082 struct udevice *dev = NULL;
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001083
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02001084 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
1085 &dev)) {
1086 if (clk_request(dev, &clk)) {
1087 pr_err("ck_dsi_phy request");
1088 } else {
1089 clk.id = 0;
1090 clock = clk_get_rate(&clk);
1091 }
1092 }
1093 break;
1094 }
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001095 default:
1096 break;
1097 }
1098
1099 debug("%s(%d) clock = %lx : %ld kHz\n",
1100 __func__, p, clock, clock / 1000);
1101
1102 return clock;
1103}
1104
1105static int stm32mp1_clk_enable(struct clk *clk)
1106{
1107 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1108 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1109 int i = stm32mp1_clk_get_id(priv, clk->id);
1110
1111 if (i < 0)
1112 return i;
1113
1114 if (gate[i].set_clr)
1115 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1116 else
1117 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1118
1119 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
1120
1121 return 0;
1122}
1123
1124static int stm32mp1_clk_disable(struct clk *clk)
1125{
1126 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1127 const struct stm32mp1_clk_gate *gate = priv->data->gate;
1128 int i = stm32mp1_clk_get_id(priv, clk->id);
1129
1130 if (i < 0)
1131 return i;
1132
1133 if (gate[i].set_clr)
1134 writel(BIT(gate[i].bit),
1135 priv->base + gate[i].offset
1136 + RCC_MP_ENCLRR_OFFSET);
1137 else
1138 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1139
1140 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
1141
1142 return 0;
1143}
1144
1145static ulong stm32mp1_clk_get_rate(struct clk *clk)
1146{
1147 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1148 int p = stm32mp1_clk_get_parent(priv, clk->id);
1149 ulong rate;
1150
1151 if (p < 0)
1152 return 0;
1153
1154 rate = stm32mp1_clk_get(priv, p);
1155
1156#ifdef DEBUG
1157 debug("%s: computed rate for id clock %d is %d (parent is %s)\n",
1158 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
1159#endif
1160 return rate;
1161}
1162
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001163#ifdef STM32MP1_CLOCK_TREE_INIT
1164static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
1165 u32 mask_on)
1166{
1167 u32 address = rcc + offset;
1168
1169 if (enable)
1170 setbits_le32(address, mask_on);
1171 else
1172 clrbits_le32(address, mask_on);
1173}
1174
1175static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
1176{
1177 if (enable)
1178 setbits_le32(rcc + RCC_OCENSETR, mask_on);
1179 else
1180 setbits_le32(rcc + RCC_OCENCLRR, mask_on);
1181}
1182
1183static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
1184 u32 mask_rdy)
1185{
1186 u32 mask_test = 0;
1187 u32 address = rcc + offset;
1188 u32 val;
1189 int ret;
1190
1191 if (enable)
1192 mask_test = mask_rdy;
1193
1194 ret = readl_poll_timeout(address, val,
1195 (val & mask_rdy) == mask_test,
1196 TIMEOUT_1S);
1197
1198 if (ret)
1199 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
1200 mask_rdy, address, enable, readl(address));
1201
1202 return ret;
1203}
1204
1205static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
1206{
1207 u32 value;
1208
1209 if (bypass)
1210 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
1211
1212 /*
1213 * warning: not recommended to switch directly from "high drive"
1214 * to "medium low drive", and vice-versa.
1215 */
1216 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
1217 >> RCC_BDCR_LSEDRV_SHIFT;
1218
1219 while (value != lsedrv) {
1220 if (value > lsedrv)
1221 value--;
1222 else
1223 value++;
1224
1225 clrsetbits_le32(rcc + RCC_BDCR,
1226 RCC_BDCR_LSEDRV_MASK,
1227 value << RCC_BDCR_LSEDRV_SHIFT);
1228 }
1229
1230 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
1231}
1232
1233static void stm32mp1_lse_wait(fdt_addr_t rcc)
1234{
1235 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
1236}
1237
1238static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
1239{
1240 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
1241 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
1242}
1243
1244static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
1245{
1246 if (bypass)
1247 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1248
1249 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
1250 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
1251
1252 if (css)
1253 setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1254}
1255
1256static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
1257{
1258 stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
1259 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
1260}
1261
1262static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
1263{
1264 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
1265 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
1266}
1267
1268static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
1269{
1270 u32 address = rcc + RCC_OCRDYR;
1271 u32 val;
1272 int ret;
1273
1274 clrsetbits_le32(rcc + RCC_HSICFGR,
1275 RCC_HSICFGR_HSIDIV_MASK,
1276 RCC_HSICFGR_HSIDIV_MASK & hsidiv);
1277
1278 ret = readl_poll_timeout(address, val,
1279 val & RCC_OCRDYR_HSIDIVRDY,
1280 TIMEOUT_200MS);
1281 if (ret)
1282 pr_err("HSIDIV failed @ 0x%x: 0x%x\n",
1283 address, readl(address));
1284
1285 return ret;
1286}
1287
1288static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
1289{
1290 u8 hsidiv;
1291 u32 hsidivfreq = MAX_HSI_HZ;
1292
1293 for (hsidiv = 0; hsidiv < 4; hsidiv++,
1294 hsidivfreq = hsidivfreq / 2)
1295 if (hsidivfreq == hsifreq)
1296 break;
1297
1298 if (hsidiv == 4) {
1299 pr_err("clk-hsi frequency invalid");
1300 return -1;
1301 }
1302
1303 if (hsidiv > 0)
1304 return stm32mp1_set_hsidiv(rcc, hsidiv);
1305
1306 return 0;
1307}
1308
1309static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
1310{
1311 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1312
1313 writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
1314}
1315
1316static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
1317{
1318 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1319 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1320 u32 val;
1321 int ret;
1322
1323 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
1324 TIMEOUT_200MS);
1325
1326 if (ret) {
1327 pr_err("PLL%d start failed @ 0x%x: 0x%x\n",
1328 pll_id, pllxcr, readl(pllxcr));
1329 return ret;
1330 }
1331
1332 /* start the requested output */
1333 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1334
1335 return 0;
1336}
1337
1338static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
1339{
1340 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1341 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1342 u32 val;
1343
1344 /* stop all output */
1345 clrbits_le32(pllxcr,
1346 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
1347
1348 /* stop PLL */
1349 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
1350
1351 /* wait PLL stopped */
1352 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
1353 TIMEOUT_200MS);
1354}
1355
1356static void pll_config_output(struct stm32mp1_clk_priv *priv,
1357 int pll_id, u32 *pllcfg)
1358{
1359 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1360 fdt_addr_t rcc = priv->base;
1361 u32 value;
1362
1363 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
1364 & RCC_PLLNCFGR2_DIVP_MASK;
1365 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
1366 & RCC_PLLNCFGR2_DIVQ_MASK;
1367 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
1368 & RCC_PLLNCFGR2_DIVR_MASK;
1369 writel(value, rcc + pll[pll_id].pllxcfgr2);
1370}
1371
1372static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
1373 u32 *pllcfg, u32 fracv)
1374{
1375 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1376 fdt_addr_t rcc = priv->base;
1377 enum stm32mp1_plltype type = pll[pll_id].plltype;
1378 int src;
1379 ulong refclk;
1380 u8 ifrge = 0;
1381 u32 value;
1382
1383 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
1384
1385 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
1386 (pllcfg[PLLCFG_M] + 1);
1387
1388 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
1389 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
1390 debug("invalid refclk = %x\n", (u32)refclk);
1391 return -EINVAL;
1392 }
1393 if (type == PLL_800 && refclk >= 8000000)
1394 ifrge = 1;
1395
1396 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
1397 & RCC_PLLNCFGR1_DIVN_MASK;
1398 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
1399 & RCC_PLLNCFGR1_DIVM_MASK;
1400 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
1401 & RCC_PLLNCFGR1_IFRGE_MASK;
1402 writel(value, rcc + pll[pll_id].pllxcfgr1);
1403
1404 /* fractional configuration: load sigma-delta modulator (SDM) */
1405
1406 /* Write into FRACV the new fractional value , and FRACLE to 0 */
1407 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
1408 rcc + pll[pll_id].pllxfracr);
1409
1410 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
1411 setbits_le32(rcc + pll[pll_id].pllxfracr,
1412 RCC_PLLNFRACR_FRACLE);
1413
1414 pll_config_output(priv, pll_id, pllcfg);
1415
1416 return 0;
1417}
1418
1419static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
1420{
1421 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1422 u32 pllxcsg;
1423
1424 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1425 RCC_PLLNCSGR_MOD_PER_MASK) |
1426 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1427 RCC_PLLNCSGR_INC_STEP_MASK) |
1428 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1429 RCC_PLLNCSGR_SSCG_MODE_MASK);
1430
1431 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
1432}
1433
1434static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
1435{
1436 u32 address = priv->base + (clksrc >> 4);
1437 u32 val;
1438 int ret;
1439
1440 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
1441 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
1442 TIMEOUT_200MS);
1443 if (ret)
1444 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
1445 clksrc, address, readl(address));
1446
1447 return ret;
1448}
1449
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001450static void stgen_config(struct stm32mp1_clk_priv *priv)
1451{
1452 int p;
1453 u32 stgenc, cntfid0;
1454 ulong rate;
1455
1456 stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
1457
1458 cntfid0 = readl(stgenc + STGENC_CNTFID0);
1459 p = stm32mp1_clk_get_parent(priv, STGEN_K);
1460 rate = stm32mp1_clk_get(priv, p);
1461
1462 if (cntfid0 != rate) {
1463 pr_debug("System Generic Counter (STGEN) update\n");
1464 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1465 writel(0x0, stgenc + STGENC_CNTCVL);
1466 writel(0x0, stgenc + STGENC_CNTCVU);
1467 writel(rate, stgenc + STGENC_CNTFID0);
1468 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
1469
1470 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
1471
1472 /* need to update gd->arch.timer_rate_hz with new frequency */
1473 timer_init();
1474 pr_debug("gd->arch.timer_rate_hz = %x\n",
1475 (u32)gd->arch.timer_rate_hz);
1476 pr_debug("Tick = %x\n", (u32)(get_ticks()));
1477 }
1478}
1479
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001480static int set_clkdiv(unsigned int clkdiv, u32 address)
1481{
1482 u32 val;
1483 int ret;
1484
1485 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
1486 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
1487 TIMEOUT_200MS);
1488 if (ret)
1489 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
1490 clkdiv, address, readl(address));
1491
1492 return ret;
1493}
1494
1495static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
1496 u32 clksrc, u32 clkdiv)
1497{
1498 u32 address = priv->base + (clksrc >> 4);
1499
1500 /*
1501 * binding clksrc : bit15-4 offset
1502 * bit3: disable
1503 * bit2-0: MCOSEL[2:0]
1504 */
1505 if (clksrc & 0x8) {
1506 clrbits_le32(address, RCC_MCOCFG_MCOON);
1507 } else {
1508 clrsetbits_le32(address,
1509 RCC_MCOCFG_MCOSRC_MASK,
1510 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1511 clrsetbits_le32(address,
1512 RCC_MCOCFG_MCODIV_MASK,
1513 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1514 setbits_le32(address, RCC_MCOCFG_MCOON);
1515 }
1516}
1517
1518static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
1519 unsigned int clksrc,
1520 int lse_css)
1521{
1522 u32 address = priv->base + RCC_BDCR;
1523
1524 if (readl(address) & RCC_BDCR_RTCCKEN)
1525 goto skip_rtc;
1526
1527 if (clksrc == CLK_RTC_DISABLED)
1528 goto skip_rtc;
1529
1530 clrsetbits_le32(address,
1531 RCC_BDCR_RTCSRC_MASK,
1532 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1533
1534 setbits_le32(address, RCC_BDCR_RTCCKEN);
1535
1536skip_rtc:
1537 if (lse_css)
1538 setbits_le32(address, RCC_BDCR_LSECSSON);
1539}
1540
1541static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
1542{
1543 u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
1544 u32 value = pkcs & 0xF;
1545 u32 mask = 0xF;
1546
1547 if (pkcs & BIT(31)) {
1548 mask <<= 4;
1549 value <<= 4;
1550 }
1551 clrsetbits_le32(address, mask, value);
1552}
1553
1554static int stm32mp1_clktree(struct udevice *dev)
1555{
1556 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1557 fdt_addr_t rcc = priv->base;
1558 unsigned int clksrc[CLKSRC_NB];
1559 unsigned int clkdiv[CLKDIV_NB];
1560 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1561 ofnode plloff[_PLL_NB];
1562 int ret;
1563 int i, len;
1564 int lse_css = 0;
1565 const u32 *pkcs_cell;
1566
1567 /* check mandatory field */
1568 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
1569 if (ret < 0) {
1570 debug("field st,clksrc invalid: error %d\n", ret);
1571 return -FDT_ERR_NOTFOUND;
1572 }
1573
1574 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
1575 if (ret < 0) {
1576 debug("field st,clkdiv invalid: error %d\n", ret);
1577 return -FDT_ERR_NOTFOUND;
1578 }
1579
1580 /* check mandatory field in each pll */
1581 for (i = 0; i < _PLL_NB; i++) {
1582 char name[12];
1583
1584 sprintf(name, "st,pll@%d", i);
1585 plloff[i] = dev_read_subnode(dev, name);
1586 if (!ofnode_valid(plloff[i]))
1587 continue;
1588 ret = ofnode_read_u32_array(plloff[i], "cfg",
1589 pllcfg[i], PLLCFG_NB);
1590 if (ret < 0) {
1591 debug("field cfg invalid: error %d\n", ret);
1592 return -FDT_ERR_NOTFOUND;
1593 }
1594 }
1595
1596 debug("configuration MCO\n");
1597 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1598 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1599
1600 debug("switch ON osillator\n");
1601 /*
1602 * switch ON oscillator found in device-tree,
1603 * HSI already ON after bootrom
1604 */
1605 if (priv->osc[_LSI])
1606 stm32mp1_lsi_set(rcc, 1);
1607
1608 if (priv->osc[_LSE]) {
1609 int bypass;
1610 int lsedrv;
1611 struct udevice *dev = priv->osc_dev[_LSE];
1612
1613 bypass = dev_read_bool(dev, "st,bypass");
1614 lse_css = dev_read_bool(dev, "st,css");
1615 lsedrv = dev_read_u32_default(dev, "st,drive",
1616 LSEDRV_MEDIUM_HIGH);
1617
1618 stm32mp1_lse_enable(rcc, bypass, lsedrv);
1619 }
1620
1621 if (priv->osc[_HSE]) {
1622 int bypass, css;
1623 struct udevice *dev = priv->osc_dev[_HSE];
1624
1625 bypass = dev_read_bool(dev, "st,bypass");
1626 css = dev_read_bool(dev, "st,css");
1627
1628 stm32mp1_hse_enable(rcc, bypass, css);
1629 }
1630 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1631 * => switch on CSI even if node is not present in device tree
1632 */
1633 stm32mp1_csi_set(rcc, 1);
1634
1635 /* come back to HSI */
1636 debug("come back to HSI\n");
1637 set_clksrc(priv, CLK_MPU_HSI);
1638 set_clksrc(priv, CLK_AXI_HSI);
1639 set_clksrc(priv, CLK_MCU_HSI);
1640
1641 debug("pll stop\n");
1642 for (i = 0; i < _PLL_NB; i++)
1643 pll_stop(priv, i);
1644
1645 /* configure HSIDIV */
1646 debug("configure HSIDIV\n");
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001647 if (priv->osc[_HSI]) {
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001648 stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001649 stgen_config(priv);
1650 }
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001651
1652 /* select DIV */
1653 debug("select DIV\n");
1654 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1655 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
1656 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
1657 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
1658 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
1659 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
1660 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
1661 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
1662 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
1663
1664 /* no ready bit for RTC */
1665 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
1666
1667 /* configure PLLs source */
1668 debug("configure PLLs source\n");
1669 set_clksrc(priv, clksrc[CLKSRC_PLL12]);
1670 set_clksrc(priv, clksrc[CLKSRC_PLL3]);
1671 set_clksrc(priv, clksrc[CLKSRC_PLL4]);
1672
1673 /* configure and start PLLs */
1674 debug("configure PLLs\n");
1675 for (i = 0; i < _PLL_NB; i++) {
1676 u32 fracv;
1677 u32 csg[PLLCSG_NB];
1678
1679 debug("configure PLL %d @ %d\n", i,
1680 ofnode_to_offset(plloff[i]));
1681 if (!ofnode_valid(plloff[i]))
1682 continue;
1683
1684 fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
1685 pll_config(priv, i, pllcfg[i], fracv);
1686 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
1687 if (!ret) {
1688 pll_csg(priv, i, csg);
1689 } else if (ret != -FDT_ERR_NOTFOUND) {
1690 debug("invalid csg node for pll@%d res=%d\n", i, ret);
1691 return ret;
1692 }
1693 pll_start(priv, i);
1694 }
1695
1696 /* wait and start PLLs ouptut when ready */
1697 for (i = 0; i < _PLL_NB; i++) {
1698 if (!ofnode_valid(plloff[i]))
1699 continue;
1700 debug("output PLL %d\n", i);
1701 pll_output(priv, i, pllcfg[i][PLLCFG_O]);
1702 }
1703
1704 /* wait LSE ready before to use it */
1705 if (priv->osc[_LSE])
1706 stm32mp1_lse_wait(rcc);
1707
1708 /* configure with expected clock source */
1709 debug("CLKSRC\n");
1710 set_clksrc(priv, clksrc[CLKSRC_MPU]);
1711 set_clksrc(priv, clksrc[CLKSRC_AXI]);
1712 set_clksrc(priv, clksrc[CLKSRC_MCU]);
1713 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
1714
1715 /* configure PKCK */
1716 debug("PKCK\n");
1717 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
1718 if (pkcs_cell) {
1719 bool ckper_disabled = false;
1720
1721 for (i = 0; i < len / sizeof(u32); i++) {
1722 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
1723
1724 if (pkcs == CLK_CKPER_DISABLED) {
1725 ckper_disabled = true;
1726 continue;
1727 }
1728 pkcs_config(priv, pkcs);
1729 }
1730 /* CKPER is source for some peripheral clock
1731 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1732 * only if previous clock is still ON
1733 * => deactivated CKPER only after switching clock
1734 */
1735 if (ckper_disabled)
1736 pkcs_config(priv, CLK_CKPER_DISABLED);
1737 }
1738
Patrick Delaunaybf7d9442018-03-20 11:41:25 +01001739 /* STGEN clock source can change with CLK_STGEN_XXX */
1740 stgen_config(priv);
1741
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001742 debug("oscillator off\n");
1743 /* switch OFF HSI if not found in device-tree */
1744 if (!priv->osc[_HSI])
1745 stm32mp1_hsi_set(rcc, 0);
1746
1747 /* Software Self-Refresh mode (SSR) during DDR initilialization */
1748 clrsetbits_le32(priv->base + RCC_DDRITFCR,
1749 RCC_DDRITFCR_DDRCKMOD_MASK,
1750 RCC_DDRITFCR_DDRCKMOD_SSR <<
1751 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1752
1753 return 0;
1754}
1755#endif /* STM32MP1_CLOCK_TREE_INIT */
1756
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02001757static int pll_set_output_rate(struct udevice *dev,
1758 int pll_id,
1759 int div_id,
1760 unsigned long clk_rate)
1761{
1762 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1763 const struct stm32mp1_clk_pll *pll = priv->data->pll;
1764 u32 pllxcr = priv->base + pll[pll_id].pllxcr;
1765 int div;
1766 ulong fvco;
1767
1768 if (div_id > _DIV_NB)
1769 return -EINVAL;
1770
1771 fvco = pll_get_fvco(priv, pll_id);
1772
1773 if (fvco <= clk_rate)
1774 div = 1;
1775 else
1776 div = DIV_ROUND_UP(fvco, clk_rate);
1777
1778 if (div > 128)
1779 div = 128;
1780
1781 debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
1782 /* stop the requested output */
1783 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1784 /* change divider */
1785 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
1786 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
1787 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
1788 /* start the requested output */
1789 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
1790
1791 return 0;
1792}
1793
1794static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
1795{
1796 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
1797 int p;
1798
1799 switch (clk->id) {
1800 case LTDC_PX:
1801 case DSI_PX:
1802 break;
1803 default:
1804 pr_err("not supported");
1805 return -EINVAL;
1806 }
1807
1808 p = stm32mp1_clk_get_parent(priv, clk->id);
1809 if (p < 0)
1810 return -EINVAL;
1811
1812 switch (p) {
1813 case _PLL4_Q:
1814 /* for LTDC_PX and DSI_PX case */
1815 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
1816 }
1817
1818 return -EINVAL;
1819}
1820
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001821static void stm32mp1_osc_clk_init(const char *name,
1822 struct stm32mp1_clk_priv *priv,
1823 int index)
1824{
1825 struct clk clk;
1826 struct udevice *dev = NULL;
1827
1828 priv->osc[index] = 0;
1829 clk.id = 0;
1830 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
1831 if (clk_request(dev, &clk))
1832 pr_err("%s request", name);
1833 else
1834 priv->osc[index] = clk_get_rate(&clk);
1835 }
1836 priv->osc_dev[index] = dev;
1837}
1838
1839static void stm32mp1_osc_init(struct udevice *dev)
1840{
1841 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1842 int i;
1843 const char *name[NB_OSC] = {
1844 [_LSI] = "clk-lsi",
1845 [_LSE] = "clk-lse",
1846 [_HSI] = "clk-hsi",
1847 [_HSE] = "clk-hse",
1848 [_CSI] = "clk-csi",
1849 [_I2S_CKIN] = "i2s_ckin",
1850 [_USB_PHY_48] = "ck_usbo_48m"};
1851
1852 for (i = 0; i < NB_OSC; i++) {
1853 stm32mp1_osc_clk_init(name[i], priv, i);
1854 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
1855 }
1856}
1857
1858static int stm32mp1_clk_probe(struct udevice *dev)
1859{
1860 int result = 0;
1861 struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
1862
1863 priv->base = dev_read_addr(dev->parent);
1864 if (priv->base == FDT_ADDR_T_NONE)
1865 return -EINVAL;
1866
1867 priv->data = (void *)&stm32mp1_data;
1868
1869 if (!priv->data->gate || !priv->data->sel ||
1870 !priv->data->pll)
1871 return -EINVAL;
1872
1873 stm32mp1_osc_init(dev);
1874
Patrick Delaunayf11398e2018-03-12 10:46:16 +01001875#ifdef STM32MP1_CLOCK_TREE_INIT
1876 /* clock tree init is done only one time, before relocation */
1877 if (!(gd->flags & GD_FLG_RELOC))
1878 result = stm32mp1_clktree(dev);
1879#endif
1880
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001881 return result;
1882}
1883
1884static const struct clk_ops stm32mp1_clk_ops = {
1885 .enable = stm32mp1_clk_enable,
1886 .disable = stm32mp1_clk_disable,
1887 .get_rate = stm32mp1_clk_get_rate,
Patrick Delaunay8314d2c2018-07-16 10:41:43 +02001888 .set_rate = stm32mp1_clk_set_rate,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001889};
1890
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001891U_BOOT_DRIVER(stm32mp1_clock) = {
1892 .name = "stm32mp1_clk",
1893 .id = UCLASS_CLK,
Patrick Delaunaye6ab6272018-03-12 10:46:15 +01001894 .ops = &stm32mp1_clk_ops,
1895 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
1896 .probe = stm32mp1_clk_probe,
1897};