blob: 78c1e965c9f54f789cb75c5ff07a04abcc342184 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chandan Nath7d744102011-10-14 02:58:26 +00002/*
3 * board.c
4 *
5 * Common board functions for AM33XX based boards
6 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -05007 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
Chandan Nath7d744102011-10-14 02:58:26 +00008 */
9
Tom Riniefd9f332024-04-30 07:35:39 -060010#include <config.h>
Simon Glass91d03902014-10-22 21:37:10 -060011#include <dm.h>
Lokesh Vutla1d3bfcd2017-05-05 13:45:28 +053012#include <debug_uart.h>
Tom Rini59c2cc92012-07-30 16:13:10 -070013#include <errno.h>
Simon Glassfc557362022-03-04 08:43:05 -070014#include <event.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -070015#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060016#include <net.h>
Simon Glassccc03a72014-10-22 21:37:11 -060017#include <ns16550.h>
Faiz Abbas618ba9f2020-09-14 12:11:15 +053018#include <omap3_spi.h>
Tom Rini28591df2012-08-13 12:03:19 -070019#include <spl.h>
Chandan Nath7d744102011-10-14 02:58:26 +000020#include <asm/arch/cpu.h>
21#include <asm/arch/hardware.h>
Chandan Nath77a73fe2012-01-09 20:38:59 +000022#include <asm/arch/omap.h>
Chandan Nath7d744102011-10-14 02:58:26 +000023#include <asm/arch/ddr_defs.h>
24#include <asm/arch/clock.h>
Steve Sakoman6229e332012-06-04 05:35:34 +000025#include <asm/arch/gpio.h>
Jean-Jacques Hiblotbf926262018-12-07 14:50:43 +010026#include <asm/arch/i2c.h>
Moses Christophera7038d12021-06-11 16:13:34 +000027#if IS_ENABLED(CONFIG_TARGET_AM335X_GUARDIAN)
28#include <asm/arch/mem-guardian.h>
29#else
Ilya Yanok2ebbb862012-11-06 13:06:30 +000030#include <asm/arch/mem.h>
Moses Christophera7038d12021-06-11 16:13:34 +000031#endif
Chandan Nath77a73fe2012-01-09 20:38:59 +000032#include <asm/arch/mmc_host_def.h>
Tom Rini7a247722012-07-31 10:50:01 -070033#include <asm/arch/sys_proto.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060034#include <asm/global_data.h>
Chandan Nath7d744102011-10-14 02:58:26 +000035#include <asm/io.h>
Tom Rini3fd44562012-07-03 08:51:34 -070036#include <asm/emif.h>
Tom Rini4b302402012-07-31 08:55:01 -070037#include <asm/gpio.h>
Semen Protsenkoa8cb0222017-06-02 18:00:00 +030038#include <asm/omap_common.h>
Tom Rini59c2cc92012-07-30 16:13:10 -070039#include <i2c.h>
40#include <miiphy.h>
41#include <cpsw.h>
Simon Glassdbd79542020-05-10 11:40:11 -060042#include <linux/delay.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090043#include <linux/errno.h>
Tom Riniac8fdf92013-08-30 16:28:44 -040044#include <linux/compiler.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060045#include <linux/printk.h>
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +000046#include <linux/usb/ch9.h>
47#include <linux/usb/gadget.h>
48#include <linux/usb/musb.h>
49#include <asm/omap_musb.h>
Tom Rini56424eb2013-08-28 09:00:28 -040050#include <asm/davinci_rtc.h>
Chandan Nath7d744102011-10-14 02:58:26 +000051
Brad Griffis4b025082019-04-29 09:59:30 +053052#define AM43XX_EMIF_BASE 0x4C000000
53#define AM43XX_SDRAM_CONFIG_OFFSET 0x8
54#define AM43XX_SDRAM_TYPE_MASK 0xE0000000
55#define AM43XX_SDRAM_TYPE_SHIFT 29
56#define AM43XX_SDRAM_TYPE_DDR3 3
57#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
58#define AM43XX_RDWRLVLFULL_START 0x80000000
59
Faiz Abbas618ba9f2020-09-14 12:11:15 +053060/* SPI flash. */
61#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
62#define AM33XX_SPI0_BASE 0x48030000
63#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
64#endif
65
Chandan Nath7d744102011-10-14 02:58:26 +000066DECLARE_GLOBAL_DATA_PTR;
67
Tom Rinifbb25522017-05-16 14:46:35 -040068int dram_init(void)
69{
Tom Rinie1e85442021-08-27 21:18:30 -040070#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Tom Rinifbb25522017-05-16 14:46:35 -040071 sdram_init();
72#endif
73
74 /* dram_init must store complete ramsize in gd->ram_size */
75 gd->ram_size = get_ram_size(
Tom Rinibb4dd962022-11-16 13:10:37 -050076 (void *)CFG_SYS_SDRAM_BASE,
Tom Rinidb9c39e2022-12-04 10:04:51 -050077 CFG_MAX_RAM_BANK_SIZE);
Tom Rinifbb25522017-05-16 14:46:35 -040078 return 0;
79}
80
81int dram_init_banksize(void)
82{
Tom Rinibb4dd962022-11-16 13:10:37 -050083 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
Tom Rinifbb25522017-05-16 14:46:35 -040084 gd->bd->bi_dram[0].size = gd->ram_size;
85
86 return 0;
87}
88
Tom Rini18dc02e2015-12-06 11:09:59 -050089#if !CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glassb75b15b2020-12-03 16:55:23 -070090static const struct ns16550_plat am33xx_serial[] = {
Tom Rinidf6a2152022-11-16 13:10:28 -050091 { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2,
92 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
93# ifdef CFG_SYS_NS16550_COM2
94 { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2,
95 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
96# ifdef CFG_SYS_NS16550_COM3
97 { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2,
98 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
99 { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2,
100 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
101 { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2,
102 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
103 { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2,
104 .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
Simon Glassccc03a72014-10-22 21:37:11 -0600105# endif
Tom Rini5ba15962015-07-31 19:55:08 -0400106# endif
Simon Glassccc03a72014-10-22 21:37:11 -0600107};
108
Simon Glass1d8364a2020-12-28 20:34:54 -0700109U_BOOT_DRVINFOS(am33xx_uarts) = {
Tom Rini18dc02e2015-12-06 11:09:59 -0500110 { "ns16550_serial", &am33xx_serial[0] },
Tom Rinidf6a2152022-11-16 13:10:28 -0500111# ifdef CFG_SYS_NS16550_COM2
Tom Rini18dc02e2015-12-06 11:09:59 -0500112 { "ns16550_serial", &am33xx_serial[1] },
Tom Rinidf6a2152022-11-16 13:10:28 -0500113# ifdef CFG_SYS_NS16550_COM3
Tom Rini18dc02e2015-12-06 11:09:59 -0500114 { "ns16550_serial", &am33xx_serial[2] },
115 { "ns16550_serial", &am33xx_serial[3] },
116 { "ns16550_serial", &am33xx_serial[4] },
117 { "ns16550_serial", &am33xx_serial[5] },
Simon Glassccc03a72014-10-22 21:37:11 -0600118# endif
119# endif
120};
Tom Rini937fd032016-01-05 12:17:15 -0500121
Igor Opaniukf7c91762021-02-09 13:52:45 +0200122#if CONFIG_IS_ENABLED(DM_I2C)
Simon Glassb75b15b2020-12-03 16:55:23 -0700123static const struct omap_i2c_plat am33xx_i2c[] = {
Jean-Jacques Hiblotbf926262018-12-07 14:50:43 +0100124 { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
125 { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
126 { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
127};
128
Simon Glass1d8364a2020-12-28 20:34:54 -0700129U_BOOT_DRVINFOS(am33xx_i2c) = {
Jean-Jacques Hiblotbf926262018-12-07 14:50:43 +0100130 { "i2c_omap", &am33xx_i2c[0] },
131 { "i2c_omap", &am33xx_i2c[1] },
132 { "i2c_omap", &am33xx_i2c[2] },
133};
134#endif
135
Simon Glassfa4689a2019-12-06 21:41:35 -0700136#if CONFIG_IS_ENABLED(DM_GPIO)
Simon Glassb75b15b2020-12-03 16:55:23 -0700137static const struct omap_gpio_plat am33xx_gpio[] = {
Tom Rini937fd032016-01-05 12:17:15 -0500138 { 0, AM33XX_GPIO0_BASE },
139 { 1, AM33XX_GPIO1_BASE },
140 { 2, AM33XX_GPIO2_BASE },
141 { 3, AM33XX_GPIO3_BASE },
142#ifdef CONFIG_AM43XX
143 { 4, AM33XX_GPIO4_BASE },
144 { 5, AM33XX_GPIO5_BASE },
Tom Rini5ba15962015-07-31 19:55:08 -0400145#endif
Tom Rini937fd032016-01-05 12:17:15 -0500146};
Simon Glassccc03a72014-10-22 21:37:11 -0600147
Simon Glass1d8364a2020-12-28 20:34:54 -0700148U_BOOT_DRVINFOS(am33xx_gpios) = {
Tom Rini937fd032016-01-05 12:17:15 -0500149 { "gpio_omap", &am33xx_gpio[0] },
150 { "gpio_omap", &am33xx_gpio[1] },
151 { "gpio_omap", &am33xx_gpio[2] },
152 { "gpio_omap", &am33xx_gpio[3] },
153#ifdef CONFIG_AM43XX
154 { "gpio_omap", &am33xx_gpio[4] },
155 { "gpio_omap", &am33xx_gpio[5] },
156#endif
Faiz Abbas618ba9f2020-09-14 12:11:15 +0530157};
158#endif
159#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
160static const struct omap3_spi_plat omap3_spi_pdata = {
161 .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
162 .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
163};
164
Simon Glass1d8364a2020-12-28 20:34:54 -0700165U_BOOT_DRVINFO(am33xx_spi) = {
Faiz Abbas618ba9f2020-09-14 12:11:15 +0530166 .name = "omap3_spi",
Simon Glass71fa5b42020-12-03 16:55:18 -0700167 .plat = &omap3_spi_pdata,
Tom Rini937fd032016-01-05 12:17:15 -0500168};
169#endif
170#endif
Simon Glass91d03902014-10-22 21:37:10 -0600171
Simon Glassfa4689a2019-12-06 21:41:35 -0700172#if !CONFIG_IS_ENABLED(DM_GPIO)
Dave Gerlach00822ca2014-02-10 11:41:49 -0500173static const struct gpio_bank gpio_bank_am33xx[] = {
Tom Rini7bc2bca2015-07-31 19:55:09 -0400174 { (void *)AM33XX_GPIO0_BASE },
175 { (void *)AM33XX_GPIO1_BASE },
176 { (void *)AM33XX_GPIO2_BASE },
177 { (void *)AM33XX_GPIO3_BASE },
Dave Gerlach00822ca2014-02-10 11:41:49 -0500178#ifdef CONFIG_AM43XX
Tom Rini7bc2bca2015-07-31 19:55:09 -0400179 { (void *)AM33XX_GPIO4_BASE },
180 { (void *)AM33XX_GPIO5_BASE },
Dave Gerlach00822ca2014-02-10 11:41:49 -0500181#endif
Steve Sakoman6229e332012-06-04 05:35:34 +0000182};
183
184const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
Simon Glass91d03902014-10-22 21:37:10 -0600185#endif
186
Jean-Jacques Hiblote0e319a2017-02-01 11:39:14 +0100187#if defined(CONFIG_MMC_OMAP_HS)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900188int cpu_mmc_init(struct bd_info *bis)
Chandan Nathd6e97f82012-01-09 20:38:58 +0000189{
Tom Rini0dc71d12012-08-08 10:31:08 -0700190 int ret;
Peter Korsgaardaabb9f82012-10-18 01:21:10 +0000191
Nikita Kiryanov4be9dbc2012-12-03 02:19:47 +0000192 ret = omap_mmc_init(0, 0, 0, -1, -1);
Tom Rini0dc71d12012-08-08 10:31:08 -0700193 if (ret)
194 return ret;
195
Nikita Kiryanov4be9dbc2012-12-03 02:19:47 +0000196 return omap_mmc_init(1, 0, 0, -1, -1);
Chandan Nathd6e97f82012-01-09 20:38:58 +0000197}
198#endif
Chandan Nath77a73fe2012-01-09 20:38:59 +0000199
Tero Kristo5d6acae2018-03-17 13:32:52 +0530200/*
201 * RTC only with DDR in self-refresh mode magic value, checked against during
202 * boot to see if we have a valid config. This should be in sync with the value
203 * that will be in drivers/soc/ti/pm33xx.c.
204 */
205#define RTC_MAGIC_VAL 0x8cd0
206
207/* Board type field bit shift for RTC only with DDR in self-refresh mode */
208#define RTC_BOARD_TYPE_SHIFT 16
209
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000210/* AM33XX has two MUSB controllers which can be host or gadget */
Tom Rini26e57e52022-03-21 21:33:27 -0400211#if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
212 defined(CONFIG_SPL_BUILD)
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100213
214static struct musb_hdrc_config musb_config = {
215 .multipoint = 1,
216 .dyn_fifo = 1,
217 .num_eps = 16,
218 .ram_bits = 12,
219};
220
Tom Rini26e57e52022-03-21 21:33:27 -0400221#ifdef CONFIG_AM335X_USB0
Simon Glassb75b15b2020-12-03 16:55:23 -0700222static struct ti_musb_plat usb0 = {
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100223 .base = (void *)USB0_OTG_BASE,
224 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
225 .plat = {
226 .config = &musb_config,
227 .power = 50,
228 .platform_ops = &musb_dsps_ops,
229 },
230};
Tom Rini26e57e52022-03-21 21:33:27 -0400231#endif
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100232
Tom Rini26e57e52022-03-21 21:33:27 -0400233#ifdef CONFIG_AM335X_USB1
Simon Glassb75b15b2020-12-03 16:55:23 -0700234static struct ti_musb_plat usb1 = {
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100235 .base = (void *)USB1_OTG_BASE,
236 .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
237 .plat = {
238 .config = &musb_config,
239 .power = 50,
240 .platform_ops = &musb_dsps_ops,
241 },
242};
Tom Rini26e57e52022-03-21 21:33:27 -0400243#endif
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100244
Simon Glass1d8364a2020-12-28 20:34:54 -0700245U_BOOT_DRVINFOS(am33xx_usbs) = {
Tom Rinid10c0ac2022-03-11 23:07:29 -0500246#ifdef CONFIG_AM335X_USB0_PERIPHERAL
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100247 { "ti-musb-peripheral", &usb0 },
Tom Rinid10c0ac2022-03-11 23:07:29 -0500248#elif defined(CONFIG_AM335X_USB0_HOST)
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100249 { "ti-musb-host", &usb0 },
250#endif
Tom Rinid10c0ac2022-03-11 23:07:29 -0500251#ifdef CONFIG_AM335X_USB1_PERIPHERAL
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100252 { "ti-musb-peripheral", &usb1 },
Tom Rinid10c0ac2022-03-11 23:07:29 -0500253#elif defined(CONFIG_AM335X_USB1_HOST)
Jean-Jacques Hiblot103d0032018-12-04 11:30:58 +0100254 { "ti-musb-host", &usb1 },
255#endif
256};
257
258int arch_misc_init(void)
259{
260 return 0;
261}
Alexandru Gagniucff16f882017-02-06 19:17:33 -0800262#else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
263
264int arch_misc_init(void)
265{
Mugunthan V N4b1d29a2016-11-17 14:38:09 +0530266 struct udevice *dev;
267 int ret;
268
Michal Suchanekac12a2f2022-10-12 21:57:59 +0200269 ret = uclass_first_device_err(UCLASS_MISC, &dev);
270 if (ret)
Mugunthan V N4b1d29a2016-11-17 14:38:09 +0530271 return ret;
Mugunthan V N6ad84ba2016-11-17 14:38:13 +0530272
273#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
Trevor Woernerc4e78c32023-08-30 22:49:50 -0400274 usb_ether_init();
Mugunthan V N6ad84ba2016-11-17 14:38:13 +0530275#endif
Alexandru Gagniucff16f882017-02-06 19:17:33 -0800276
Ilya Yanok7aa1a6e2012-11-06 13:48:23 +0000277 return 0;
278}
Heiko Schocher8aa1da92013-06-05 07:47:56 +0200279
Alexandru Gagniucff16f882017-02-06 19:17:33 -0800280#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
281
Tom Rinie1e85442021-08-27 21:18:30 -0400282#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Tero Kristo5d6acae2018-03-17 13:32:52 +0530283
284#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
285 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
286static void rtc32k_unlock(struct davinci_rtc *rtc)
287{
288 /*
289 * Unlock the RTC's registers. For more details please see the
290 * RTC_SS section of the TRM. In order to unlock we need to
291 * write these specific values (keys) in this order.
292 */
293 writel(RTC_KICK0R_WE, &rtc->kick0r);
294 writel(RTC_KICK1R_WE, &rtc->kick1r);
295}
296#endif
297
298#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
299/*
300 * Write contents of the RTC_SCRATCH1 register based on board type
301 * Two things are passed
302 * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
303 * control gets to kernel, kernel reads the scratchpad register and gets to
304 * know that bootloader has rtc_only support.
305 *
306 * Second important thing is the board type (16:31). This is needed in the
307 * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
308 * identify the board type and we go ahead and copy the board strings to
309 * am43xx_board_name.
310 */
311void update_rtc_magic(void)
312{
313 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
314 u32 magic = RTC_MAGIC_VAL;
315
316 magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
317
318 rtc32k_unlock(rtc);
319
320 /* write magic */
321 writel(magic, &rtc->scratch1);
322}
323#endif
324
Tom Riniac8fdf92013-08-30 16:28:44 -0400325/*
Tom Rini9fec9ae2014-05-21 12:57:22 -0400326 * In the case of non-SPL based booting we'll want to call these
327 * functions a tiny bit later as it will require gd to be set and cleared
328 * and that's not true in s_init in this case so we cannot do it there.
329 */
330int board_early_init_f(void)
331{
Tom Rini9fec9ae2014-05-21 12:57:22 -0400332 set_mux_conf_regs();
Marek Vasut0de45b82019-05-25 22:40:35 +0200333 prcm_init();
Tero Kristo5d6acae2018-03-17 13:32:52 +0530334#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
335 update_rtc_magic();
336#endif
Tom Rini9fec9ae2014-05-21 12:57:22 -0400337 return 0;
338}
339
340/*
Tom Riniac8fdf92013-08-30 16:28:44 -0400341 * This function is the place to do per-board things such as ramp up the
342 * MPU clock frequency.
343 */
344__weak void am33xx_spl_board_init(void)
345{
346}
347
Heiko Schocher2233e462013-11-04 14:05:00 +0100348#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530349static void rtc32k_enable(void)
Heiko Schocher8aa1da92013-06-05 07:47:56 +0200350{
Tom Rini56424eb2013-08-28 09:00:28 -0400351 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
Heiko Schocher8aa1da92013-06-05 07:47:56 +0200352
Tero Kristo5d6acae2018-03-17 13:32:52 +0530353 rtc32k_unlock(rtc);
Heiko Schocher8aa1da92013-06-05 07:47:56 +0200354
355 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
356 writel((1 << 3) | (1 << 6), &rtc->osc);
357}
Heiko Schocher2233e462013-11-04 14:05:00 +0100358#endif
Heiko Schocher57004c52013-06-04 11:00:57 +0200359
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530360static void uart_soft_reset(void)
Heiko Schocher57004c52013-06-04 11:00:57 +0200361{
362 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
363 u32 regval;
364
365 regval = readl(&uart_base->uartsyscfg);
366 regval |= UART_RESET;
367 writel(regval, &uart_base->uartsyscfg);
368 while ((readl(&uart_base->uartsyssts) &
369 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
370 ;
371
372 /* Disable smart idle */
373 regval = readl(&uart_base->uartsyscfg);
374 regval |= UART_SMART_IDLE_EN;
375 writel(regval, &uart_base->uartsyscfg);
376}
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530377
378static void watchdog_disable(void)
379{
380 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
381
382 writel(0xAAAA, &wdtimer->wdtwspr);
383 while (readl(&wdtimer->wdtwwps) != 0x0)
384 ;
385 writel(0x5555, &wdtimer->wdtwspr);
386 while (readl(&wdtimer->wdtwwps) != 0x0)
387 ;
388}
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530389
Tero Kristo5d6acae2018-03-17 13:32:52 +0530390#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
391/*
392 * Check if we are executing rtc-only + DDR mode, and resume from it if needed
393 */
394static void rtc_only(void)
395{
396 struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
Russ Dillbe5bacc2018-03-20 12:23:00 +0530397 struct prm_device_inst *prm_device =
398 (struct prm_device_inst *)PRM_DEVICE_INST;
399
Brad Griffis4b025082019-04-29 09:59:30 +0530400 u32 scratch1, sdrc;
Tero Kristo5d6acae2018-03-17 13:32:52 +0530401 void (*resume_func)(void);
402
403 scratch1 = readl(&rtc->scratch1);
404
405 /*
406 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
407 * written to this register when we want to wake up from RTC only
408 * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
409 * bits 0-15: RTC_MAGIC_VAL
410 * bits 16-31: board type (needed for sdram_init)
411 */
412 if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
413 return;
414
415 rtc32k_unlock(rtc);
416
417 /* Clear RTC magic */
418 writel(0, &rtc->scratch1);
419
420 /*
421 * Update board type based on value stored on RTC_SCRATCH1, this
422 * is done so that we don't need to read the board type from eeprom
423 * over i2c bus which is expensive
424 */
425 rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
426
Russ Dillbe5bacc2018-03-20 12:23:00 +0530427 /*
428 * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
429 * are resuming from self-refresh. This avoids an unnecessary re-init
430 * of the DDR. The re-init takes time and we would need to wait for
431 * it to complete before accessing DDR to avoid L3 NOC errors.
432 */
433 writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
434
Tero Kristo5d6acae2018-03-17 13:32:52 +0530435 rtc_only_prcm_init();
436 sdram_init();
437
Brad Griffis4b025082019-04-29 09:59:30 +0530438 /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
439 /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
440 sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
441
442 sdrc &= AM43XX_SDRAM_TYPE_MASK;
443 sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
444
445 if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
446 writel(AM43XX_RDWRLVLFULL_START,
447 AM43XX_EMIF_BASE +
448 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
449 mdelay(1);
450
451am43xx_wait:
452 sdrc = readl(AM43XX_EMIF_BASE +
453 AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
454 if (sdrc == AM43XX_RDWRLVLFULL_START)
455 goto am43xx_wait;
456 }
457
Tero Kristo5d6acae2018-03-17 13:32:52 +0530458 resume_func = (void *)readl(&rtc->scratch0);
459 if (resume_func)
460 resume_func();
461}
462#endif
463
Lokesh Vutlab5056182016-10-14 10:35:23 +0530464void s_init(void)
Simon Glass0c078ea2015-03-03 08:03:02 -0700465{
Tero Kristo5d6acae2018-03-17 13:32:52 +0530466#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
467 rtc_only();
468#endif
Simon Glass0c078ea2015-03-03 08:03:02 -0700469}
Simon Glass0c078ea2015-03-03 08:03:02 -0700470
Lokesh Vutlab5056182016-10-14 10:35:23 +0530471void early_system_init(void)
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530472{
473 /*
474 * The ROM will only have set up sufficient pinmux to allow for the
475 * first 4KiB NOR to be read, we must finish doing what we know of
476 * the NOR mux in this space in order to continue.
477 */
478#ifdef CONFIG_NOR_BOOT
479 enable_norboot_pin_mux();
480#endif
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530481 watchdog_disable();
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530482 set_uart_mux_conf();
Lokesh Vutlad33266b2016-10-14 10:35:24 +0530483 setup_early_clocks();
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530484 uart_soft_reset();
Lokesh Vutlaca23da12017-06-27 13:50:56 +0530485#ifdef CONFIG_SPL_BUILD
486 /*
487 * Save the boot parameters passed from romcode.
488 * We cannot delay the saving further than this,
489 * to prevent overwrites.
490 */
491 save_omap_boot_params();
492#endif
Lokesh Vutla1d3bfcd2017-05-05 13:45:28 +0530493#ifdef CONFIG_DEBUG_UART_OMAP
494 debug_uart_init();
495#endif
Jean-Jacques Hiblot3a502f62018-12-07 14:50:45 +0100496
Faiz Abbas3e73a182018-01-24 14:44:49 +0530497#ifdef CONFIG_SPL_BUILD
498 spl_early_init();
499#endif
Jean-Jacques Hiblot3a502f62018-12-07 14:50:45 +0100500
501#ifdef CONFIG_TI_I2C_BOARD_DETECT
502 do_board_detect();
503#endif
504
Heiko Schocher2233e462013-11-04 14:05:00 +0100505#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530506 /* Enable RTC32K clock */
507 rtc32k_enable();
Heiko Schocher2233e462013-11-04 14:05:00 +0100508#endif
Heiko Schocherb21f2ac2013-07-30 10:48:54 +0530509}
Lokesh Vutlab5056182016-10-14 10:35:23 +0530510
511#ifdef CONFIG_SPL_BUILD
512void board_init_f(ulong dummy)
513{
Semen Protsenkoa8cb0222017-06-02 18:00:00 +0300514 hw_data_init();
Lokesh Vutlab5056182016-10-14 10:35:23 +0530515 early_system_init();
516 board_early_init_f();
517 sdram_init();
Lokesh Vutlabed46ef2017-04-18 17:27:24 +0530518 /* dram_init must store complete ramsize in gd->ram_size */
519 gd->ram_size = get_ram_size(
Tom Rinibb4dd962022-11-16 13:10:37 -0500520 (void *)CFG_SYS_SDRAM_BASE,
Tom Rinidb9c39e2022-12-04 10:04:51 -0500521 CFG_MAX_RAM_BANK_SIZE);
Lokesh Vutlab5056182016-10-14 10:35:23 +0530522}
Tom Rini35c616c2014-03-05 14:57:47 -0500523#endif
Lokesh Vutlab5056182016-10-14 10:35:23 +0530524
525#endif
526
Simon Glassb8357c12023-08-21 21:16:56 -0600527static int am33xx_dm_post_init(void)
Lokesh Vutlab5056182016-10-14 10:35:23 +0530528{
Semen Protsenkoa8cb0222017-06-02 18:00:00 +0300529 hw_data_init();
Tom Rinie1e85442021-08-27 21:18:30 -0400530#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
Lokesh Vutlab5056182016-10-14 10:35:23 +0530531 early_system_init();
532#endif
533 return 0;
534}
Simon Glassb8357c12023-08-21 21:16:56 -0600535EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init);