Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/system.h> |
R Sricharan | 0871607 | 2013-03-04 20:04:44 +0000 | [diff] [blame] | 9 | #include <asm/cache.h> |
| 10 | #include <linux/compiler.h> |
Lokesh Vutla | 19858f9 | 2018-04-26 18:21:31 +0530 | [diff] [blame] | 11 | #include <asm/armv7_mpu.h> |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 12 | |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 13 | #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 14 | |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
Lokesh Vutla | 19858f9 | 2018-04-26 18:21:31 +0530 | [diff] [blame] | 17 | #ifdef CONFIG_SYS_ARM_MMU |
Jeroen Hofstee | d746077 | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 18 | __weak void arm_init_before_mmu(void) |
Aneesh V | 3e3bc1e | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 19 | { |
| 20 | } |
Aneesh V | 3e3bc1e | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 21 | |
R Sricharan | 06396c1 | 2013-03-04 20:04:45 +0000 | [diff] [blame] | 22 | __weak void arm_init_domains(void) |
| 23 | { |
| 24 | } |
| 25 | |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 26 | void set_section_dcache(int section, enum dcache_option option) |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 27 | { |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 28 | #ifdef CONFIG_ARMV7_LPAE |
| 29 | u64 *page_table = (u64 *)gd->arch.tlb_addr; |
| 30 | /* Need to set the access flag to not fault */ |
| 31 | u64 value = TTB_SECT_AP | TTB_SECT_AF; |
| 32 | #else |
Simon Glass | 6b4ee15 | 2012-12-13 20:48:39 +0000 | [diff] [blame] | 33 | u32 *page_table = (u32 *)gd->arch.tlb_addr; |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 34 | u32 value = TTB_SECT_AP; |
| 35 | #endif |
| 36 | |
| 37 | /* Add the page offset */ |
| 38 | value |= ((u32)section << MMU_SECTION_SHIFT); |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 39 | |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 40 | /* Add caching bits */ |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 41 | value |= option; |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 42 | |
| 43 | /* Set PTE */ |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 44 | page_table[section] = value; |
| 45 | } |
| 46 | |
Jeroen Hofstee | d746077 | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 47 | __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 48 | { |
| 49 | debug("%s: Warning: not implemented\n", __func__); |
| 50 | } |
| 51 | |
Thierry Reding | fe200715 | 2014-08-26 17:34:21 +0200 | [diff] [blame] | 52 | void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 53 | enum dcache_option option) |
| 54 | { |
Stefan Agner | c4a7322 | 2016-08-14 21:33:00 -0700 | [diff] [blame] | 55 | #ifdef CONFIG_ARMV7_LPAE |
| 56 | u64 *page_table = (u64 *)gd->arch.tlb_addr; |
| 57 | #else |
Simon Glass | 6b4ee15 | 2012-12-13 20:48:39 +0000 | [diff] [blame] | 58 | u32 *page_table = (u32 *)gd->arch.tlb_addr; |
Stefan Agner | c4a7322 | 2016-08-14 21:33:00 -0700 | [diff] [blame] | 59 | #endif |
Stefan Agner | bae1480 | 2016-08-14 21:33:01 -0700 | [diff] [blame] | 60 | unsigned long startpt, stoppt; |
Thierry Reding | fe200715 | 2014-08-26 17:34:21 +0200 | [diff] [blame] | 61 | unsigned long upto, end; |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 62 | |
| 63 | end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; |
| 64 | start = start >> MMU_SECTION_SHIFT; |
Keerthy | 266c8c1 | 2016-10-29 15:19:10 +0530 | [diff] [blame] | 65 | #ifdef CONFIG_ARMV7_LPAE |
| 66 | debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size, |
| 67 | option); |
| 68 | #else |
Keerthy | 485110a | 2016-10-29 15:19:09 +0530 | [diff] [blame] | 69 | debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 70 | option); |
Keerthy | 266c8c1 | 2016-10-29 15:19:10 +0530 | [diff] [blame] | 71 | #endif |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 72 | for (upto = start; upto < end; upto++) |
| 73 | set_section_dcache(upto, option); |
Stefan Agner | bae1480 | 2016-08-14 21:33:01 -0700 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * Make sure range is cache line aligned |
| 77 | * Only CPU maintains page tables, hence it is safe to always |
| 78 | * flush complete cache lines... |
| 79 | */ |
| 80 | |
| 81 | startpt = (unsigned long)&page_table[start]; |
| 82 | startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); |
| 83 | stoppt = (unsigned long)&page_table[end]; |
| 84 | stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); |
| 85 | mmu_page_table_flush(startpt, stoppt); |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 86 | } |
| 87 | |
R Sricharan | 0871607 | 2013-03-04 20:04:44 +0000 | [diff] [blame] | 88 | __weak void dram_bank_mmu_setup(int bank) |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 89 | { |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 90 | bd_t *bd = gd->bd; |
| 91 | int i; |
| 92 | |
| 93 | debug("%s: bank: %d\n", __func__, bank); |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 94 | for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; |
| 95 | i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + |
| 96 | (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 97 | i++) { |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 98 | #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
| 99 | set_section_dcache(i, DCACHE_WRITETHROUGH); |
Marek Vasut | 79b9072 | 2014-09-15 02:44:36 +0200 | [diff] [blame] | 100 | #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) |
| 101 | set_section_dcache(i, DCACHE_WRITEALLOC); |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 102 | #else |
| 103 | set_section_dcache(i, DCACHE_WRITEBACK); |
| 104 | #endif |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 105 | } |
| 106 | } |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 107 | |
| 108 | /* to activate the MMU we need to set up virtual memory: use 1M areas */ |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 109 | static inline void mmu_setup(void) |
| 110 | { |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 111 | int i; |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 112 | u32 reg; |
| 113 | |
Aneesh V | 3e3bc1e | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 114 | arm_init_before_mmu(); |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 115 | /* Set up an identity-mapping for all 4GB, rw for everyone */ |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 116 | for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++) |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 117 | set_section_dcache(i, DCACHE_OFF); |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 118 | |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 119 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 120 | dram_bank_mmu_setup(i); |
| 121 | } |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 122 | |
Simon Glass | 5bfd41d | 2017-05-31 17:57:13 -0600 | [diff] [blame] | 123 | #if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4 |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 124 | /* Set up 4 PTE entries pointing to our 4 1GB page tables */ |
| 125 | for (i = 0; i < 4; i++) { |
| 126 | u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4)); |
| 127 | u64 tpt = gd->arch.tlb_addr + (4096 * i); |
| 128 | page_table[i] = tpt | TTB_PAGETABLE; |
| 129 | } |
| 130 | |
| 131 | reg = TTBCR_EAE; |
| 132 | #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
| 133 | reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT; |
| 134 | #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) |
| 135 | reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA; |
| 136 | #else |
| 137 | reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; |
| 138 | #endif |
| 139 | |
| 140 | if (is_hyp()) { |
Simon Glass | 3b37247 | 2017-05-31 17:57:12 -0600 | [diff] [blame] | 141 | /* Set HTCR to enable LPAE */ |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 142 | asm volatile("mcr p15, 4, %0, c2, c0, 2" |
| 143 | : : "r" (reg) : "memory"); |
| 144 | /* Set HTTBR0 */ |
| 145 | asm volatile("mcrr p15, 4, %0, %1, c2" |
| 146 | : |
| 147 | : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0) |
| 148 | : "memory"); |
| 149 | /* Set HMAIR */ |
| 150 | asm volatile("mcr p15, 4, %0, c10, c2, 0" |
| 151 | : : "r" (MEMORY_ATTRIBUTES) : "memory"); |
| 152 | } else { |
| 153 | /* Set TTBCR to enable LPAE */ |
| 154 | asm volatile("mcr p15, 0, %0, c2, c0, 2" |
| 155 | : : "r" (reg) : "memory"); |
| 156 | /* Set 64-bit TTBR0 */ |
| 157 | asm volatile("mcrr p15, 0, %0, %1, c2" |
| 158 | : |
| 159 | : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0) |
| 160 | : "memory"); |
| 161 | /* Set MAIR */ |
| 162 | asm volatile("mcr p15, 0, %0, c10, c2, 0" |
| 163 | : : "r" (MEMORY_ATTRIBUTES) : "memory"); |
| 164 | } |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 165 | #elif defined(CONFIG_CPU_V7A) |
Simon Glass | 1375e58 | 2017-05-31 17:57:14 -0600 | [diff] [blame] | 166 | if (is_hyp()) { |
| 167 | /* Set HTCR to disable LPAE */ |
| 168 | asm volatile("mcr p15, 4, %0, c2, c0, 2" |
| 169 | : : "r" (0) : "memory"); |
| 170 | } else { |
| 171 | /* Set TTBCR to disable LPAE */ |
| 172 | asm volatile("mcr p15, 0, %0, c2, c0, 2" |
| 173 | : : "r" (0) : "memory"); |
| 174 | } |
Bryan Brinsko | 29d23ec | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 175 | /* Set TTBR0 */ |
| 176 | reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; |
| 177 | #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
| 178 | reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT; |
| 179 | #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) |
| 180 | reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA; |
| 181 | #else |
| 182 | reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB; |
| 183 | #endif |
| 184 | asm volatile("mcr p15, 0, %0, c2, c0, 0" |
| 185 | : : "r" (reg) : "memory"); |
| 186 | #else |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 187 | /* Copy the page table address to cp15 */ |
| 188 | asm volatile("mcr p15, 0, %0, c2, c0, 0" |
Simon Glass | 6b4ee15 | 2012-12-13 20:48:39 +0000 | [diff] [blame] | 189 | : : "r" (gd->arch.tlb_addr) : "memory"); |
Bryan Brinsko | 29d23ec | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 190 | #endif |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 191 | /* Set the access control to all-supervisor */ |
| 192 | asm volatile("mcr p15, 0, %0, c3, c0, 0" |
| 193 | : : "r" (~0)); |
R Sricharan | 06396c1 | 2013-03-04 20:04:45 +0000 | [diff] [blame] | 194 | |
| 195 | arm_init_domains(); |
| 196 | |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 197 | /* and enable the mmu */ |
| 198 | reg = get_cr(); /* get control reg. */ |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 199 | set_cr(reg | CR_M); |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 200 | } |
| 201 | |
Aneesh V | 3bda377 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 202 | static int mmu_enabled(void) |
| 203 | { |
| 204 | return get_cr() & CR_M; |
| 205 | } |
Lokesh Vutla | 19858f9 | 2018-04-26 18:21:31 +0530 | [diff] [blame] | 206 | #endif /* CONFIG_SYS_ARM_MMU */ |
Aneesh V | 3bda377 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 207 | |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 208 | /* cache_bit must be either CR_I or CR_C */ |
| 209 | static void cache_enable(uint32_t cache_bit) |
| 210 | { |
| 211 | uint32_t reg; |
| 212 | |
Lokesh Vutla | 19858f9 | 2018-04-26 18:21:31 +0530 | [diff] [blame] | 213 | /* The data cache is not active unless the mmu/mpu is enabled too */ |
| 214 | #ifdef CONFIG_SYS_ARM_MMU |
Aneesh V | 3bda377 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 215 | if ((cache_bit == CR_C) && !mmu_enabled()) |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 216 | mmu_setup(); |
Lokesh Vutla | 19858f9 | 2018-04-26 18:21:31 +0530 | [diff] [blame] | 217 | #elif defined(CONFIG_SYS_ARM_MPU) |
| 218 | if ((cache_bit == CR_C) && !mpu_enabled()) { |
| 219 | printf("Consider enabling MPU before enabling caches\n"); |
| 220 | return; |
| 221 | } |
| 222 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 223 | reg = get_cr(); /* get control reg. */ |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 224 | set_cr(reg | cache_bit); |
| 225 | } |
| 226 | |
| 227 | /* cache_bit must be either CR_I or CR_C */ |
| 228 | static void cache_disable(uint32_t cache_bit) |
| 229 | { |
| 230 | uint32_t reg; |
| 231 | |
SRICHARAN R | 88f4bf2 | 2012-05-16 23:52:54 +0000 | [diff] [blame] | 232 | reg = get_cr(); |
SRICHARAN R | 88f4bf2 | 2012-05-16 23:52:54 +0000 | [diff] [blame] | 233 | |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 234 | if (cache_bit == CR_C) { |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 235 | /* if cache isn;t enabled no need to disable */ |
Heiko Schocher | aeb2991 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 236 | if ((reg & CR_C) != CR_C) |
| 237 | return; |
Lokesh Vutla | 9ac1d17 | 2019-10-30 15:55:41 +0530 | [diff] [blame] | 238 | #ifdef CONFIG_SYS_ARM_MMU |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 239 | /* if disabling data cache, disable mmu too */ |
| 240 | cache_bit |= CR_M; |
Lokesh Vutla | 9ac1d17 | 2019-10-30 15:55:41 +0530 | [diff] [blame] | 241 | #endif |
Heiko Schocher | 69f1d0c | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 242 | } |
Arun Mankuzhi | 7a7825f | 2012-11-30 13:01:14 +0000 | [diff] [blame] | 243 | reg = get_cr(); |
Lothar Waßmann | bded0c8 | 2017-06-08 09:48:41 +0200 | [diff] [blame] | 244 | |
Lokesh Vutla | 9ac1d17 | 2019-10-30 15:55:41 +0530 | [diff] [blame] | 245 | #ifdef CONFIG_SYS_ARM_MMU |
Arun Mankuzhi | 7a7825f | 2012-11-30 13:01:14 +0000 | [diff] [blame] | 246 | if (cache_bit == (CR_C | CR_M)) |
Lokesh Vutla | 9ac1d17 | 2019-10-30 15:55:41 +0530 | [diff] [blame] | 247 | #elif defined(CONFIG_SYS_ARM_MPU) |
| 248 | if (cache_bit == CR_C) |
| 249 | #endif |
Arun Mankuzhi | 7a7825f | 2012-11-30 13:01:14 +0000 | [diff] [blame] | 250 | flush_dcache_all(); |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 251 | set_cr(reg & ~cache_bit); |
| 252 | } |
| 253 | #endif |
| 254 | |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 255 | #if CONFIG_IS_ENABLED(SYS_ICACHE_OFF) |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 256 | void icache_enable (void) |
| 257 | { |
| 258 | return; |
| 259 | } |
| 260 | |
| 261 | void icache_disable (void) |
| 262 | { |
| 263 | return; |
| 264 | } |
| 265 | |
| 266 | int icache_status (void) |
| 267 | { |
| 268 | return 0; /* always off */ |
| 269 | } |
| 270 | #else |
| 271 | void icache_enable(void) |
| 272 | { |
| 273 | cache_enable(CR_I); |
| 274 | } |
| 275 | |
| 276 | void icache_disable(void) |
| 277 | { |
| 278 | cache_disable(CR_I); |
| 279 | } |
| 280 | |
| 281 | int icache_status(void) |
| 282 | { |
| 283 | return (get_cr() & CR_I) != 0; |
| 284 | } |
| 285 | #endif |
| 286 | |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 287 | #if CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
Jean-Christophe PLAGNIOL-VILLARD | e6b5f1b | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 288 | void dcache_enable (void) |
| 289 | { |
| 290 | return; |
| 291 | } |
| 292 | |
| 293 | void dcache_disable (void) |
| 294 | { |
| 295 | return; |
| 296 | } |
| 297 | |
| 298 | int dcache_status (void) |
| 299 | { |
| 300 | return 0; /* always off */ |
| 301 | } |
| 302 | #else |
| 303 | void dcache_enable(void) |
| 304 | { |
| 305 | cache_enable(CR_C); |
| 306 | } |
| 307 | |
| 308 | void dcache_disable(void) |
| 309 | { |
| 310 | cache_disable(CR_C); |
| 311 | } |
| 312 | |
| 313 | int dcache_status(void) |
| 314 | { |
| 315 | return (get_cr() & CR_C) != 0; |
| 316 | } |
| 317 | #endif |