| commit | 29d23ec56dd038b776a626068b518bd5c2120748 | [log] [tgz] |
|---|---|---|
| author | Bryan Brinsko <bryan.brinsko@rockwellcollins.com> | Tue Mar 24 11:25:12 2015 -0500 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Thu Apr 16 14:59:33 2015 +0200 |
| tree | 3ae40c9ca7eceb5306544d318e38e6dad6dcedb2 | |
| parent | 689bfa236faf236d5a9f453edd16e794100935eb [diff] |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>