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git01.mediatek.com / filogic / uboot / e219c96bf7ad2bee4ce70f0b62d486723c92c2dd / . / include / configs / ti_omap3_common.h
blob: 0147662f443dd9719d2904e7d7ef2b222d3041ac [file] [log] [blame]
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]1/*
2 * ti_omap3_common.h
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * For more details, please see the technical documents listed at
9 * http://www.ti.com/product/omap3530
10 * http://www.ti.com/product/omap3630
11 * http://www.ti.com/product/dm3730
12 */
13
14#ifndef __CONFIG_TI_OMAP3_COMMON_H__
15#define __CONFIG_TI_OMAP3_COMMON_H__
16
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +0100[diff] [blame]17/*
18 * High Level Configuration Options
19 */
20
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]21#include <asm/arch/cpu.h>
Nishanth Menonfa96c962015-03-09 17:12:04 -0500[diff] [blame]22#include <asm/arch/omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]23
24/* The chip has SDRC controller */
25#define CONFIG_SDRC
26
27/* Clock Defines */
28#define V_OSCK 26000000 /* Clock output from T2 */
29#define V_SCLK (V_OSCK >> 1)
30
31/* NS16550 Configuration */
32#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
Thomas Chou52ac4432015-11-19 21:48:12 +0800[diff] [blame]33#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]34#ifdef CONFIG_SPL_BUILD
35# define CONFIG_SYS_NS16550_SERIAL
36# define CONFIG_SYS_NS16550_REG_SIZE (-4)
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]37#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]38#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
39 115200}
40
41/* Select serial console configuration */
42#define CONFIG_CONS_INDEX 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]43#ifdef CONFIG_SPL_BUILD
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]44#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
45#define CONFIG_SERIAL3 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]46#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]47
48/* Physical Memory Map */
49#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
50#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
51
52/*
53 * OMAP3 has 12 GP timers, they can be driven by the system clock
54 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
55 * This rate is divided by a local divisor.
56 */
57#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
58
59#define CONFIG_SYS_MONITOR_LEN (256 << 10)
60
61/* TWL4030 */
Igor Grinberg48b034a2015-10-08 21:12:25 +0300[diff] [blame]62#define CONFIG_TWL4030_POWER
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]63
64/* SPL */
65#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rini28eec372016-11-07 21:34:54 -0500[diff] [blame]66#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
Tom Rinid9f808d2014-04-03 07:52:53 -0400[diff] [blame]67#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
68 (64 << 20))
69
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]70#ifdef CONFIG_NAND
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]71#define CONFIG_SPL_NAND_SIMPLE
Tom Rinie10247f2014-04-03 15:17:15 -0400[diff] [blame]72#define CONFIG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]73#endif
74
75/* Now bring in the rest of the common code. */
Nishanth Menonad63dd72015-07-22 18:05:41 -0500[diff] [blame]76#include <configs/ti_armv7_omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]77
78#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */