| commit | bf9032ad2250283860f36a829a3dbd0fd8e63b2f | [log] [tgz] |
|---|---|---|
| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | Wed Jan 27 08:46:11 2016 +0100 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Sun Jan 31 16:32:56 2016 +0100 |
| tree | d89b5d8b6a58a9dc38d18e3415a06a9622932b6e | |
| parent | d6e436e5d2927c2b0f3151e4393697a6efe3e407 [diff] |
armv7: add cacheline sizes where missing Some armv7 targets are missing a cache line size declaration. In preparation for "arm: cache: Implement cache range check for v7" patch, add these declarations with the appropriate value for the target's SoC or CPU. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Tom Rini <trini@konsulko.com>