tree d89b5d8b6a58a9dc38d18e3415a06a9622932b6e
parent d6e436e5d2927c2b0f3151e4393697a6efe3e407
author Albert ARIBAUD <albert.u.boot@aribaud.net> 1453880771 +0100
committer Albert ARIBAUD <albert.u.boot@aribaud.net> 1454254376 +0100

armv7: add cacheline sizes where missing

Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Tom Rini <trini@konsulko.com>