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git01.mediatek.com / filogic / uboot / bc0f4ea6e21cf957c96176886d952b334944d205 / . / include / configs / ti_omap3_common.h
blob: 3c634ee680d02143b69fa0534143f28705b1a36b [file] [log] [blame]
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]1/*
2 * ti_omap3_common.h
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * For more details, please see the technical documents listed at
9 * http://www.ti.com/product/omap3530
10 * http://www.ti.com/product/omap3630
11 * http://www.ti.com/product/dm3730
12 */
13
14#ifndef __CONFIG_TI_OMAP3_COMMON_H__
15#define __CONFIG_TI_OMAP3_COMMON_H__
16
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]17
18#include <asm/arch/cpu.h>
19#include <asm/arch/omap3.h>
20
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame^]21#ifndef CONFIG_SPL_BUILD
22# define CONFIG_DM
23# define CONFIG_CMD_DM
24# define CONFIG_DM_GPIO
25# define CONFIG_DM_SERIAL
26# define CONFIG_OMAP_SERIAL
27# define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
28#endif
29
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]30/* The chip has SDRC controller */
31#define CONFIG_SDRC
32
33/* Clock Defines */
34#define V_OSCK 26000000 /* Clock output from T2 */
35#define V_SCLK (V_OSCK >> 1)
36
37/* NS16550 Configuration */
38#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
39#define CONFIG_SYS_NS16550
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame^]40#ifdef CONFIG_SPL_BUILD
41# define CONFIG_SYS_NS16550_SERIAL
42# define CONFIG_SYS_NS16550_REG_SIZE (-4)
43# define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
44#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]45#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
46 115200}
47
48/* Select serial console configuration */
49#define CONFIG_CONS_INDEX 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame^]50#ifdef CONFIG_SPL_BUILD
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]51#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
52#define CONFIG_SERIAL3 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame^]53#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]54
55/* Physical Memory Map */
56#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
57#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
58
59/*
60 * OMAP3 has 12 GP timers, they can be driven by the system clock
61 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
62 * This rate is divided by a local divisor.
63 */
64#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
65
66#define CONFIG_SYS_MONITOR_LEN (256 << 10)
67
68/* TWL4030 */
69#define CONFIG_TWL4030_POWER 1
70
71/* SPL */
72#define CONFIG_SPL_TEXT_BASE 0x40200800
73#define CONFIG_SPL_MAX_SIZE (54 * 1024)
74#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
75#define CONFIG_SPL_POWER_SUPPORT
Tom Rinid9f808d2014-04-03 07:52:53 -0400[diff] [blame]76#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
77 (64 << 20))
78
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]79
80#ifdef CONFIG_NAND
81#define CONFIG_SPL_NAND_SUPPORT
82#define CONFIG_SPL_NAND_SIMPLE
Tom Rinie10247f2014-04-03 15:17:15 -0400[diff] [blame]83#define CONFIG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]84#endif
85
86/* Now bring in the rest of the common code. */
87#include <configs/ti_armv7_common.h>
88
89#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */