Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / da1ad1169721546b1b2a2767267fa62472f025a7 / . / arch / m68k / cpu / mcf5445x / start.S
blob: 4c09489bcb73f4afb3303c7af9329a1f81bb06c1 [file] [log] [blame]
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]9 */
10
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]11#include <common.h>
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]12#include <asm-offsets.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]13#include <config.h>
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]14#include <timestamp.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]15#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]16#include <asm/cache.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]17
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]18#define _START _start
19#define _FAULT _fault
20
21#define SAVE_ALL \
22 move.w #0x2700,%sr; /* disable intrs */ \
23 subl #60,%sp; /* space for 15 regs */ \
24 moveml %d0-%d7/%a0-%a6,%sp@;
25
26#define RESTORE_ALL \
27 moveml %sp@,%d0-%d7/%a0-%a6; \
28 addl #60,%sp; /* space for 15 regs */ \
29 rte;
30
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]31#if defined(CONFIG_SERIAL_BOOT)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]32#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
33 CONFIG_SYS_INIT_RAM_ADDR)
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]34#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]35#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
36 CONFIG_SYS_INIT_RAM_ADDR)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]37#endif
38
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]39.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]40
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]41/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]42 * Vector table. This is used for initial platform startup.
43 * These vectors are to catch any un-intended traps.
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]44 */
45_vectors:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]46#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]47
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]48INITSP: .long 0 /* Initial SP */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]49#ifdef CONFIG_CF_SBF
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]50INITPC: .long ASM_DRAMINIT /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]51#endif
52#ifdef CONFIG_SYS_NAND_BOOT
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]53INITPC: .long ASM_DRAMINIT_N /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]54#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]55
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]56#else
57
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]58INITSP: .long 0 /* Initial SP */
59INITPC: .long _START /* Initial PC */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]60
61#endif
62
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]63vector02_0F:
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]66
67/* Reserved */
68vector10_17:
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]71vector18_1F:
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]73
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]74#if !defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]75
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]76/* TRAP #0 - #15 */
77vector20_2F:
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80
81/* Reserved */
82vector30_3F:
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85
86vector64_127:
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95
96vector128_191:
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105
106vector192_255:
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]115#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]116
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]117#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]118 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
119asm_sbf_img_hdr:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]120 .long 0x00000000 /* checksum, not yet implemented */
121 .long 0x00040000 /* image length */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]122 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]123
124asm_dram_init:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]125 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]126
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]127#ifdef CONFIG_SYS_NAND_BOOT
128 /* for assembly stack */
129 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
130 movec %d0, %RAMBAR1
131
132 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]133 clr.l %sp@-
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]134#endif
135
136#ifdef CONFIG_CF_SBF
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]137 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
138 movec %d0, %VBR
139
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]140 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]141 movec %d0, %RAMBAR1
142
143 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]144 move.l #0, %d0
145 move.l #(ICACHE_STATUS), %a1 /* icache */
146 move.l #(DCACHE_STATUS), %a2 /* dcache */
147 move.l %d0, (%a1)
148 move.l %d0, (%a2)
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]149
150 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]151 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]152 movec %d0, %CACR /* Invalidate cache */
153 move.l #0, %d0
154 movec %d0, %ACR0
155 movec %d0, %ACR1
156 movec %d0, %ACR2
157 movec %d0, %ACR3
158
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]159 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]160 clr.l %sp@-
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]161
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]162#ifdef CONFIG_SYS_CS0_BASE
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]163 /* Must disable global address */
164 move.l #0xFC008000, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]165 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]166 move.l #0xFC008008, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]167 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]168 move.l #0xFC008004, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]169 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]170#endif
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]171#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]172
173#ifdef CONFIG_MCF5441x
174 /* TC: enable all peripherals,
175 in the future only enable certain peripherals */
176 move.l #0xFC04002D, %a1
177
178#if defined(CONFIG_CF_SBF)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]179 move.b #23, (%a1) /* dspi */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]180#endif
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]181#endif /* CONFIG_MCF5441x */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]182
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]183 /* mandatory board level ddr-sdram init,
184 * for both 5441x and 5445x
185 */
186 bsr sbf_dram_init
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]187
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]188#ifdef CONFIG_CF_SBF
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]189 /*
190 * DSPI Initialization
191 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
192 * a1 - dspi status
193 * a2 - dtfr
194 * a3 - drfr
195 * a4 - Dst addr
196 */
197 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]198asm_dspi_init:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]199#ifdef CONFIG_MCF5441x
200 move.l #0xEC09404E, %a1
201 move.l #0xEC09404F, %a2
202 move.b #0xFF, (%a1)
203 move.b #0x80, (%a2)
204#endif
205
206#ifdef CONFIG_MCF5445x
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]207 move.l #0xFC0A4063, %a0
208 move.b #0x7F, (%a0)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]209#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]210 /* Configure DSPI module */
211 move.l #0xFC05C000, %a0
212 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
213
214 move.l #0xFC05C00C, %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]215#ifdef CONFIG_MCF5441x
216 move.l #0x3E000016, (%a0)
217#endif
218#ifdef CONFIG_MCF5445x
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]219 move.l #0x3E000011, (%a0)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]220#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]221
222 move.l #0xFC05C034, %a2 /* dtfr */
223 move.l #0xFC05C03B, %a3 /* drfr */
224
225 move.l #(ASM_SBF_IMG_HDR + 4), %a1
226 move.l (%a1)+, %d5
227 move.l (%a1), %a4
228
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]229 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
230 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]231
232 move.l #0xFC05C02C, %a1 /* dspi status */
233
234 /* Issue commands and address */
235 move.l #0x8002000B, %d2 /* Fast Read Cmd */
236 jsr asm_dspi_wr_status
237 jsr asm_dspi_rd_status
238
239 move.l #0x80020000, %d2 /* Address byte 2 */
240 jsr asm_dspi_wr_status
241 jsr asm_dspi_rd_status
242
243 move.l #0x80020000, %d2 /* Address byte 1 */
244 jsr asm_dspi_wr_status
245 jsr asm_dspi_rd_status
246
247 move.l #0x80020000, %d2 /* Address byte 0 */
248 jsr asm_dspi_wr_status
249 jsr asm_dspi_rd_status
250
251 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
252 jsr asm_dspi_wr_status
253 jsr asm_dspi_rd_status
254
255 /* Transfer serial boot header to sram */
256asm_dspi_rd_loop1:
257 move.l #0x80020000, %d2
258 jsr asm_dspi_wr_status
259 jsr asm_dspi_rd_status
260
261 move.b %d1, (%a0) /* read, copy to dst */
262
263 add.l #1, %a0 /* inc dst by 1 */
264 sub.l #1, %d4 /* dec cnt by 1 */
265 bne asm_dspi_rd_loop1
266
267 /* Transfer u-boot from serial flash to memory */
268asm_dspi_rd_loop2:
269 move.l #0x80020000, %d2
270 jsr asm_dspi_wr_status
271 jsr asm_dspi_rd_status
272
273 move.b %d1, (%a4) /* read, copy to dst */
274
275 add.l #1, %a4 /* inc dst by 1 */
276 sub.l #1, %d5 /* dec cnt by 1 */
277 bne asm_dspi_rd_loop2
278
279 move.l #0x00020000, %d2 /* Terminate */
280 jsr asm_dspi_wr_status
281 jsr asm_dspi_rd_status
282
283 /* jump to memory and execute */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]284 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]285 jmp (%a0)
286
287asm_dspi_wr_status:
288 move.l (%a1), %d0 /* status */
289 and.l #0x0000F000, %d0
290 cmp.l #0x00003000, %d0
291 bgt asm_dspi_wr_status
292
293 move.l %d2, (%a2)
294 rts
295
296asm_dspi_rd_status:
297 move.l (%a1), %d0 /* status */
298 and.l #0x000000F0, %d0
299 lsr.l #4, %d0
300 cmp.l #0, %d0
301 beq asm_dspi_rd_status
302
303 move.b (%a3), %d1
304 rts
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]305#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]306
307#ifdef CONFIG_SYS_NAND_BOOT
308 /* copy 4 boot pages to dram as soon as possible */
309 /* each page is 996 bytes (1056 total with 60 ECC bytes */
310 move.l #0x00000000, %a1 /* src */
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]311 move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]312 move.l #0x3E0, %d0 /* sz in long */
313
314asm_boot_nand_copy:
315 move.l (%a1)+, (%a2)+
316 subq.l #1, %d0
317 bne asm_boot_nand_copy
318
319 /* jump to memory and execute */
320 move.l #(asm_nand_init), %a0
321 jmp (%a0)
322
323asm_nand_init:
324 /* exit nand boot-mode */
325 move.l #0xFC0FFF30, %a1
326 or.l #0x00000040, %d1
327 move.l %d1, (%a1)
328
329 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]330 move.l #0, %d0
331 move.l #(CACR_STATUS), %a1 /* CACR */
332 move.l #(ICACHE_STATUS), %a2 /* icache */
333 move.l #(DCACHE_STATUS), %a3 /* dcache */
334 move.l %d0, (%a1)
335 move.l %d0, (%a2)
336 move.l %d0, (%a3)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]337
338 /* invalidate and disable cache */
339 move.l #0x01004100, %d0 /* Invalidate cache cmd */
340 movec %d0, %CACR /* Invalidate cache */
341 move.l #0, %d0
342 movec %d0, %ACR0
343 movec %d0, %ACR1
344 movec %d0, %ACR2
345 movec %d0, %ACR3
346
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]347#ifdef CONFIG_SYS_CS0_BASE
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]348 /* Must disable global address */
349 move.l #0xFC008000, %a1
350 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
351 move.l #0xFC008008, %a1
352 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
353 move.l #0xFC008004, %a1
354 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]355#endif
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]356
357 /* NAND port configuration */
358 move.l #0xEC094048, %a1
359 move.b #0xFD, (%a1)+
360 move.b #0x5F, (%a1)+
361 move.b #0x04, (%a1)+
362
363 /* reset nand */
364 move.l #0xFC0FFF38, %a1 /* isr */
365 move.l #0x000e0000, (%a1)
366 move.l #0xFC0FFF08, %a2
367 move.l #0x00000000, (%a2)+ /* car */
368 move.l #0x11000000, (%a2)+ /* rar */
369 move.l #0x00000000, (%a2)+ /* rpt */
370 move.l #0x00000000, (%a2)+ /* rai */
371 move.l #0xFC0FFF2c, %a2 /* cfg */
372 move.l #0x00000000, (%a2)+ /* secsz */
373 move.l #0x000e0681, (%a2)+
374 move.l #0xFC0FFF04, %a2 /* cmd2 */
375 move.l #0xFF404001, (%a2)
376 move.l #0x000e0000, (%a1)
377
378 move.l #0x2000, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]379 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]380
381 /* setup nand */
382 move.l #0xFC0FFF00, %a1
383 move.l #0x30700000, (%a1)+ /* cmd1 */
384 move.l #0x007EF000, (%a1)+ /* cmd2 */
385
386 move.l #0xFC0FFF2C, %a1
387 move.l #0x00000841, (%a1)+ /* secsz */
388 move.l #0x000e0681, (%a1)+ /* cfg */
389
390 move.l #100, %d4 /* 100 pages ~200KB */
391 move.l #4, %d2 /* start at 4 */
392 move.l #0xFC0FFF04, %a0 /* cmd2 */
393 move.l #0xFC0FFF0C, %a1 /* rar */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]394 move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]395
396asm_nand_read:
397 move.l #0x11000000, %d0 /* rar */
398 or.l %d2, %d0
399 move.l %d0, (%a1)
400 add.l #1, %d2
401
402 move.l (%a0), %d0 /* cmd2 */
403 or.l #1, %d0
404 move.l %d0, (%a0)
405
406 move.l #0x200, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]407 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]408
409asm_nand_chk_status:
410 move.l #0xFC0FFF38, %a4 /* isr */
411 move.l (%a4), %d0
412 and.l #0x40000000, %d0
413 tst.l %d0
414 beq asm_nand_chk_status
415
416 move.l #0xFC0FFF38, %a4 /* isr */
417 move.l (%a4), %d0
418 or.l #0x000E0000, %d0
419 move.l %d0, (%a4)
420
421 move.l #0x200, %d3
422 move.l #0xFC0FC000, %a3 /* buf 1 */
423asm_nand_copy:
424 move.l (%a3)+, (%a2)+
425 subq.l #1, %d3
426 bgt asm_nand_copy
427
428 subq.l #1, %d4
429 bgt asm_nand_read
430
431 /* jump to memory and execute */
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]432 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]433 jmp (%a0)
434
435#endif /* CONFIG_SYS_NAND_BOOT */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]436
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]437.globl asm_delay
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]438asm_delay:
439 nop
440 subq.l #1, %d1
441 bne asm_delay
442 rts
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]443#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]444
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]445.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]446 . = 0x400
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]447.globl _start
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]448_start:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]449#if !defined(CONFIG_SERIAL_BOOT)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]450 nop
451 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]452 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]453
454 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]455 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]456 movec %d0, %VBR
457
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]458 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew0573a7a2007-11-07 18:00:54 -0600[diff] [blame]459 movec %d0, %RAMBAR1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]460
461 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]462 move.l #0, %d0
463 move.l #(ICACHE_STATUS), %a1 /* icache */
464 move.l #(DCACHE_STATUS), %a2 /* dcache */
465 move.l %d0, (%a1)
466 move.l %d0, (%a2)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]467
468 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]469 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]470 movec %d0, %CACR /* Invalidate cache */
471 move.l #0, %d0
472 movec %d0, %ACR0
473 movec %d0, %ACR1
474 movec %d0, %ACR2
475 movec %d0, %ACR3
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]476#else
477 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
478 movec %d0, %RAMBAR1
479#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]480
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]481 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]482 move.l #__got_start, %a5
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]483
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]484 /* setup stack initially on top of internal static ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]485 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]486
487 /*
488 * if configured, malloc_f arena will be reserved first,
489 * then (and always) gd struct space will be reserved
490 */
491 move.l %sp, -(%sp)
492 move.l #board_init_f_alloc_reserve, %a1
493 jsr (%a1)
494
495 /* update stack and frame-pointers */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]496 move.l %d0, %sp
497 move.l %sp, %fp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]498
499 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]500 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]501 move.l #board_init_f_init_reserve, %a1
502 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]503
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]504 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]505 move.l #cpu_init_f, %a1
506 jsr (%a1)
507
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]508 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]509 clr.l %sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]510 move.l #board_init_f, %a1
511 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]512
513 /* board_init_f() does not return */
514
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]515/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]516
517/*
518 * void relocate_code (addr_sp, gd, addr_moni)
519 *
520 * This "function" does not return, instead it continues in RAM
521 * after relocating the monitor code.
522 *
523 * r3 = dest
524 * r4 = src
525 * r5 = length in bytes
526 * r6 = cachelinesize
527 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]528.globl relocate_code
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]529relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]530 link.w %a6,#0
531 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]532
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]533 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
534 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]535
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]536 move.l #CONFIG_SYS_MONITOR_BASE, %a1
537 move.l #__init_end, %a2
538 move.l %a0, %a3
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]539
540 /* copy the code to RAM */
5411:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]542 move.l (%a1)+, (%a3)+
543 cmp.l %a1,%a2
544 bgt.s 1b
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]545
546/*
547 * We are done. Do not return, instead branch to second part of board
548 * initialization, now running from RAM.
549 */
550 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]551 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]552 jmp (%a1)
553
554in_ram:
555
556clear_bss:
557 /*
558 * Now clear BSS segment
559 */
560 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]561 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]562 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]563 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]5646:
565 clr.l (%a1)+
566 cmp.l %a1,%d1
567 bgt.s 6b
568
569 /*
570 * fix got table in RAM
571 */
572 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]573 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]574 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]575
576 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]577 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]578
5797:
580 move.l (%a1),%d1
581 sub.l #_start,%d1
582 add.l %a0,%d1
583 move.l %d1,(%a1)+
584 cmp.l %a2, %a1
585 bne 7b
586
587 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]588 move.l %a0, %a1
589 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]590
591 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]592 move.l %a0,-(%sp) /* dest_addr */
593 move.l %d0,-(%sp) /* gd */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]594 jsr (%a1)
595
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]596/******************************************************************************/
597
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]598/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]599.globl _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]600_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]601 bra _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]602
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]603.globl _exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]604_exc_handler:
605 SAVE_ALL
606 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]607 bsr exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]608 addql #4,%sp
609 RESTORE_ALL
610
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]611.globl _int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]612_int_handler:
613 SAVE_ALL
614 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]615 bsr int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]616 addql #4,%sp
617 RESTORE_ALL
618
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]619/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]620
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]621.globl version_string
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]622version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]623.ascii U_BOOT_VERSION_STRING, "\0"
624.align 4