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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
David Feng3b5458c2013-12-14 11:47:37 +08002/*
3 * Configuration for Versatile Express. Parts were derived from other ARM
4 * configurations.
David Feng3b5458c2013-12-14 11:47:37 +08005 */
6
Peter Hoyes32860372021-11-11 09:26:00 +00007#ifndef __VEXPRESS_AEMV8_H
8#define __VEXPRESS_AEMV8_H
David Feng3b5458c2013-12-14 11:47:37 +08009
Peter Hoyes16fff302021-11-11 09:26:01 +000010#include <linux/stringify.h>
11
David Feng3b5458c2013-12-14 11:47:37 +080012/* Link Definitions */
Peter Hoyes32860372021-11-11 09:26:00 +000013#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Peter Hoyes32860372021-11-11 09:26:00 +000014#else
Darwin Rambod32d4112014-06-09 11:12:59 -070015/* ATF loads u-boot here for BASE_FVP model */
Darwin Rambod32d4112014-06-09 11:12:59 -070016#endif
David Feng3b5458c2013-12-14 11:47:37 +080017
David Feng3b5458c2013-12-14 11:47:37 +080018/* CS register bases for the original memory map. */
Peter Hoyes3ca0ea02022-03-04 16:30:18 +000019#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
20#define V2M_DRAM_BASE 0x00000000
21#define V2M_PA_BASE 0x80000000
22#else
Andre Przywara87de4b72022-03-04 16:30:16 +000023#define V2M_DRAM_BASE 0x80000000
Peter Hoyes32860372021-11-11 09:26:00 +000024#define V2M_PA_BASE 0x00000000
Peter Hoyes3ca0ea02022-03-04 16:30:18 +000025#endif
Peter Hoyes32860372021-11-11 09:26:00 +000026
27#define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000)
28#define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000)
29#define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000)
30#define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000)
31#define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000)
32#define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000)
David Feng3b5458c2013-12-14 11:47:37 +080033
34#define V2M_PERIPH_OFFSET(x) (x << 16)
35#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
36#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
37#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
38
David Feng3b5458c2013-12-14 11:47:37 +080039/* Common peripherals relative to CS7. */
40#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
41#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
42#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
43#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
44
Linus Walleijc5822502015-01-23 14:41:10 +010045#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
46#define V2M_UART0 0x7ff80000
47#define V2M_UART1 0x7ff70000
48#else /* Not Juno */
David Feng3b5458c2013-12-14 11:47:37 +080049#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
50#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
51#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
52#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
Linus Walleijc5822502015-01-23 14:41:10 +010053#endif
David Feng3b5458c2013-12-14 11:47:37 +080054
55#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
56
57#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
58#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
59
60#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
61#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
62
63#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
64
65#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
66
67/* System register offsets. */
68#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
69#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
70#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
71
David Feng3b5458c2013-12-14 11:47:37 +080072/* Generic Interrupt Controller Definitions */
David Feng79bbde02014-03-14 14:26:27 +080073#ifdef CONFIG_GICV3
Peter Hoyes32860372021-11-11 09:26:00 +000074#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
75#define GICR_BASE (V2M_PA_BASE + 0x2f100000)
David Feng79bbde02014-03-14 14:26:27 +080076#else
Darwin Rambod32d4112014-06-09 11:12:59 -070077
Peter Hoyes32860372021-11-11 09:26:00 +000078#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Linus Walleijc5822502015-01-23 14:41:10 +010079#define GICD_BASE (0x2C010000)
80#define GICC_BASE (0x2C02f000)
Peter Hoyes32860372021-11-11 09:26:00 +000081#else
82#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
83#define GICC_BASE (V2M_PA_BASE + 0x2c000000)
David Feng79bbde02014-03-14 14:26:27 +080084#endif
Linus Walleija90caa32015-03-23 11:06:14 +010085#endif /* !CONFIG_GICV3 */
David Feng3b5458c2013-12-14 11:47:37 +080086
Peter Hoyes8194cda2021-11-11 09:26:03 +000087#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH)
88/* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */
Bhupesh Sharmae997f352014-01-16 09:47:40 -060089#define CONFIG_SMC91111 1
Peter Hoyes32860372021-11-11 09:26:00 +000090#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
Linus Walleij48b47552015-02-17 11:35:25 +010091#endif
David Feng3b5458c2013-12-14 11:47:37 +080092
93/* PL011 Serial Configuration */
Linus Walleijc5822502015-01-23 14:41:10 +010094#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywarad3457182020-04-27 19:18:00 +010095#define CONFIG_PL011_CLOCK 7372800
Linus Walleijc5822502015-01-23 14:41:10 +010096#else
David Feng3b5458c2013-12-14 11:47:37 +080097#define CONFIG_PL011_CLOCK 24000000
Linus Walleijc5822502015-01-23 14:41:10 +010098#endif
David Feng3b5458c2013-12-14 11:47:37 +080099
David Feng3b5458c2013-12-14 11:47:37 +0800100/* Physical Memory Map */
Andre Przywara87de4b72022-03-04 16:30:16 +0000101#define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */
Linus Walleij0a38bfe2015-05-11 10:03:57 +0200102/* Top 16MB reserved for secure world use */
103#define DRAM_SEC_SIZE 0x01000000
104#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
105#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
106
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000107#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000108#define PHYS_SDRAM_2 (0x880000000)
109#define PHYS_SDRAM_2_SIZE 0x180000000
Peter Hoyes32860372021-11-11 09:26:00 +0000110#elif CONFIG_NR_DRAM_BANKS == 2
Diego Sueiro7a02a1b2021-02-15 07:27:57 +0000111#define PHYS_SDRAM_2 (0x880000000)
112#define PHYS_SDRAM_2_SIZE 0x80000000
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000113#endif
114
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000115/* Copy the kernel, initrd and FDT from NOR flash to DRAM memory and boot. */
Andre Przywarabe035312021-07-12 00:25:15 +0100116#define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
117 "bootcmd_afs=" \
118 "afs load ${kernel_name} ${kernel_addr_r} ;"\
119 "if test $? -eq 1; then "\
120 " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
121 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
122 "fi ; "\
123 "afs load ${fdtfile} ${fdt_addr_r} ;"\
124 "if test $? -eq 1; then "\
125 " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
126 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
127 "fi ; "\
128 "fdt addr ${fdt_addr_r}; fdt resize; " \
129 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
130 "then "\
131 " setenv ramdisk_param ${ramdisk_addr_r}; "\
132 "else "\
133 " setenv ramdisk_param -; "\
134 "fi ; " \
135 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
136#define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
137
Andre Przywara019753a2022-03-04 16:30:14 +0000138/* Boot by executing a U-Boot script pre-loaded into DRAM. */
139#define BOOTENV_DEV_MEM(devtypeu, devtypel, instance) \
140 "bootcmd_mem= " \
141 "source ${scriptaddr}; " \
142 "if test $? -eq 1; then " \
143 " env import -t ${scriptaddr}; " \
144 " if test -n $uenvcmd; then " \
145 " echo Running uenvcmd ...; " \
146 " run uenvcmd; " \
147 " fi; " \
148 "fi\0"
149#define BOOTENV_DEV_NAME_MEM(devtypeu, devtypel, instance) "mem "
150
151#ifdef CONFIG_CMD_VIRTIO
152#define FUNC_VIRTIO(func) func(VIRTIO, virtio, 0)
153#else
154#define FUNC_VIRTIO(func)
155#endif
156
157/*
158 * Boot by loading an Android image, or kernel, initrd and FDT through
159 * semihosting into DRAM.
160 */
161#define BOOTENV_DEV_SMH(devtypeu, devtypel, instance) \
162 "bootcmd_smh= " \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400163 "if load hostfs - ${boot_addr_r} ${boot_name}; then" \
Andre Przywara019753a2022-03-04 16:30:14 +0000164 " setenv bootargs;" \
165 " abootimg addr ${boot_addr_r};" \
166 " abootimg get dtb --index=0 fdt_addr_r;" \
167 " bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r};" \
168 "else" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400169 " if load hostfs - ${kernel_addr_r} ${kernel_name}; then" \
Andre Przywara019753a2022-03-04 16:30:14 +0000170 " setenv fdt_high 0xffffffffffffffff;" \
171 " setenv initrd_high 0xffffffffffffffff;" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400172 " load hostfs - ${fdt_addr_r} ${fdtfile};" \
173 " load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \
Andre Przywara019753a2022-03-04 16:30:14 +0000174 " fdt addr ${fdt_addr_r};" \
175 " fdt resize;" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400176 " fdt chosen ${ramdisk_addr_r} ${filesize};" \
Andre Przywara019753a2022-03-04 16:30:14 +0000177 " booti $kernel_addr_r - $fdt_addr_r;" \
178 " fi;" \
179 "fi\0"
180#define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh "
181
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000182/* Boot sources for distro boot and load addresses, per board */
183
184#ifdef CONFIG_TARGET_VEXPRESS64_JUNO /* Arm Juno board */
185
Andre Przywarabe035312021-07-12 00:25:15 +0100186#define BOOT_TARGET_DEVICES(func) \
187 func(USB, usb, 0) \
188 func(SATA, sata, 0) \
189 func(SATA, sata, 1) \
190 func(PXE, pxe, na) \
191 func(DHCP, dhcp, na) \
192 func(AFS, afs, na)
193
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000194#define VEXPRESS_KERNEL_ADDR 0x80080000
195#define VEXPRESS_PXEFILE_ADDR 0x8fb00000
196#define VEXPRESS_FDT_ADDR 0x8fc00000
197#define VEXPRESS_SCRIPT_ADDR 0x8fd00000
198#define VEXPRESS_RAMDISK_ADDR 0x8fe00000
Linus Walleijc39566a2015-04-05 01:48:32 +0200199
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000200#define EXTRA_ENV_NAMES \
201 "kernel_name=norkern\0" \
202 "kernel_alt_name=Image\0" \
203 "ramdisk_name=ramdisk.img\0" \
204 "fdtfile=board.dtb\0" \
205 "fdt_alt_name=juno\0"
Peter Hoyes16fff302021-11-11 09:26:01 +0000206
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000207#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ARMv8-A base model */
Peter Hoyes16fff302021-11-11 09:26:01 +0000208
Andre Przywara019753a2022-03-04 16:30:14 +0000209#define BOOT_TARGET_DEVICES(func) \
210 func(SMH, smh, na) \
211 func(MEM, mem, na) \
212 FUNC_VIRTIO(func) \
213 func(PXE, pxe, na) \
214 func(DHCP, dhcp, na)
215
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000216#define VEXPRESS_KERNEL_ADDR 0x80080000
217#define VEXPRESS_PXEFILE_ADDR 0x8fa00000
218#define VEXPRESS_SCRIPT_ADDR 0x8fb00000
219#define VEXPRESS_FDT_ADDR 0x8fc00000
220#define VEXPRESS_BOOT_ADDR 0x8fd00000
221#define VEXPRESS_RAMDISK_ADDR 0x8fe00000
222
223#define EXTRA_ENV_NAMES \
224 "kernel_name=Image\0" \
225 "ramdisk_name=ramdisk.img\0" \
226 "fdtfile=devtree.dtb\0" \
227 "boot_name=boot.img\0" \
228 "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0"
229
Peter Hoyes3ca0ea02022-03-04 16:30:18 +0000230#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP /* ARMv8-R base model */
231
232#define BOOT_TARGET_DEVICES(func) \
233 func(MEM, mem, na) \
234 FUNC_VIRTIO(func) \
235 func(PXE, pxe, na) \
236 func(DHCP, dhcp, na)
237
238#define VEXPRESS_KERNEL_ADDR 0x00200000
239#define VEXPRESS_PXEFILE_ADDR 0x0fb00000
240#define VEXPRESS_FDT_ADDR 0x0fc00000
241#define VEXPRESS_SCRIPT_ADDR 0x0fd00000
242#define VEXPRESS_RAMDISK_ADDR 0x0fe00000
243
244#define EXTRA_ENV_NAMES \
245 "kernel_name=Image\0" \
246 "ramdisk_name=ramdisk.img\0" \
247 "fdtfile=board.dtb\0"
Darwin Rambod32d4112014-06-09 11:12:59 -0700248#endif
David Feng3b5458c2013-12-14 11:47:37 +0800249
Andre Przywara019753a2022-03-04 16:30:14 +0000250#include <config_distro_bootcmd.h>
251
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000252/* Default load addresses and names for the different payloads. */
253#define CONFIG_EXTRA_ENV_SETTINGS \
254 "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \
255 "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \
256 "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \
257 "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \
258 "scriptaddr=" __stringify(VEXPRESS_SCRIPT_ADDR) "\0" \
259 EXTRA_ENV_NAMES \
260 BOOTENV
261
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000262#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
263#define CONFIG_SYS_FLASH_BASE 0x08000000
264/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
265#define CONFIG_SYS_MAX_FLASH_SECT 259
266/* Store environment at top of flash in the same location as blank.img */
267/* in the Juno firmware. */
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100268#else
Peter Hoyes32860372021-11-11 09:26:00 +0000269#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000270/* 256 x 256KiB sectors */
271#define CONFIG_SYS_MAX_FLASH_SECT 256
272/* Store environment at top of flash */
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000273#endif
274
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100275#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000276#define FLASH_MAX_SECTOR_SIZE 0x00040000
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100277
Peter Hoyes32860372021-11-11 09:26:00 +0000278#endif /* __VEXPRESS_AEMV8_H */