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git01.mediatek.com / filogic / uboot / d35b4c8f1973f13464589289410c3c7a8a7755bd / . / include / configs / ti_omap3_common.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]2/*
3 * ti_omap3_common.h
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 *
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]7 * For more details, please see the technical documents listed at
8 * http://www.ti.com/product/omap3530
9 * http://www.ti.com/product/omap3630
10 * http://www.ti.com/product/dm3730
11 */
12
13#ifndef __CONFIG_TI_OMAP3_COMMON_H__
14#define __CONFIG_TI_OMAP3_COMMON_H__
15
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +0100[diff] [blame]16/*
17 * High Level Configuration Options
18 */
19
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]20#include <asm/arch/cpu.h>
Nishanth Menonfa96c962015-03-09 17:12:04 -0500[diff] [blame]21#include <asm/arch/omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]22
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]23/* Clock Defines */
24#define V_OSCK 26000000 /* Clock output from T2 */
25#define V_SCLK (V_OSCK >> 1)
26
27/* NS16550 Configuration */
28#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
Tom Rinidf6a2152022-11-16 13:10:28 -0500[diff] [blame]29#define CFG_SYS_NS16550_CLK V_NS16550_CLK
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]30#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]31 115200}
32
33/* Select serial console configuration */
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]34#ifdef CONFIG_SPL_BUILD
Tom Rinidf6a2152022-11-16 13:10:28 -0500[diff] [blame]35#define CFG_SYS_NS16550_COM1 OMAP34XX_UART1
36#define CFG_SYS_NS16550_COM2 OMAP34XX_UART2
37#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]38#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]39
40/* Physical Memory Map */
41#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
42#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
43
44/*
45 * OMAP3 has 12 GP timers, they can be driven by the system clock
46 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
47 * This rate is divided by a local divisor.
48 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]49#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2)
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]50
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]51/* SPL */
Tom Rinid9f808d2014-04-03 07:52:53 -0400[diff] [blame]52
Miquel Raynald0935362019-10-03 19:50:03 +0200[diff] [blame]53#ifdef CONFIG_MTD_RAW_NAND
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]54#define CFG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]55#endif
56
57/* Now bring in the rest of the common code. */
Nishanth Menonad63dd72015-07-22 18:05:41 -0500[diff] [blame]58#include <configs/ti_armv7_omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]59
60#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */