Blame - arch/arm/mach-mvebu/Kconfig - filogic/uboot

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Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	1	if ARCH_MVEBU
				2
Mario Six	10d1449	2017-01-11 16:01:00 +0100	[diff] [blame]	3	config HAVE_MVEBU_EFUSE
				4	bool
Mario Six	10d1449	2017-01-11 16:01:00 +0100	[diff] [blame]	5
Stefan Roese	05b1765	2016-05-17 15:00:30 +0200	[diff] [blame]	6	config ARMADA_32BIT
				7	bool
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	8	select BOARD_EARLY_INIT_F
Lokesh Vutla	81b1a67	2018-04-26 18:21:26 +0530	[diff] [blame]	9	select CPU_V7A
Stefan Roese	1f1b3e9	2019-04-11 08:58:32 +0200	[diff] [blame]	10	select SPL_DM if SPL
				11	select SPL_DM_SEQ_ALIAS if SPL
				12	select SPL_OF_CONTROL if SPL
Tom Rini	b7cc2fe	2021-10-15 10:54:41 -0400	[diff] [blame]	13	select SPL_SKIP_LOWLEVEL_INIT if SPL
Stefan Roese	1f1b3e9	2019-04-11 08:58:32 +0200	[diff] [blame]	14	select SPL_SIMPLE_BUS if SPL
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	15	select SUPPORT_SPL
Philip Oberfichtner	5833e1b	2022-08-17 15:07:12 +0200	[diff] [blame]	16	select SYS_L2_PL310 if !SYS_L2CACHE_OFF
Stefan Roese	85bddff	2019-04-12 16:42:28 +0200	[diff] [blame]	17	select TRANSLATION_OFFSET
Alexander Dahl	3f3c838	2023-12-21 08:26:10 +0100	[diff] [blame]	18	select TOOLS_KWBIMAGE if SPL
Pali Rohár	c5c28df	2022-04-06 16:20:20 +0200	[diff] [blame]	19	select SPL_SYS_NO_VECTOR_TABLE if SPL
Pali Rohár	aaed328	2022-05-06 11:05:14 +0200	[diff] [blame]	20	select ARCH_VERY_EARLY_INIT
Marek Behún	32a932a	2024-04-04 09:50:59 +0200	[diff] [blame]	21	select ARMADA_32BIT_SYSCON_RESET if DM_RESET && PCI_MVEBU
Marek Behún	514628c	2024-04-04 09:51:00 +0200	[diff] [blame]	22	select ARMADA_32BIT_SYSCON_SYSRESET if SYSRESET
Stefan Roese	05b1765	2016-05-17 15:00:30 +0200	[diff] [blame]	23
Stefan Roese	05b1765	2016-05-17 15:00:30 +0200	[diff] [blame]	24	# ARMv7 SoCs...
Stefan Roese	9106ed0	2016-01-29 09:14:54 +0100	[diff] [blame]	25	config ARMADA_375
				26	bool
Stefan Roese	05b1765	2016-05-17 15:00:30 +0200	[diff] [blame]	27	select ARMADA_32BIT
Stefan Roese	9106ed0	2016-01-29 09:14:54 +0100	[diff] [blame]	28
Stefan Roese	eb083e5	2015-12-21 13:56:33 +0100	[diff] [blame]	29	config ARMADA_38X
				30	bool
Stefan Roese	05b1765	2016-05-17 15:00:30 +0200	[diff] [blame]	31	select ARMADA_32BIT
Mario Six	10d1449	2017-01-11 16:01:00 +0100	[diff] [blame]	32	select HAVE_MVEBU_EFUSE
Stefan Roese	eb083e5	2015-12-21 13:56:33 +0100	[diff] [blame]	33
Joshua Scott	4ba8e99	2020-11-09 10:14:08 +1300	[diff] [blame]	34	config ARMADA_38X_HS_IMPEDANCE_THRESH
				35	hex "Armada 38x USB 2.0 High-Speed Impedance Threshold (0x0 - 0x7)"
				36	depends on ARMADA_38X
				37	default 0x6
				38	range 0x0 0x7
				39
Marek Behún	e4a2cca	2024-06-18 17:34:38 +0200	[diff] [blame]	40	config ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
				41	bool
				42	depends on ARMADA_38X
				43
Stefan Roese	eb083e5	2015-12-21 13:56:33 +0100	[diff] [blame]	44	config ARMADA_XP
				45	bool
Stefan Roese	05b1765	2016-05-17 15:00:30 +0200	[diff] [blame]	46	select ARMADA_32BIT
				47
				48	# ARMv8 SoCs...
				49	config ARMADA_3700
				50	bool
				51	select ARM64
Pali Rohár	70d9bee	2022-02-23 14:15:45 +0100	[diff] [blame]	52	select HAVE_MVEBU_EFUSE
Stefan Roese	eb083e5	2015-12-21 13:56:33 +0100	[diff] [blame]	53
Stefan Roese	cb41033	2016-05-25 08:13:45 +0200	[diff] [blame]	54	# Armada 7K and 8K are very similar - use only one Kconfig symbol for both
				55	config ARMADA_8K
				56	bool
				57	select ARM64
				58
Chris Packham	eaab461	2022-11-05 17:23:59 +1300	[diff] [blame]	59	config ALLEYCAT_5
				60	bool
				61	select ARM64
				62
Chris Packham	1d49668	2016-10-26 14:08:30 +1300	[diff] [blame]	63	# Armada PLL frequency (used for NAND clock generation)
				64	config SYS_MVEBU_PLL_CLOCK
				65	int
Chris Packham	a8f845e	2019-04-11 22:22:50 +1200	[diff] [blame]	66	default "2000000000" if ARMADA_XP \|\| ARMADA_3700 \|\| ARMADA_8K \|\| ARMADA_MSYS
Chris Packham	1d49668	2016-10-26 14:08:30 +1300	[diff] [blame]	67	default "1000000000" if ARMADA_38X \|\| ARMADA_375
				68
Stefan Roese	05b1765	2016-05-17 15:00:30 +0200	[diff] [blame]	69	# Armada XP/38x SoC types...
Phil Sutter	a7f94ad	2015-12-25 14:41:22 +0100	[diff] [blame]	70	config MV78230
				71	bool
				72	select ARMADA_XP
				73
				74	config MV78260
				75	bool
				76	select ARMADA_XP
Simon Glass	203b3ab	2017-06-14 21:28:24 -0600	[diff] [blame]	77	imply CMD_SATA
Phil Sutter	a7f94ad	2015-12-25 14:41:22 +0100	[diff] [blame]	78
				79	config MV78460
				80	bool
				81	select ARMADA_XP
				82
Chris Packham	a8f845e	2019-04-11 22:22:50 +1200	[diff] [blame]	83	config ARMADA_MSYS
				84	bool
				85	select ARMADA_32BIT
				86
				87	config 98DX4251
				88	bool
				89	select ARMADA_MSYS
				90
				91	config 98DX3336
				92	bool
				93	select ARMADA_MSYS
				94
				95	config 98DX3236
				96	bool
				97	select ARMADA_MSYS
				98
Chris Packham	f5fc25b	2016-09-22 12:56:13 +1200	[diff] [blame]	99	config 88F6820
Phil Sutter	a7f94ad	2015-12-25 14:41:22 +0100	[diff] [blame]	100	bool
				101	select ARMADA_38X
				102
Tom Rini	40a325f	2022-03-30 18:07:24 -0400	[diff] [blame]	103	config CUSTOMER_BOARD_SUPPORT
				104	bool
				105
Tony Dinh	63eba13	2023-02-01 15:13:05 -0800	[diff] [blame]	106	config DDR4
				107	bool "Support Marvell DDR4 Training driver"
				108
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	109	choice
Chris Packham	67b7d50	2022-11-05 17:24:00 +1300	[diff] [blame]	110	prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	111	optional
				112
Stefan Roese	7360640	2015-10-20 15:14:47 +0200	[diff] [blame]	113	config TARGET_CLEARFOG
				114	bool "Support ClearFog"
Chris Packham	f5fc25b	2016-09-22 12:56:13 +1200	[diff] [blame]	115	select 88F6820
Baruch Siach	1c5e95d	2020-01-20 14:20:13 +0200	[diff] [blame]	116	select BOARD_LATE_INIT
Martin Rowe	7eceb67	2023-03-27 21:24:09 +1000	[diff] [blame]	117	select OF_BOARD_SETUP
Stefan Roese	7360640	2015-10-20 15:14:47 +0200	[diff] [blame]	118
Dennis Gilmore	77c3940	2018-06-11 19:39:53 -0500	[diff] [blame]	119	config TARGET_HELIOS4
				120	bool "Support Helios4"
				121	select 88F6820
				122
Konstantin Porotchkin	7f8dfea	2017-02-16 13:52:22 +0200	[diff] [blame]	123	config TARGET_MVEBU_ARMADA_37XX
				124	bool "Support Armada 37xx platforms"
Stefan Roese	6edf27e	2016-05-17 15:04:16 +0200	[diff] [blame]	125	select ARMADA_3700
Simon Glass	0e5faf0	2017-06-14 21:28:21 -0600	[diff] [blame]	126	imply SCSI
Stefan Roese	6edf27e	2016-05-17 15:04:16 +0200	[diff] [blame]	127
Stefan Roese	9106ed0	2016-01-29 09:14:54 +0100	[diff] [blame]	128	config TARGET_DB_88F6720
				129	bool "Support DB-88F6720 Armada 375"
				130	select ARMADA_375
				131
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	132	config TARGET_DB_88F6820_GP
				133	bool "Support DB-88F6820-GP"
Chris Packham	f5fc25b	2016-09-22 12:56:13 +1200	[diff] [blame]	134	select 88F6820
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	135
Chris Packham	a90dd4c	2016-09-22 12:56:14 +1200	[diff] [blame]	136	config TARGET_DB_88F6820_AMC
				137	bool "Support DB-88F6820-AMC"
				138	select 88F6820
				139
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	140	config TARGET_TURRIS_OMNIA
				141	bool "Support Turris Omnia"
				142	select 88F6820
Marek Behún	0f2e66a	2019-05-02 16:53:37 +0200	[diff] [blame]	143	select BOARD_LATE_INIT
Marek Behún	1e4cbb9	2019-05-02 16:53:28 +0200	[diff] [blame]	144	select DM_I2C
				145	select I2C_MUX
				146	select I2C_MUX_PCA954x
Marek Behún	4c3abea	2021-10-09 19:33:46 +0200	[diff] [blame]	147	select SPL_DRIVERS_MISC
Marek Behún	1e4cbb9	2019-05-02 16:53:28 +0200	[diff] [blame]	148	select SPL_I2C_MUX
Marek Behún	ca6095b	2021-10-09 19:33:45 +0200	[diff] [blame]	149	select SPL_SYS_MALLOC_SIMPLE
Marek Behún	1e4cbb9	2019-05-02 16:53:28 +0200	[diff] [blame]	150	select SYS_I2C_MVTWSI
Marek Behún	5e92efe	2019-05-02 16:53:32 +0200	[diff] [blame]	151	select ATSHA204A
Marek Behún	d1e6844	2024-06-18 17:34:39 +0200	[diff] [blame^]	152	select ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	153
Marek Behún	f835bed	2018-04-24 17:21:31 +0200	[diff] [blame]	154	config TARGET_TURRIS_MOX
Marek Behún	1b01011	2023-10-20 16:29:16 +0200	[diff] [blame]	155	bool "Support CZ.NIC's Turris Mox / RIPE Atlas Probe"
Marek Behún	f835bed	2018-04-24 17:21:31 +0200	[diff] [blame]	156	select ARMADA_3700
Marek Behún	1b01011	2023-10-20 16:29:16 +0200	[diff] [blame]	157	select BOARD_TYPES
				158	select ENV_IS_IN_MMC
				159	select ENV_IS_IN_SPI_FLASH
				160	select MULTI_DTB_FIT
Marek Behún	f835bed	2018-04-24 17:21:31 +0200	[diff] [blame]	161
Stefan Roese	5c806f1	2016-10-25 10:56:19 +0200	[diff] [blame]	162	config TARGET_MVEBU_ARMADA_8K
				163	bool "Support Armada 7k/8k platforms"
Stefan Roese	7be1b9b	2016-05-25 08:21:21 +0200	[diff] [blame]	164	select ARMADA_8K
Tom Rini	22d567e	2017-01-22 19:43:11 -0500	[diff] [blame]	165	select BOARD_LATE_INIT
Simon Glass	0e5faf0	2017-06-14 21:28:21 -0600	[diff] [blame]	166	imply SCSI
Stefan Roese	7be1b9b	2016-05-25 08:21:21 +0200	[diff] [blame]	167
Chris Packham	67b7d50	2022-11-05 17:24:00 +1300	[diff] [blame]	168	config TARGET_MVEBU_ALLEYCAT5
				169	bool "Support AlleyCat 5 platforms"
				170	select ALLEYCAT_5
				171
Konstantin Porotchkin	1d6ff1f	2021-03-16 17:20:57 +0100	[diff] [blame]	172	config TARGET_OCTEONTX2_CN913x
				173	bool "Support CN913x platforms"
				174	select ARMADA_8K
				175	imply BOARD_EARLY_INIT_R
				176	select BOARD_LATE_INIT
				177	imply SCSI
				178
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	179	config TARGET_DB_MV784MP_GP
				180	bool "Support db-mv784mp-gp"
Tom Rini	9a04d7d	2022-02-25 11:19:46 -0500	[diff] [blame]	181	select BOARD_ECC_SUPPORT
Phil Sutter	a7f94ad	2015-12-25 14:41:22 +0100	[diff] [blame]	182	select MV78460
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	183
Tony Dinh	6aebc1a	2023-02-09 14:00:03 -0800	[diff] [blame]	184	config TARGET_DS116
				185	bool "Support Synology DS116"
				186	select 88F6820
				187
Phil Sutter	d76eba6	2015-12-25 14:41:25 +0100	[diff] [blame]	188	config TARGET_DS414
				189	bool "Support Synology DS414"
				190	select MV78230
				191
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	192	config TARGET_MAXBCM
				193	bool "Support maxbcm"
Tom Rini	9a04d7d	2022-02-25 11:19:46 -0500	[diff] [blame]	194	select BOARD_ECC_SUPPORT
Phil Sutter	a7f94ad	2015-12-25 14:41:22 +0100	[diff] [blame]	195	select MV78460
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	196
Tony Dinh	63eba13	2023-02-01 15:13:05 -0800	[diff] [blame]	197	config TARGET_N2350
				198	bool "Support Thecus N2350"
				199	select 88F6820
				200	select DDR4
				201
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	202	config TARGET_THEADORABLE
				203	bool "Support theadorable Armada XP"
Tom Rini	22d567e	2017-01-22 19:43:11 -0500	[diff] [blame]	204	select BOARD_LATE_INIT if USB
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	205	select MV78260
Simon Glass	203b3ab	2017-06-14 21:28:24 -0600	[diff] [blame]	206	imply CMD_SATA
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	207
Dirk Eibach	fb60594	2017-02-22 16:07:23 +0100	[diff] [blame]	208	config TARGET_CONTROLCENTERDC
				209	bool "Support CONTROLCENTERDC"
				210	select 88F6820
Tom Rini	40a325f	2022-03-30 18:07:24 -0400	[diff] [blame]	211	select CUSTOMER_BOARD_SUPPORT
Dirk Eibach	fb60594	2017-02-22 16:07:23 +0100	[diff] [blame]	212
Chris Packham	b55b2c9	2019-01-10 21:01:00 +1300	[diff] [blame]	213	config TARGET_X530
				214	bool "Support Allied Telesis x530"
				215	select 88F6820
				216
Chris Packham	7325f1f	2023-07-10 10:47:36 +1200	[diff] [blame]	217	config TARGET_X240
				218	bool "Support Allied Telesis x240"
				219	select ALLEYCAT_5
				220
Chris Packham	199e318	2019-04-11 22:22:53 +1200	[diff] [blame]	221	config TARGET_DB_XC3_24G4XG
				222	bool "Support DB-XC3-24G4XG"
				223	select 98DX3336
				224
Luka Kovacic	25acb8b	2020-05-26 20:17:50 +0200	[diff] [blame]	225	config TARGET_CRS3XX_98DX3236
				226	bool "Support CRS3XX-98DX3236"
Luka Kovacic	b686e22	2019-05-07 19:35:55 +0200	[diff] [blame]	227	select 98DX3236
				228
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	229	endchoice
				230
Tom Rini	5918039	2021-08-21 13:50:13 -0400	[diff] [blame]	231	choice
				232	prompt "DDR bus width"
				233	default DDR_64BIT
				234	depends on ARMADA_XP
				235
				236	config DDR_64BIT
				237	bool "64bit bus width"
				238
				239	config DDR_32BIT
				240	bool "32bit bus width"
				241
				242	endchoice
				243
Tom Rini	592bcd0	2021-08-21 13:50:15 -0400	[diff] [blame]	244	config DDR_LOG_LEVEL
				245	int "DDR training code log level"
				246	depends on ARMADA_XP
				247	default 0
				248	range 0 3
				249	help
				250	Amount of information provided on error while running the DDR
				251	training code. At level 0, provides an error code in a case of
				252	failure, RL, WL errors and other algorithm failure. At level 1,
				253	provides the D-Unit setup (SPD/Static configuration). At level 2,
				254	provides the windows margin as a results of DQS centeralization.
				255	At level 3, rovides the windows margin of each DQ as a results of
				256	DQS centeralization.
				257
Marek Behún	e8bd758	2024-06-18 17:34:28 +0200	[diff] [blame]	258	config DDR_IMMUTABLE_DEBUG_SETTINGS
				259	bool "Immutable DDR debug level (always DEBUG_LEVEL_ERROR)"
				260	depends on ARMADA_38X
				261	help
				262	Makes the DDR training code debug level settings immutable.
				263	The debug level setting from board topology definition is ignored.
				264	The debug level is always set to DEBUG_LEVEL_ERROR and register
				265	dumps are disabled.
				266	This can save around 10 KiB of space in SPL binary.
				267
Marek Behún	90555af	2022-02-17 13:54:42 +0100	[diff] [blame]	268	config DDR_RESET_ON_TRAINING_FAILURE
				269	bool "Reset the board on DDR training failure instead of hanging"
				270	depends on ARMADA_38X \|\| ARMADA_XP
				271	help
				272	If DDR training fails in SPL, reset the board instead of hanging.
				273	Some boards are known to fail DDR training occasionally and an
				274	immediate reset may be preferable to waiting until the board is
				275	reset by watchdog (if there even is one).
				276
				277	Note that if booting via UART and the DDR training fails, the
				278	device will still hang - it doesn't make sense to reset the board
				279	in such a case.
				280
Tom Rini	9a04d7d	2022-02-25 11:19:46 -0500	[diff] [blame]	281	config BOARD_ECC_SUPPORT
				282	bool
				283
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	284	config SYS_BOARD
				285	default "clearfog" if TARGET_CLEARFOG
Dennis Gilmore	77c3940	2018-06-11 19:39:53 -0500	[diff] [blame]	286	default "helios4" if TARGET_HELIOS4
Konstantin Porotchkin	7f8dfea	2017-02-16 13:52:22 +0200	[diff] [blame]	287	default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX
Stefan Roese	9106ed0	2016-01-29 09:14:54 +0100	[diff] [blame]	288	default "db-88f6720" if TARGET_DB_88F6720
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	289	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
Chris Packham	a90dd4c	2016-09-22 12:56:14 +1200	[diff] [blame]	290	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	291	default "turris_omnia" if TARGET_TURRIS_OMNIA
Marek Behún	f835bed	2018-04-24 17:21:31 +0200	[diff] [blame]	292	default "turris_mox" if TARGET_TURRIS_MOX
Stefan Roese	5c806f1	2016-10-25 10:56:19 +0200	[diff] [blame]	293	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
Konstantin Porotchkin	1d6ff1f	2021-03-16 17:20:57 +0100	[diff] [blame]	294	default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	295	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
Tony Dinh	6aebc1a	2023-02-09 14:00:03 -0800	[diff] [blame]	296	default "ds116" if TARGET_DS116
Phil Sutter	d76eba6	2015-12-25 14:41:25 +0100	[diff] [blame]	297	default "ds414" if TARGET_DS414
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	298	default "maxbcm" if TARGET_MAXBCM
Tony Dinh	63eba13	2023-02-01 15:13:05 -0800	[diff] [blame]	299	default "n2350" if TARGET_N2350
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	300	default "theadorable" if TARGET_THEADORABLE
Baruch Siach	daa6f08	2018-06-18 21:56:23 +0300	[diff] [blame]	301	default "a38x" if TARGET_CONTROLCENTERDC
Chris Packham	b55b2c9	2019-01-10 21:01:00 +1300	[diff] [blame]	302	default "x530" if TARGET_X530
Chris Packham	7325f1f	2023-07-10 10:47:36 +1200	[diff] [blame]	303	default "x240" if TARGET_X240
Chris Packham	199e318	2019-04-11 22:22:53 +1200	[diff] [blame]	304	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
Luka Kovacic	25acb8b	2020-05-26 20:17:50 +0200	[diff] [blame]	305	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
Chris Packham	67b7d50	2022-11-05 17:24:00 +1300	[diff] [blame]	306	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	307
				308	config SYS_CONFIG_NAME
				309	default "clearfog" if TARGET_CLEARFOG
Dennis Gilmore	77c3940	2018-06-11 19:39:53 -0500	[diff] [blame]	310	default "helios4" if TARGET_HELIOS4
Konstantin Porotchkin	7f8dfea	2017-02-16 13:52:22 +0200	[diff] [blame]	311	default "mvebu_armada-37xx" if TARGET_MVEBU_ARMADA_37XX
Stefan Roese	9106ed0	2016-01-29 09:14:54 +0100	[diff] [blame]	312	default "db-88f6720" if TARGET_DB_88F6720
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	313	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
Chris Packham	a90dd4c	2016-09-22 12:56:14 +1200	[diff] [blame]	314	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
Stefan Roese	5c806f1	2016-10-25 10:56:19 +0200	[diff] [blame]	315	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
Konstantin Porotchkin	1d6ff1f	2021-03-16 17:20:57 +0100	[diff] [blame]	316	default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	317	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
Tony Dinh	6aebc1a	2023-02-09 14:00:03 -0800	[diff] [blame]	318	default "ds116" if TARGET_DS116
Phil Sutter	d76eba6	2015-12-25 14:41:25 +0100	[diff] [blame]	319	default "ds414" if TARGET_DS414
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	320	default "maxbcm" if TARGET_MAXBCM
Tony Dinh	63eba13	2023-02-01 15:13:05 -0800	[diff] [blame]	321	default "n2350" if TARGET_N2350
Stefan Roese	459e064	2016-01-20 08:13:29 +0100	[diff] [blame]	322	default "theadorable" if TARGET_THEADORABLE
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	323	default "turris_omnia" if TARGET_TURRIS_OMNIA
Marek Behún	f835bed	2018-04-24 17:21:31 +0200	[diff] [blame]	324	default "turris_mox" if TARGET_TURRIS_MOX
Baruch Siach	daa6f08	2018-06-18 21:56:23 +0300	[diff] [blame]	325	default "controlcenterdc" if TARGET_CONTROLCENTERDC
Chris Packham	b55b2c9	2019-01-10 21:01:00 +1300	[diff] [blame]	326	default "x530" if TARGET_X530
Chris Packham	7325f1f	2023-07-10 10:47:36 +1200	[diff] [blame]	327	default "x240" if TARGET_X240
Chris Packham	199e318	2019-04-11 22:22:53 +1200	[diff] [blame]	328	default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
Luka Kovacic	25acb8b	2020-05-26 20:17:50 +0200	[diff] [blame]	329	default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
Chris Packham	67b7d50	2022-11-05 17:24:00 +1300	[diff] [blame]	330	default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	331
				332	config SYS_VENDOR
				333	default "Marvell" if TARGET_DB_MV784MP_GP
Konstantin Porotchkin	7f8dfea	2017-02-16 13:52:22 +0200	[diff] [blame]	334	default "Marvell" if TARGET_MVEBU_ARMADA_37XX
Stefan Roese	9106ed0	2016-01-29 09:14:54 +0100	[diff] [blame]	335	default "Marvell" if TARGET_DB_88F6720
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	336	default "Marvell" if TARGET_DB_88F6820_GP
Chris Packham	a90dd4c	2016-09-22 12:56:14 +1200	[diff] [blame]	337	default "Marvell" if TARGET_DB_88F6820_AMC
Stefan Roese	5c806f1	2016-10-25 10:56:19 +0200	[diff] [blame]	338	default "Marvell" if TARGET_MVEBU_ARMADA_8K
Konstantin Porotchkin	1d6ff1f	2021-03-16 17:20:57 +0100	[diff] [blame]	339	default "Marvell" if TARGET_OCTEONTX2_CN913x
Chris Packham	199e318	2019-04-11 22:22:53 +1200	[diff] [blame]	340	default "Marvell" if TARGET_DB_XC3_24G4XG
				341	default "Marvell" if TARGET_MVEBU_DB_88F7040
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	342	default "solidrun" if TARGET_CLEARFOG
Dennis Gilmore	77c3940	2018-06-11 19:39:53 -0500	[diff] [blame]	343	default "kobol" if TARGET_HELIOS4
Tony Dinh	6aebc1a	2023-02-09 14:00:03 -0800	[diff] [blame]	344	default "Synology" if TARGET_DS116
Phil Sutter	d76eba6	2015-12-25 14:41:25 +0100	[diff] [blame]	345	default "Synology" if TARGET_DS414
Tony Dinh	63eba13	2023-02-01 15:13:05 -0800	[diff] [blame]	346	default "thecus" if TARGET_N2350
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	347	default "CZ.NIC" if TARGET_TURRIS_OMNIA
Marek Behún	f835bed	2018-04-24 17:21:31 +0200	[diff] [blame]	348	default "CZ.NIC" if TARGET_TURRIS_MOX
Baruch Siach	daa6f08	2018-06-18 21:56:23 +0300	[diff] [blame]	349	default "gdsys" if TARGET_CONTROLCENTERDC
Chris Packham	b55b2c9	2019-01-10 21:01:00 +1300	[diff] [blame]	350	default "alliedtelesis" if TARGET_X530
Chris Packham	7325f1f	2023-07-10 10:47:36 +1200	[diff] [blame]	351	default "alliedtelesis" if TARGET_X240
Luka Kovacic	25acb8b	2020-05-26 20:17:50 +0200	[diff] [blame]	352	default "mikrotik" if TARGET_CRS3XX_98DX3236
Chris Packham	67b7d50	2022-11-05 17:24:00 +1300	[diff] [blame]	353	default "Marvell" if TARGET_MVEBU_ALLEYCAT5
Stefan Roese	b9f41bf	2015-12-21 13:40:37 +0100	[diff] [blame]	354
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	355	config SYS_SOC
				356	default "mvebu"
				357
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	358	choice
Baruch Siach	8d196a4	2018-06-18 21:56:24 +0300	[diff] [blame]	359	prompt "Boot method"
Joel Johnson	a2018ab	2020-04-17 01:19:05 -0600	[diff] [blame]	360	depends on SPL
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	361
Baruch Siach	8d196a4	2018-06-18 21:56:24 +0300	[diff] [blame]	362	config MVEBU_SPL_BOOT_DEVICE_SPI
Pali Rohár	8d11032	2023-01-10 23:13:01 +0100	[diff] [blame]	363	bool "NOR flash (SPI or parallel)"
Joel Johnson	a2018ab	2020-04-17 01:19:05 -0600	[diff] [blame]	364	imply ENV_IS_IN_SPI_FLASH
Pali Rohár	cf97b82	2021-07-23 11:14:29 +0200	[diff] [blame]	365	imply SPL_DM_SPI
				366	imply SPL_SPI_FLASH_SUPPORT
				367	imply SPL_SPI_LOAD
Simon Glass	a582047	2021-08-08 12:20:14 -0600	[diff] [blame]	368	imply SPL_SPI
Pali Rohár	a3a38e5	2021-07-23 11:14:25 +0200	[diff] [blame]	369	select SPL_BOOTROM_SUPPORT
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	370
Pali Rohár	5c5cf60	2023-01-10 22:55:21 +0100	[diff] [blame]	371	config MVEBU_SPL_BOOT_DEVICE_NAND
				372	bool "NAND flash (SPI or parallel)"
				373	select MTD_RAW_NAND
				374	select SPL_BOOTROM_SUPPORT
				375
Baruch Siach	8d196a4	2018-06-18 21:56:24 +0300	[diff] [blame]	376	config MVEBU_SPL_BOOT_DEVICE_MMC
Pali Rohár	8d11032	2023-01-10 23:13:01 +0100	[diff] [blame]	377	bool "eMMC or SD card"
Joel Johnson	a2018ab	2020-04-17 01:19:05 -0600	[diff] [blame]	378	imply ENV_IS_IN_MMC
				379	# GPIO needed for eMMC/SD card presence detection
Pali Rohár	cf97b82	2021-07-23 11:14:29 +0200	[diff] [blame]	380	imply SPL_DM_GPIO
				381	imply SPL_DM_MMC
				382	imply SPL_GPIO
				383	imply SPL_LIBDISK_SUPPORT
Simon Glass	b58bfe0	2021-08-08 12:20:09 -0600	[diff] [blame]	384	imply SPL_MMC
Pali Rohár	cefdc03	2023-01-08 13:31:41 +0100	[diff] [blame]	385	select SUPPORT_EMMC_BOOT if SPL_MMC
Pali Rohár	aa6244e	2023-01-09 00:52:09 +0100	[diff] [blame]	386	select SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR if SPL_MMC
Pali Rohár	a3a38e5	2021-07-23 11:14:25 +0200	[diff] [blame]	387	select SPL_BOOTROM_SUPPORT
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	388
Baruch Siach	b936a27	2019-05-16 13:03:58 +0300	[diff] [blame]	389	config MVEBU_SPL_BOOT_DEVICE_SATA
				390	bool "SATA"
Simon Glass	081a45a	2021-08-08 12:20:17 -0600	[diff] [blame]	391	imply SPL_SATA
Pali Rohár	cf97b82	2021-07-23 11:14:29 +0200	[diff] [blame]	392	imply SPL_LIBDISK_SUPPORT
Pali Rohár	a3a38e5	2021-07-23 11:14:25 +0200	[diff] [blame]	393	select SPL_BOOTROM_SUPPORT
Baruch Siach	b936a27	2019-05-16 13:03:58 +0300	[diff] [blame]	394
Pali Rohár	ea87690	2023-01-10 23:09:15 +0100	[diff] [blame]	395	config MVEBU_SPL_BOOT_DEVICE_PEX
				396	bool "PCI Express"
				397	select SPL_BOOTROM_SUPPORT
				398
Baruch Siach	b35c447	2018-06-18 21:56:26 +0300	[diff] [blame]	399	config MVEBU_SPL_BOOT_DEVICE_UART
				400	bool "UART"
Pali Rohár	a3a38e5	2021-07-23 11:14:25 +0200	[diff] [blame]	401	select SPL_BOOTROM_SUPPORT
Baruch Siach	b35c447	2018-06-18 21:56:26 +0300	[diff] [blame]	402
Marek Behún	09e16b8	2017-06-09 19:28:45 +0200	[diff] [blame]	403	endchoice
				404
Pali Rohár	5c5cf60	2023-01-10 22:55:21 +0100	[diff] [blame]	405	config MVEBU_SPL_NAND_BADBLK_LOCATION
				406	hex "NAND Bad block indicator location"
				407	depends on MVEBU_SPL_BOOT_DEVICE_NAND
				408	range 0x0 0x1
				409	help
				410	Value 0x0 = SLC flash = BBI at page 0 or page 1
				411	Value 0x1 = MLC flash = BBI at last page in the block
				412
Pali Rohár	7085f82	2023-03-29 21:25:58 +0200	[diff] [blame]	413	config MVEBU_SPL_SATA_BLKSZ
				414	int "SATA block size"
				415	depends on MVEBU_SPL_BOOT_DEVICE_SATA
				416	range 512 32768
				417	default 512
				418	help
				419	Block size of the SATA disk in bytes.
				420	Typically 512 bytes for majority of disks
				421	and 4096 bytes for 4K Native disks.
				422
Mario Six	10d1449	2017-01-11 16:01:00 +0100	[diff] [blame]	423	config MVEBU_EFUSE
				424	bool "Enable eFuse support"
Mario Six	10d1449	2017-01-11 16:01:00 +0100	[diff] [blame]	425	depends on HAVE_MVEBU_EFUSE
				426	help
				427	Enable support for reading and writing eFuses on mvebu SoCs.
				428
				429	config MVEBU_EFUSE_FAKE
				430	bool "Fake eFuse access (dry run)"
Mario Six	10d1449	2017-01-11 16:01:00 +0100	[diff] [blame]	431	depends on MVEBU_EFUSE
				432	help
				433	This enables a "dry run" mode where eFuses are not really programmed.
				434	Instead the eFuse accesses are emulated by writing to and reading
				435	from a memory block.
				436	This is can be used for testing prog scripts.
				437
Pali Rohár	2662d2c	2022-09-22 13:43:45 +0200	[diff] [blame]	438	config MVEBU_EFUSE_VHV_GPIO
				439	string "VHV_Enable GPIO name for eFuse programming"
				440	depends on MVEBU_EFUSE && !ARMADA_3700
				441	help
				442	The eFuse programing (burning) phase requires supplying 1.8V to the
				443	device on the VHV power pin, while for normal operation the VHV power
				444	rail must be left unconnected. See Marvell AN-389: ARMADA VHV Power
				445	document (Doc. No. MV-S302545-00 Rev. C, August 2, 2016) for details.
				446	.
				447	This specify VHV_Enable GPIO name used in U-Boot for enabling VHV power.
				448
				449	config MVEBU_EFUSE_VHV_GPIO_ACTIVE_LOW
				450	bool "VHV_Enable GPIO is Active Low"
				451	depends on MVEBU_EFUSE_VHV_GPIO != ""
				452
Mario Six	10d1449	2017-01-11 16:01:00 +0100	[diff] [blame]	453	config SECURED_MODE_IMAGE
				454	bool "Build image for trusted boot"
				455	default false
				456	depends on 88F6820
				457	help
				458	Build an image that employs the ARMADA SoC's trusted boot framework
				459	for securely booting images.
				460
				461	config SECURED_MODE_CSK_INDEX
				462	int "Index of active CSK"
				463	default 0
				464	depends on SECURED_MODE_IMAGE
				465
Tony Dinh	89dc46d	2023-03-02 19:27:29 -0800	[diff] [blame]	466	config SF_DEFAULT_SPEED
				467	int "Default speed for SPI flash in Hz"
				468	default 10000000
				469	depends on MVEBU_SPL_BOOT_DEVICE_SPI
				470
				471	config SF_DEFAULT_MODE
				472	hex "Default mode for SPI flash"
				473	default 0x0
				474	depends on MVEBU_SPL_BOOT_DEVICE_SPI
				475
Marek Behún	514628c	2024-04-04 09:51:00 +0200	[diff] [blame]	476	config ARMADA_32BIT_SYSCON
				477	bool
				478	depends on ARMADA_32BIT
				479	select REGMAP
				480	select SYSCON
				481
Marek Behún	1c657bc	2024-04-04 09:50:58 +0200	[diff] [blame]	482	config ARMADA_32BIT_SYSCON_RESET
				483	bool "Support Armada XP/375/38x/39x reset controller"
				484	depends on ARMADA_32BIT
				485	depends on DM_RESET
Marek Behún	514628c	2024-04-04 09:51:00 +0200	[diff] [blame]	486	select ARMADA_32BIT_SYSCON
Marek Behún	1c657bc	2024-04-04 09:50:58 +0200	[diff] [blame]	487	help
				488	Build support for Armada XP/375/38x/39x reset controller. This is
				489	needed for PCIe support.
				490
Marek Behún	514628c	2024-04-04 09:51:00 +0200	[diff] [blame]	491	config ARMADA_32BIT_SYSCON_SYSRESET
				492	bool "Support Armada XP/375/38x/39x sysreset via driver model"
				493	depends on ARMADA_32BIT
				494	depends on SYSRESET
				495	select ARMADA_32BIT_SYSCON
				496	help
				497	Build support for Armada XP/375/38x/39x system reset via driver model.
				498
Joel Johnson	28bf4ca	2020-03-23 14:21:32 -0600	[diff] [blame]	499	source "board/solidrun/clearfog/Kconfig"
Dennis Gilmore	838e49b	2020-12-08 21:07:36 -0600	[diff] [blame]	500	source "board/kobol/helios4/Kconfig"
Joel Johnson	28bf4ca	2020-03-23 14:21:32 -0600	[diff] [blame]	501
Stefan Roese	383e0c1	2015-08-25 13:18:38 +0200	[diff] [blame]	502	endif