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git01.mediatek.com / filogic / uboot / cdc2ca10093af95dfb360c9fc15a5a4a664e1db4 / . / arch / arm / dts / stm32mp15-u-boot.dtsi
blob: 42e2e2efc5f11d569ef3e661eb36f76beeef8fcc [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]2/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]4 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 gpio9 = &gpioj;
18 gpio10 = &gpiok;
19 gpio25 = &gpioz;
Patrick Delaunay1b58b552019-04-12 14:38:28 +0200[diff] [blame]20 pinctrl0 = &pinctrl;
21 pinctrl1 = &pinctrl_z;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]22 };
23
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]24 clocks {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]25 u-boot,dm-pre-reloc;
26 };
27
Patrick Delaunaycf45d9d2019-07-30 19:16:15 +0200[diff] [blame]28 /* need PSCI for sysreset during board_f */
29 psci {
30 u-boot,dm-pre-proper;
31 };
32
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]33 reboot {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]34 u-boot,dm-pre-reloc;
Patrick Delaunaycdc2ca12020-07-06 13:26:53 +0200[diff] [blame^]35 compatible = "syscon-reboot";
36 regmap = <&rcc>;
37 offset = <0x404>;
38 mask = <0x1>;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]39 };
40
41 soc {
42 u-boot,dm-pre-reloc;
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame]43
44 ddr: ddr@5a003000 {
45 u-boot,dm-pre-reloc;
46
47 compatible = "st,stm32mp1-ddr";
48
49 reg = <0x5A003000 0x550
50 0x5A004000 0x234>;
51
52 clocks = <&rcc AXIDCG>,
53 <&rcc DDRC1>,
54 <&rcc DDRC2>,
55 <&rcc DDRPHYC>,
56 <&rcc DDRCAPB>,
57 <&rcc DDRPHYCAPB>;
58
59 clock-names = "axidcg",
60 "ddrc1",
61 "ddrc2",
62 "ddrphyc",
63 "ddrcapb",
64 "ddrphycapb";
65
66 status = "okay";
67 };
Patrick Delaunay089d4352018-03-20 11:45:14 +0100[diff] [blame]68 };
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]69};
70
Patrick Delaunaybdd71362019-02-27 17:01:27 +0100[diff] [blame]71&bsec {
Patrick Delaunayb6cc5052020-05-25 12:19:41 +0200[diff] [blame]72 u-boot,dm-pre-reloc;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]73};
74
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]75&clk_csi {
76 u-boot,dm-pre-reloc;
77};
78
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]79&clk_hsi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]80 u-boot,dm-pre-reloc;
81};
82
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]83&clk_hse {
Patrick Delaunay32ddd262018-03-20 14:15:06 +0100[diff] [blame]84 u-boot,dm-pre-reloc;
85};
86
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]87&clk_lsi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]88 u-boot,dm-pre-reloc;
89};
90
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]91&clk_lse {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]92 u-boot,dm-pre-reloc;
93};
94
Patrick Delaunay72b10802020-05-25 12:19:48 +0200[diff] [blame]95&cpu0_opp_table {
96 u-boot,dm-spl;
97 opp-650000000 {
98 u-boot,dm-spl;
99 };
100 opp-800000000 {
101 u-boot,dm-spl;
102 };
103};
104
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]105&gpioa {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]106 u-boot,dm-pre-reloc;
107};
108
109&gpiob {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]110 u-boot,dm-pre-reloc;
111};
112
113&gpioc {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]114 u-boot,dm-pre-reloc;
115};
116
117&gpiod {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]118 u-boot,dm-pre-reloc;
119};
120
121&gpioe {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]122 u-boot,dm-pre-reloc;
123};
124
125&gpiof {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]126 u-boot,dm-pre-reloc;
127};
128
129&gpiog {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]130 u-boot,dm-pre-reloc;
131};
132
133&gpioh {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]134 u-boot,dm-pre-reloc;
135};
136
137&gpioi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]138 u-boot,dm-pre-reloc;
139};
140
141&gpioj {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]142 u-boot,dm-pre-reloc;
143};
144
145&gpiok {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]146 u-boot,dm-pre-reloc;
147};
148
149&gpioz {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]150 u-boot,dm-pre-reloc;
151};
Patrice Chotard26d11072019-04-30 17:26:21 +0200[diff] [blame]152
Patrick Delaunay1ebe34b2019-07-30 19:16:14 +0200[diff] [blame]153&iwdg2 {
154 u-boot,dm-pre-reloc;
155};
156
Patrick Delaunayd918b882019-07-30 19:16:16 +0200[diff] [blame]157/* pre-reloc probe = reserve video frame buffer in video_reserve() */
158&ltdc {
159 u-boot,dm-pre-proper;
160};
161
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]162&pinctrl {
163 u-boot,dm-pre-reloc;
164};
165
166&pinctrl_z {
167 u-boot,dm-pre-reloc;
168};
169
Patrick Delaunay900494d2020-01-28 10:10:59 +0100[diff] [blame]170&pwr_regulators {
Patrice Chotard26d11072019-04-30 17:26:21 +0200[diff] [blame]171 u-boot,dm-pre-reloc;
172};
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]173
174&rcc {
175 u-boot,dm-pre-reloc;
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]176 #address-cells = <1>;
177 #size-cells = <0>;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]178};
179
180&sdmmc1 {
181 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
182};
183
184&sdmmc2 {
185 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
186};
187
188&sdmmc3 {
189 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
190};
191
192&usbotg_hs {
193 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
194};