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git01.mediatek.com / filogic / uboot / 379775ca10bb8463aad49599cea5416806a9bc69 / . / arch / arm / dts / stm32mp15-u-boot.dtsi
blob: 1279589a563246d1b55c9835750e291d8fef8afc [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]2/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]4 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 gpio9 = &gpioj;
18 gpio10 = &gpiok;
19 gpio25 = &gpioz;
Patrick Delaunay1b58b552019-04-12 14:38:28 +0200[diff] [blame]20 pinctrl0 = &pinctrl;
21 pinctrl1 = &pinctrl_z;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]22 };
23
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]24 clocks {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]25 u-boot,dm-pre-reloc;
26 };
27
Patrick Delaunaycf45d9d2019-07-30 19:16:15 +0200[diff] [blame]28 /* need PSCI for sysreset during board_f */
29 psci {
30 u-boot,dm-pre-proper;
31 };
32
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]33 reboot {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]34 u-boot,dm-pre-reloc;
35 };
36
37 soc {
38 u-boot,dm-pre-reloc;
Marek Vasut379775c2020-04-22 13:18:13 +0200[diff] [blame^]39
40 ddr: ddr@5a003000 {
41 u-boot,dm-pre-reloc;
42
43 compatible = "st,stm32mp1-ddr";
44
45 reg = <0x5A003000 0x550
46 0x5A004000 0x234>;
47
48 clocks = <&rcc AXIDCG>,
49 <&rcc DDRC1>,
50 <&rcc DDRC2>,
51 <&rcc DDRPHYC>,
52 <&rcc DDRCAPB>,
53 <&rcc DDRPHYCAPB>;
54
55 clock-names = "axidcg",
56 "ddrc1",
57 "ddrc2",
58 "ddrphyc",
59 "ddrcapb",
60 "ddrphycapb";
61
62 status = "okay";
63 };
Patrick Delaunay089d4352018-03-20 11:45:14 +0100[diff] [blame]64 };
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]65};
66
Patrick Delaunaybdd71362019-02-27 17:01:27 +0100[diff] [blame]67&bsec {
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]68 u-boot,dm-pre-proper;
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]69};
70
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]71&clk_csi {
72 u-boot,dm-pre-reloc;
73};
74
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]75&clk_hsi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]76 u-boot,dm-pre-reloc;
77};
78
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]79&clk_hse {
Patrick Delaunay32ddd262018-03-20 14:15:06 +0100[diff] [blame]80 u-boot,dm-pre-reloc;
81};
82
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]83&clk_lsi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]84 u-boot,dm-pre-reloc;
85};
86
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]87&clk_lse {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]88 u-boot,dm-pre-reloc;
89};
90
91&gpioa {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]92 u-boot,dm-pre-reloc;
93};
94
95&gpiob {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]96 u-boot,dm-pre-reloc;
97};
98
99&gpioc {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]100 u-boot,dm-pre-reloc;
101};
102
103&gpiod {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]104 u-boot,dm-pre-reloc;
105};
106
107&gpioe {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]108 u-boot,dm-pre-reloc;
109};
110
111&gpiof {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]112 u-boot,dm-pre-reloc;
113};
114
115&gpiog {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]116 u-boot,dm-pre-reloc;
117};
118
119&gpioh {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]120 u-boot,dm-pre-reloc;
121};
122
123&gpioi {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]124 u-boot,dm-pre-reloc;
125};
126
127&gpioj {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]128 u-boot,dm-pre-reloc;
129};
130
131&gpiok {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]132 u-boot,dm-pre-reloc;
133};
134
135&gpioz {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100[diff] [blame]136 u-boot,dm-pre-reloc;
137};
Patrice Chotard26d11072019-04-30 17:26:21 +0200[diff] [blame]138
Patrick Delaunay1ebe34b2019-07-30 19:16:14 +0200[diff] [blame]139&iwdg2 {
140 u-boot,dm-pre-reloc;
141};
142
Patrick Delaunayd918b882019-07-30 19:16:16 +0200[diff] [blame]143/* pre-reloc probe = reserve video frame buffer in video_reserve() */
144&ltdc {
145 u-boot,dm-pre-proper;
146};
147
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]148&pinctrl {
149 u-boot,dm-pre-reloc;
150};
151
152&pinctrl_z {
153 u-boot,dm-pre-reloc;
154};
155
Patrick Delaunay900494d2020-01-28 10:10:59 +0100[diff] [blame]156&pwr_regulators {
Patrice Chotard26d11072019-04-30 17:26:21 +0200[diff] [blame]157 u-boot,dm-pre-reloc;
158};
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]159
160&rcc {
161 u-boot,dm-pre-reloc;
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]162 #address-cells = <1>;
163 #size-cells = <0>;
Patrick Delaunaya3705302019-07-11 11:15:28 +0200[diff] [blame]164};
165
166&sdmmc1 {
167 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
168};
169
170&sdmmc2 {
171 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
172};
173
174&sdmmc3 {
175 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
176};
177
178&usbotg_hs {
179 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
180};