blob: cb8d60e33da647c0cdea451e4a4cadf00dd4ab5c [file] [log] [blame]
Tom Rini8b0c8a12018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay06020d82018-03-12 10:46:17 +01002/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay06020d82018-03-12 10:46:17 +01004 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 gpio9 = &gpioj;
18 gpio10 = &gpiok;
19 gpio25 = &gpioz;
Patrick Delaunay1b58b552019-04-12 14:38:28 +020020 pinctrl0 = &pinctrl;
21 pinctrl1 = &pinctrl_z;
Patrick Delaunay06020d82018-03-12 10:46:17 +010022 };
23
Patrick Delaunaya3705302019-07-11 11:15:28 +020024 clocks {
Patrick Delaunay06020d82018-03-12 10:46:17 +010025 u-boot,dm-pre-reloc;
26 };
27
Patrick Delaunaycf45d9d2019-07-30 19:16:15 +020028 /* need PSCI for sysreset during board_f */
29 psci {
30 u-boot,dm-pre-proper;
31 };
32
Patrick Delaunaya3705302019-07-11 11:15:28 +020033 reboot {
Patrick Delaunay06020d82018-03-12 10:46:17 +010034 u-boot,dm-pre-reloc;
35 };
36
37 soc {
38 u-boot,dm-pre-reloc;
Patrick Delaunay089d4352018-03-20 11:45:14 +010039 };
Patrick Delaunay06020d82018-03-12 10:46:17 +010040};
41
Patrick Delaunaybdd71362019-02-27 17:01:27 +010042&bsec {
Patrick Delaunaya3705302019-07-11 11:15:28 +020043 u-boot,dm-pre-proper;
Patrick Delaunay06020d82018-03-12 10:46:17 +010044};
45
Patrick Delaunay06020d82018-03-12 10:46:17 +010046&clk_csi {
47 u-boot,dm-pre-reloc;
48};
49
Patrick Delaunaya3705302019-07-11 11:15:28 +020050&clk_hsi {
Patrick Delaunay06020d82018-03-12 10:46:17 +010051 u-boot,dm-pre-reloc;
52};
53
Patrick Delaunaya3705302019-07-11 11:15:28 +020054&clk_hse {
Patrick Delaunay32ddd262018-03-20 14:15:06 +010055 u-boot,dm-pre-reloc;
56};
57
Patrick Delaunaya3705302019-07-11 11:15:28 +020058&clk_lsi {
Patrick Delaunay06020d82018-03-12 10:46:17 +010059 u-boot,dm-pre-reloc;
60};
61
Patrick Delaunaya3705302019-07-11 11:15:28 +020062&clk_lse {
Patrick Delaunay06020d82018-03-12 10:46:17 +010063 u-boot,dm-pre-reloc;
64};
65
66&gpioa {
Patrick Delaunay06020d82018-03-12 10:46:17 +010067 u-boot,dm-pre-reloc;
68};
69
70&gpiob {
Patrick Delaunay06020d82018-03-12 10:46:17 +010071 u-boot,dm-pre-reloc;
72};
73
74&gpioc {
Patrick Delaunay06020d82018-03-12 10:46:17 +010075 u-boot,dm-pre-reloc;
76};
77
78&gpiod {
Patrick Delaunay06020d82018-03-12 10:46:17 +010079 u-boot,dm-pre-reloc;
80};
81
82&gpioe {
Patrick Delaunay06020d82018-03-12 10:46:17 +010083 u-boot,dm-pre-reloc;
84};
85
86&gpiof {
Patrick Delaunay06020d82018-03-12 10:46:17 +010087 u-boot,dm-pre-reloc;
88};
89
90&gpiog {
Patrick Delaunay06020d82018-03-12 10:46:17 +010091 u-boot,dm-pre-reloc;
92};
93
94&gpioh {
Patrick Delaunay06020d82018-03-12 10:46:17 +010095 u-boot,dm-pre-reloc;
96};
97
98&gpioi {
Patrick Delaunay06020d82018-03-12 10:46:17 +010099 u-boot,dm-pre-reloc;
100};
101
102&gpioj {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100103 u-boot,dm-pre-reloc;
104};
105
106&gpiok {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100107 u-boot,dm-pre-reloc;
108};
109
110&gpioz {
Patrick Delaunay06020d82018-03-12 10:46:17 +0100111 u-boot,dm-pre-reloc;
112};
Patrice Chotard26d11072019-04-30 17:26:21 +0200113
Patrick Delaunay1ebe34b2019-07-30 19:16:14 +0200114&iwdg2 {
115 u-boot,dm-pre-reloc;
116};
117
Patrick Delaunayd918b882019-07-30 19:16:16 +0200118/* pre-reloc probe = reserve video frame buffer in video_reserve() */
119&ltdc {
120 u-boot,dm-pre-proper;
121};
122
Patrick Delaunaya3705302019-07-11 11:15:28 +0200123&pinctrl {
124 u-boot,dm-pre-reloc;
125};
126
127&pinctrl_z {
128 u-boot,dm-pre-reloc;
129};
130
Patrick Delaunay900494d2020-01-28 10:10:59 +0100131&pwr_regulators {
Patrice Chotard26d11072019-04-30 17:26:21 +0200132 u-boot,dm-pre-reloc;
133};
Patrick Delaunaya3705302019-07-11 11:15:28 +0200134
135&rcc {
136 u-boot,dm-pre-reloc;
137};
138
139&sdmmc1 {
140 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
141};
142
143&sdmmc2 {
144 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
145};
146
147&sdmmc3 {
148 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
149};
150
151&usbotg_hs {
152 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
153};