Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | menu "MIPS architecture" |
| 2 | depends on MIPS |
| 3 | |
| 4 | config SYS_ARCH |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 5 | default "mips" |
| 6 | |
Daniel Schwierzeck | 99e7af2 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 7 | config SYS_CPU |
Paul Burton | 3246437 | 2016-05-16 10:52:11 +0100 | [diff] [blame] | 8 | default "mips32" if CPU_MIPS32 |
| 9 | default "mips64" if CPU_MIPS64 |
Daniel Schwierzeck | 99e7af2 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 10 | |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 11 | choice |
| 12 | prompt "Target select" |
Joe Hershberger | f069960 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 13 | optional |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 14 | |
| 15 | config TARGET_QEMU_MIPS |
| 16 | bool "Support qemu-mips" |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 17 | select SUPPORTS_BIG_ENDIAN |
| 18 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 19 | select SUPPORTS_CPU_MIPS32_R1 |
| 20 | select SUPPORTS_CPU_MIPS32_R2 |
Daniel Schwierzeck | 94384d1 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 21 | select SUPPORTS_CPU_MIPS64_R1 |
| 22 | select SUPPORTS_CPU_MIPS64_R2 |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 23 | |
| 24 | config TARGET_MALTA |
| 25 | bool "Support malta" |
Paul Burton | a31a3df | 2016-05-17 07:43:28 +0100 | [diff] [blame] | 26 | select DM |
| 27 | select DM_SERIAL |
Paul Burton | 8d6600b | 2016-01-29 13:54:52 +0000 | [diff] [blame] | 28 | select DYNAMIC_IO_PORT_BASE |
Paul Burton | 59a4c8b | 2016-09-21 11:18:56 +0100 | [diff] [blame] | 29 | select MIPS_CM |
| 30 | select MIPS_L2_CACHE |
Paul Burton | a31a3df | 2016-05-17 07:43:28 +0100 | [diff] [blame] | 31 | select OF_CONTROL |
| 32 | select OF_ISA_BUS |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 33 | select SUPPORTS_BIG_ENDIAN |
| 34 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 35 | select SUPPORTS_CPU_MIPS32_R1 |
| 36 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | 1c10e0d | 2016-05-16 10:52:14 +0100 | [diff] [blame] | 37 | select SUPPORTS_CPU_MIPS32_R6 |
Paul Burton | 825cfbd | 2016-05-26 14:49:36 +0100 | [diff] [blame] | 38 | select SUPPORTS_CPU_MIPS64_R1 |
| 39 | select SUPPORTS_CPU_MIPS64_R2 |
| 40 | select SUPPORTS_CPU_MIPS64_R6 |
Daniel Schwierzeck | 7dca686 | 2015-01-18 22:00:18 +0100 | [diff] [blame] | 41 | select SWAP_IO_SPACE |
Daniel Schwierzeck | 02ca55e | 2016-01-09 17:32:50 +0100 | [diff] [blame] | 42 | select MIPS_L1_CACHE_SHIFT_6 |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 43 | |
| 44 | config TARGET_VCT |
| 45 | bool "Support vct" |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 46 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 47 | select SUPPORTS_CPU_MIPS32_R1 |
| 48 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | 6832bdc | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 49 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 50 | |
| 51 | config TARGET_DBAU1X00 |
| 52 | bool "Support dbau1x00" |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 53 | select SUPPORTS_BIG_ENDIAN |
| 54 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 55 | select SUPPORTS_CPU_MIPS32_R1 |
| 56 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | 6832bdc | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 57 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
Daniel Schwierzeck | aadd332 | 2015-12-26 19:55:37 +0100 | [diff] [blame] | 58 | select MIPS_TUNE_4KC |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 59 | |
| 60 | config TARGET_PB1X00 |
| 61 | bool "Support pb1x00" |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 62 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 63 | select SUPPORTS_CPU_MIPS32_R1 |
| 64 | select SUPPORTS_CPU_MIPS32_R2 |
Paul Burton | 6832bdc | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 65 | select SYS_MIPS_CACHE_INIT_RAM_LOAD |
Daniel Schwierzeck | aadd332 | 2015-12-26 19:55:37 +0100 | [diff] [blame] | 66 | select MIPS_TUNE_4KC |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 67 | |
Wills Wang | 833a1a8 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 68 | config ARCH_ATH79 |
| 69 | bool "Support QCA/Atheros ath79" |
| 70 | select OF_CONTROL |
| 71 | select DM |
| 72 | |
Purna Chandra Mandal | 825b321 | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 73 | config MACH_PIC32 |
| 74 | bool "Support Microchip PIC32" |
| 75 | select OF_CONTROL |
| 76 | select DM |
| 77 | |
Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 78 | config TARGET_BOSTON |
| 79 | bool "Support Boston" |
| 80 | select DM |
| 81 | select DM_SERIAL |
| 82 | select OF_CONTROL |
| 83 | select MIPS_CM |
| 84 | select MIPS_L1_CACHE_SHIFT_6 |
| 85 | select MIPS_L2_CACHE |
| 86 | select SUPPORTS_BIG_ENDIAN |
| 87 | select SUPPORTS_LITTLE_ENDIAN |
| 88 | select SUPPORTS_CPU_MIPS32_R1 |
| 89 | select SUPPORTS_CPU_MIPS32_R2 |
| 90 | select SUPPORTS_CPU_MIPS32_R6 |
| 91 | select SUPPORTS_CPU_MIPS64_R1 |
| 92 | select SUPPORTS_CPU_MIPS64_R2 |
| 93 | select SUPPORTS_CPU_MIPS64_R6 |
| 94 | |
Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 95 | config TARGET_XILFPGA |
| 96 | bool "Support Imagination Xilfpga" |
| 97 | select OF_CONTROL |
| 98 | select DM |
| 99 | select DM_SERIAL |
| 100 | select DM_GPIO |
| 101 | select DM_ETH |
| 102 | select SUPPORTS_LITTLE_ENDIAN |
| 103 | select SUPPORTS_CPU_MIPS32_R1 |
| 104 | select SUPPORTS_CPU_MIPS32_R2 |
| 105 | select MIPS_L1_CACHE_SHIFT_4 |
| 106 | help |
| 107 | This supports IMGTEC MIPSfpga platform |
| 108 | |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 109 | endchoice |
| 110 | |
| 111 | source "board/dbau1x00/Kconfig" |
Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 112 | source "board/imgtec/boston/Kconfig" |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 113 | source "board/imgtec/malta/Kconfig" |
Zubair Lutfullah Kakakhel | 1d153b3 | 2016-07-29 15:11:20 +0100 | [diff] [blame] | 114 | source "board/imgtec/xilfpga/Kconfig" |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 115 | source "board/micronas/vct/Kconfig" |
| 116 | source "board/pb1x00/Kconfig" |
| 117 | source "board/qemu-mips/Kconfig" |
Wills Wang | 833a1a8 | 2016-03-16 16:59:52 +0800 | [diff] [blame] | 118 | source "arch/mips/mach-ath79/Kconfig" |
Purna Chandra Mandal | 825b321 | 2016-01-28 15:30:10 +0530 | [diff] [blame] | 119 | source "arch/mips/mach-pic32/Kconfig" |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 120 | |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 121 | if MIPS |
| 122 | |
| 123 | choice |
| 124 | prompt "Endianness selection" |
| 125 | help |
| 126 | Some MIPS boards can be configured for either little or big endian |
| 127 | byte order. These modes require different U-Boot images. In general there |
| 128 | is one preferred byteorder for a particular system but some systems are |
| 129 | just as commonly used in the one or the other endianness. |
| 130 | |
| 131 | config SYS_BIG_ENDIAN |
| 132 | bool "Big endian" |
| 133 | depends on SUPPORTS_BIG_ENDIAN |
| 134 | |
| 135 | config SYS_LITTLE_ENDIAN |
| 136 | bool "Little endian" |
| 137 | depends on SUPPORTS_LITTLE_ENDIAN |
| 138 | |
| 139 | endchoice |
| 140 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 141 | choice |
| 142 | prompt "CPU selection" |
| 143 | default CPU_MIPS32_R2 |
| 144 | |
| 145 | config CPU_MIPS32_R1 |
| 146 | bool "MIPS32 Release 1" |
| 147 | depends on SUPPORTS_CPU_MIPS32_R1 |
| 148 | select 32BIT |
| 149 | help |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 150 | Choose this option to build an U-Boot for release 1 through 5 of the |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 151 | MIPS32 architecture. |
| 152 | |
| 153 | config CPU_MIPS32_R2 |
| 154 | bool "MIPS32 Release 2" |
| 155 | depends on SUPPORTS_CPU_MIPS32_R2 |
| 156 | select 32BIT |
| 157 | help |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 158 | Choose this option to build an U-Boot for release 2 through 5 of the |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 159 | MIPS32 architecture. |
| 160 | |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 161 | config CPU_MIPS32_R6 |
| 162 | bool "MIPS32 Release 6" |
| 163 | depends on SUPPORTS_CPU_MIPS32_R6 |
| 164 | select 32BIT |
| 165 | help |
| 166 | Choose this option to build an U-Boot for release 6 or later of the |
| 167 | MIPS32 architecture. |
| 168 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 169 | config CPU_MIPS64_R1 |
| 170 | bool "MIPS64 Release 1" |
| 171 | depends on SUPPORTS_CPU_MIPS64_R1 |
| 172 | select 64BIT |
| 173 | help |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 174 | Choose this option to build a kernel for release 1 through 5 of the |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 175 | MIPS64 architecture. |
| 176 | |
| 177 | config CPU_MIPS64_R2 |
| 178 | bool "MIPS64 Release 2" |
| 179 | depends on SUPPORTS_CPU_MIPS64_R2 |
| 180 | select 64BIT |
| 181 | help |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 182 | Choose this option to build a kernel for release 2 through 5 of the |
| 183 | MIPS64 architecture. |
| 184 | |
| 185 | config CPU_MIPS64_R6 |
| 186 | bool "MIPS64 Release 6" |
| 187 | depends on SUPPORTS_CPU_MIPS64_R6 |
| 188 | select 64BIT |
| 189 | help |
| 190 | Choose this option to build a kernel for release 6 or later of the |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 191 | MIPS64 architecture. |
| 192 | |
| 193 | endchoice |
| 194 | |
Daniel Schwierzeck | f9749fa | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 195 | menu "OS boot interface" |
| 196 | |
| 197 | config MIPS_BOOT_CMDLINE_LEGACY |
| 198 | bool "Hand over legacy command line to Linux kernel" |
| 199 | default y |
| 200 | help |
| 201 | Enable this option if you want U-Boot to hand over the Yamon-style |
| 202 | command line to the kernel. All bootargs will be prepared as argc/argv |
| 203 | compatible list. The argument count (argc) is stored in register $a0. |
| 204 | The address of the argument list (argv) is stored in register $a1. |
| 205 | |
Daniel Schwierzeck | c07dc60 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 206 | config MIPS_BOOT_ENV_LEGACY |
| 207 | bool "Hand over legacy environment to Linux kernel" |
| 208 | default y |
| 209 | help |
| 210 | Enable this option if you want U-Boot to hand over the Yamon-style |
| 211 | environment to the kernel. Information like memory size, initrd |
| 212 | address and size will be prepared as zero-terminated key/value list. |
Robert P. J. Day | 8c60f92 | 2016-05-04 04:47:31 -0400 | [diff] [blame] | 213 | The address of the environment is stored in register $a2. |
Daniel Schwierzeck | c07dc60 | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 214 | |
Daniel Schwierzeck | 8d7ff4d | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 215 | config MIPS_BOOT_FDT |
Daniel Schwierzeck | d1b29d2 | 2015-02-22 16:58:30 +0100 | [diff] [blame] | 216 | bool "Hand over a flattened device tree to Linux kernel" |
Daniel Schwierzeck | 8d7ff4d | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 217 | default n |
| 218 | help |
| 219 | Enable this option if you want U-Boot to hand over a flattened |
Daniel Schwierzeck | d1b29d2 | 2015-02-22 16:58:30 +0100 | [diff] [blame] | 220 | device tree to the kernel. According to UHI register $a0 will be set |
| 221 | to -2 and the FDT address is stored in $a1. |
Daniel Schwierzeck | 8d7ff4d | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 222 | |
Daniel Schwierzeck | f9749fa | 2015-01-14 21:44:13 +0100 | [diff] [blame] | 223 | endmenu |
| 224 | |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 225 | config SUPPORTS_BIG_ENDIAN |
| 226 | bool |
| 227 | |
| 228 | config SUPPORTS_LITTLE_ENDIAN |
| 229 | bool |
| 230 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 231 | config SUPPORTS_CPU_MIPS32_R1 |
| 232 | bool |
| 233 | |
| 234 | config SUPPORTS_CPU_MIPS32_R2 |
| 235 | bool |
| 236 | |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 237 | config SUPPORTS_CPU_MIPS32_R6 |
| 238 | bool |
| 239 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 240 | config SUPPORTS_CPU_MIPS64_R1 |
| 241 | bool |
| 242 | |
| 243 | config SUPPORTS_CPU_MIPS64_R2 |
| 244 | bool |
| 245 | |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 246 | config SUPPORTS_CPU_MIPS64_R6 |
| 247 | bool |
| 248 | |
Daniel Schwierzeck | dfbad0f | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 249 | config CPU_MIPS32 |
| 250 | bool |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 251 | default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 |
Daniel Schwierzeck | dfbad0f | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 252 | |
| 253 | config CPU_MIPS64 |
| 254 | bool |
Paul Burton | 55e29dd | 2016-05-16 10:52:12 +0100 | [diff] [blame] | 255 | default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 |
Daniel Schwierzeck | dfbad0f | 2015-01-18 21:59:35 +0100 | [diff] [blame] | 256 | |
Daniel Schwierzeck | aadd332 | 2015-12-26 19:55:37 +0100 | [diff] [blame] | 257 | config MIPS_TUNE_4KC |
| 258 | bool |
| 259 | |
| 260 | config MIPS_TUNE_14KC |
| 261 | bool |
| 262 | |
| 263 | config MIPS_TUNE_24KC |
| 264 | bool |
| 265 | |
Daniel Schwierzeck | c7661d5 | 2016-05-27 15:39:39 +0200 | [diff] [blame] | 266 | config MIPS_TUNE_34KC |
| 267 | bool |
| 268 | |
Marek Vasut | a9c6e8b | 2016-05-06 20:10:33 +0200 | [diff] [blame] | 269 | config MIPS_TUNE_74KC |
| 270 | bool |
| 271 | |
Daniel Schwierzeck | 256034d | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 272 | config 32BIT |
| 273 | bool |
| 274 | |
| 275 | config 64BIT |
| 276 | bool |
| 277 | |
Daniel Schwierzeck | 7dca686 | 2015-01-18 22:00:18 +0100 | [diff] [blame] | 278 | config SWAP_IO_SPACE |
| 279 | bool |
| 280 | |
Paul Burton | 6832bdc | 2015-01-29 01:28:02 +0000 | [diff] [blame] | 281 | config SYS_MIPS_CACHE_INIT_RAM_LOAD |
| 282 | bool |
| 283 | |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 284 | config SYS_DCACHE_SIZE |
| 285 | int |
| 286 | default 0 |
| 287 | help |
| 288 | The total size of the L1 Dcache, if known at compile time. |
| 289 | |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 290 | config SYS_DCACHE_LINE_SIZE |
Paul Burton | 79e49fd | 2016-06-09 13:09:52 +0100 | [diff] [blame] | 291 | int |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 292 | default 0 |
| 293 | help |
| 294 | The size of L1 Dcache lines, if known at compile time. |
| 295 | |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 296 | config SYS_ICACHE_SIZE |
| 297 | int |
| 298 | default 0 |
| 299 | help |
| 300 | The total size of the L1 ICache, if known at compile time. |
| 301 | |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 302 | config SYS_ICACHE_LINE_SIZE |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 303 | int |
| 304 | default 0 |
| 305 | help |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 306 | The size of L1 Icache lines, if known at compile time. |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 307 | |
| 308 | config SYS_CACHE_SIZE_AUTO |
| 309 | def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ |
Paul Burton | 62f1352 | 2016-05-27 14:28:05 +0100 | [diff] [blame] | 310 | SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 |
Paul Burton | 5e51142 | 2016-05-27 14:28:04 +0100 | [diff] [blame] | 311 | help |
| 312 | Select this (or let it be auto-selected by not defining any cache |
| 313 | sizes) in order to allow U-Boot to automatically detect the sizes |
| 314 | of caches at runtime. This has a small cost in code size & runtime |
| 315 | so if you know the cache configuration for your system at compile |
| 316 | time it would be beneficial to configure it. |
| 317 | |
Daniel Schwierzeck | 02ca55e | 2016-01-09 17:32:50 +0100 | [diff] [blame] | 318 | config MIPS_L1_CACHE_SHIFT_4 |
| 319 | bool |
| 320 | |
| 321 | config MIPS_L1_CACHE_SHIFT_5 |
| 322 | bool |
| 323 | |
| 324 | config MIPS_L1_CACHE_SHIFT_6 |
| 325 | bool |
| 326 | |
| 327 | config MIPS_L1_CACHE_SHIFT_7 |
| 328 | bool |
| 329 | |
| 330 | config MIPS_L1_CACHE_SHIFT |
| 331 | int |
| 332 | default "7" if MIPS_L1_CACHE_SHIFT_7 |
| 333 | default "6" if MIPS_L1_CACHE_SHIFT_6 |
| 334 | default "5" if MIPS_L1_CACHE_SHIFT_5 |
| 335 | default "4" if MIPS_L1_CACHE_SHIFT_4 |
| 336 | default "5" |
| 337 | |
Paul Burton | 8156078 | 2016-09-21 11:18:54 +0100 | [diff] [blame] | 338 | config MIPS_L2_CACHE |
| 339 | bool |
| 340 | help |
| 341 | Select this if your system includes an L2 cache and you want U-Boot |
| 342 | to initialise & maintain it. |
| 343 | |
Paul Burton | 8d6600b | 2016-01-29 13:54:52 +0000 | [diff] [blame] | 344 | config DYNAMIC_IO_PORT_BASE |
| 345 | bool |
| 346 | |
Paul Burton | 79ac174 | 2016-09-21 11:18:53 +0100 | [diff] [blame] | 347 | config MIPS_CM |
| 348 | bool |
| 349 | help |
| 350 | Select this if your system contains a MIPS Coherence Manager and you |
| 351 | wish U-Boot to configure it or make use of it to retrieve system |
| 352 | information such as cache configuration. |
| 353 | |
| 354 | config MIPS_CM_BASE |
| 355 | hex |
| 356 | default 0x1fbf8000 |
| 357 | help |
| 358 | The physical base address at which to map the MIPS Coherence Manager |
| 359 | Global Configuration Registers (GCRs). This should be set such that |
| 360 | the GCRs occupy a region of the physical address space which is |
| 361 | otherwise unused, or at minimum that software doesn't need to access. |
| 362 | |
Daniel Schwierzeck | a4c242b | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 363 | endif |
| 364 | |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 365 | endmenu |