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git01.mediatek.com / filogic / uboot / cb2a32a90534e6a15ca2d8da0072498e9688a11c / . / include / configs / ti_omap3_common.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]2/*
3 * ti_omap3_common.h
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 *
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]7 * For more details, please see the technical documents listed at
8 * http://www.ti.com/product/omap3530
9 * http://www.ti.com/product/omap3630
10 * http://www.ti.com/product/dm3730
11 */
12
13#ifndef __CONFIG_TI_OMAP3_COMMON_H__
14#define __CONFIG_TI_OMAP3_COMMON_H__
15
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +0100[diff] [blame]16/*
17 * High Level Configuration Options
18 */
19
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]20#include <asm/arch/cpu.h>
Nishanth Menonfa96c962015-03-09 17:12:04 -0500[diff] [blame]21#include <asm/arch/omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]22
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]23/* Clock Defines */
24#define V_OSCK 26000000 /* Clock output from T2 */
25#define V_SCLK (V_OSCK >> 1)
26
27/* NS16550 Configuration */
28#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
Thomas Chou52ac4432015-11-19 21:48:12 +0800[diff] [blame]29#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Derald D. Woods26fd38c2018-02-04 19:04:49 -0600[diff] [blame]30#if !defined(CONFIG_DM_SERIAL)
Adam Fordebd0d3d2018-08-20 20:43:00 -0500[diff] [blame]31#define CONFIG_SYS_NS16550_SERIAL
Derald D. Woods26fd38c2018-02-04 19:04:49 -0600[diff] [blame]32#define CONFIG_SYS_NS16550_REG_SIZE (-4)
33#endif /* !CONFIG_DM_SERIAL */
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]34#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
35 115200}
36
37/* Select serial console configuration */
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]38#ifdef CONFIG_SPL_BUILD
Adam Ford7bf27252018-07-24 18:06:04 -0500[diff] [blame]39#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
40#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]41#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]42#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]43
44/* Physical Memory Map */
45#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
46#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
47
48/*
49 * OMAP3 has 12 GP timers, they can be driven by the system clock
50 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
51 * This rate is divided by a local divisor.
52 */
53#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
54
55#define CONFIG_SYS_MONITOR_LEN (256 << 10)
56
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]57/* SPL */
Tom Rinid9f808d2014-04-03 07:52:53 -0400[diff] [blame]58
Miquel Raynald0935362019-10-03 19:50:03 +0200[diff] [blame]59#ifdef CONFIG_MTD_RAW_NAND
Tom Rinie10247f2014-04-03 15:17:15 -0400[diff] [blame]60#define CONFIG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]61#endif
62
63/* Now bring in the rest of the common code. */
Nishanth Menonad63dd72015-07-22 18:05:41 -0500[diff] [blame]64#include <configs/ti_armv7_omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]65
66#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */