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git01.mediatek.com / filogic / uboot / cb00c1846322f86d4b57282a6dedb667c26ccde3 / . / arch / m68k / cpu / mcf5445x / start.S
blob: 80eb287151e263593e4d2c90b433361cb7d01f6e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]2/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 *
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]6 * Copyright 2010-2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]8 */
9
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]10#include <common.h>
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]11#include <asm-offsets.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]12#include <config.h>
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]13#include <timestamp.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]14#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]15#include <asm/cache.h>
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]16
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]17#define _START _start
18#define _FAULT _fault
19
20#define SAVE_ALL \
21 move.w #0x2700,%sr; /* disable intrs */ \
22 subl #60,%sp; /* space for 15 regs */ \
23 moveml %d0-%d7/%a0-%a6,%sp@;
24
25#define RESTORE_ALL \
26 moveml %sp@,%d0-%d7/%a0-%a6; \
27 addl #60,%sp; /* space for 15 regs */ \
28 rte;
29
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]30#if defined(CONFIG_SERIAL_BOOT)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]31#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
32 CONFIG_SYS_INIT_RAM_ADDR)
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]33#define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]34#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
35 CONFIG_SYS_INIT_RAM_ADDR)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]36#endif
37
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]38.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]39
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]40/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]41 * Vector table. This is used for initial platform startup.
42 * These vectors are to catch any un-intended traps.
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]43 */
44_vectors:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]45#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]46
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]47INITSP: .long 0 /* Initial SP */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]48#ifdef CONFIG_CF_SBF
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]49INITPC: .long ASM_DRAMINIT /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]50#endif
51#ifdef CONFIG_SYS_NAND_BOOT
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]52INITPC: .long ASM_DRAMINIT_N /* Initial PC */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]53#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]54
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]55#else
56
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]57INITSP: .long 0 /* Initial SP */
58INITPC: .long _START /* Initial PC */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]59
60#endif
61
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]62vector02_0F:
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]65
66/* Reserved */
67vector10_17:
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]70vector18_1F:
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]72
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]73#if !defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]74
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]75/* TRAP #0 - #15 */
76vector20_2F:
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79
80/* Reserved */
81vector30_3F:
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84
85vector64_127:
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94
95vector128_191:
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104
105vector192_255:
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]114#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]115
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]116#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]117 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
118asm_sbf_img_hdr:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]119 .long 0x00000000 /* checksum, not yet implemented */
120 .long 0x00040000 /* image length */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]121 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]122
123asm_dram_init:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]124 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]125
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]126#ifdef CONFIG_SYS_NAND_BOOT
127 /* for assembly stack */
128 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
129 movec %d0, %RAMBAR1
130
131 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]132 clr.l %sp@-
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]133#endif
134
135#ifdef CONFIG_CF_SBF
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]136 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
137 movec %d0, %VBR
138
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]139 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]140 movec %d0, %RAMBAR1
141
142 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]143 move.l #0, %d0
144 move.l #(ICACHE_STATUS), %a1 /* icache */
145 move.l #(DCACHE_STATUS), %a2 /* dcache */
146 move.l %d0, (%a1)
147 move.l %d0, (%a2)
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]148
149 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]150 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]151 movec %d0, %CACR /* Invalidate cache */
152 move.l #0, %d0
153 movec %d0, %ACR0
154 movec %d0, %ACR1
155 movec %d0, %ACR2
156 movec %d0, %ACR3
157
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]158 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]159 clr.l %sp@-
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]160
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]161#ifdef CONFIG_SYS_CS0_BASE
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]162 /* Must disable global address */
163 move.l #0xFC008000, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]164 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]165 move.l #0xFC008008, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]166 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]167 move.l #0xFC008004, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]168 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]169#endif
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]170#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]171
172#ifdef CONFIG_MCF5441x
173 /* TC: enable all peripherals,
174 in the future only enable certain peripherals */
175 move.l #0xFC04002D, %a1
176
177#if defined(CONFIG_CF_SBF)
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]178 move.b #23, (%a1) /* dspi */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]179#endif
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]180#endif /* CONFIG_MCF5441x */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]181
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]182 /* mandatory board level ddr-sdram init,
183 * for both 5441x and 5445x
184 */
185 bsr sbf_dram_init
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]186
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]187#ifdef CONFIG_CF_SBF
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]188 /*
189 * DSPI Initialization
190 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
191 * a1 - dspi status
192 * a2 - dtfr
193 * a3 - drfr
194 * a4 - Dst addr
195 */
196 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]197asm_dspi_init:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]198#ifdef CONFIG_MCF5441x
199 move.l #0xEC09404E, %a1
200 move.l #0xEC09404F, %a2
201 move.b #0xFF, (%a1)
202 move.b #0x80, (%a2)
203#endif
204
205#ifdef CONFIG_MCF5445x
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]206 move.l #0xFC0A4063, %a0
207 move.b #0x7F, (%a0)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]208#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]209 /* Configure DSPI module */
210 move.l #0xFC05C000, %a0
211 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
212
213 move.l #0xFC05C00C, %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]214#ifdef CONFIG_MCF5441x
215 move.l #0x3E000016, (%a0)
216#endif
217#ifdef CONFIG_MCF5445x
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]218 move.l #0x3E000011, (%a0)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]219#endif
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]220
221 move.l #0xFC05C034, %a2 /* dtfr */
222 move.l #0xFC05C03B, %a3 /* drfr */
223
224 move.l #(ASM_SBF_IMG_HDR + 4), %a1
225 move.l (%a1)+, %d5
226 move.l (%a1), %a4
227
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]228 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
229 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]230
231 move.l #0xFC05C02C, %a1 /* dspi status */
232
233 /* Issue commands and address */
234 move.l #0x8002000B, %d2 /* Fast Read Cmd */
235 jsr asm_dspi_wr_status
236 jsr asm_dspi_rd_status
237
238 move.l #0x80020000, %d2 /* Address byte 2 */
239 jsr asm_dspi_wr_status
240 jsr asm_dspi_rd_status
241
242 move.l #0x80020000, %d2 /* Address byte 1 */
243 jsr asm_dspi_wr_status
244 jsr asm_dspi_rd_status
245
246 move.l #0x80020000, %d2 /* Address byte 0 */
247 jsr asm_dspi_wr_status
248 jsr asm_dspi_rd_status
249
250 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
251 jsr asm_dspi_wr_status
252 jsr asm_dspi_rd_status
253
254 /* Transfer serial boot header to sram */
255asm_dspi_rd_loop1:
256 move.l #0x80020000, %d2
257 jsr asm_dspi_wr_status
258 jsr asm_dspi_rd_status
259
260 move.b %d1, (%a0) /* read, copy to dst */
261
262 add.l #1, %a0 /* inc dst by 1 */
263 sub.l #1, %d4 /* dec cnt by 1 */
264 bne asm_dspi_rd_loop1
265
266 /* Transfer u-boot from serial flash to memory */
267asm_dspi_rd_loop2:
268 move.l #0x80020000, %d2
269 jsr asm_dspi_wr_status
270 jsr asm_dspi_rd_status
271
272 move.b %d1, (%a4) /* read, copy to dst */
273
274 add.l #1, %a4 /* inc dst by 1 */
275 sub.l #1, %d5 /* dec cnt by 1 */
276 bne asm_dspi_rd_loop2
277
278 move.l #0x00020000, %d2 /* Terminate */
279 jsr asm_dspi_wr_status
280 jsr asm_dspi_rd_status
281
282 /* jump to memory and execute */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200[diff] [blame]283 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]284 jmp (%a0)
285
286asm_dspi_wr_status:
287 move.l (%a1), %d0 /* status */
288 and.l #0x0000F000, %d0
289 cmp.l #0x00003000, %d0
290 bgt asm_dspi_wr_status
291
292 move.l %d2, (%a2)
293 rts
294
295asm_dspi_rd_status:
296 move.l (%a1), %d0 /* status */
297 and.l #0x000000F0, %d0
298 lsr.l #4, %d0
299 cmp.l #0, %d0
300 beq asm_dspi_rd_status
301
302 move.b (%a3), %d1
303 rts
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]304#endif /* CONFIG_CF_SBF */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]305
306#ifdef CONFIG_SYS_NAND_BOOT
307 /* copy 4 boot pages to dram as soon as possible */
308 /* each page is 996 bytes (1056 total with 60 ECC bytes */
309 move.l #0x00000000, %a1 /* src */
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]310 move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]311 move.l #0x3E0, %d0 /* sz in long */
312
313asm_boot_nand_copy:
314 move.l (%a1)+, (%a2)+
315 subq.l #1, %d0
316 bne asm_boot_nand_copy
317
318 /* jump to memory and execute */
319 move.l #(asm_nand_init), %a0
320 jmp (%a0)
321
322asm_nand_init:
323 /* exit nand boot-mode */
324 move.l #0xFC0FFF30, %a1
325 or.l #0x00000040, %d1
326 move.l %d1, (%a1)
327
328 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]329 move.l #0, %d0
330 move.l #(CACR_STATUS), %a1 /* CACR */
331 move.l #(ICACHE_STATUS), %a2 /* icache */
332 move.l #(DCACHE_STATUS), %a3 /* dcache */
333 move.l %d0, (%a1)
334 move.l %d0, (%a2)
335 move.l %d0, (%a3)
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]336
337 /* invalidate and disable cache */
338 move.l #0x01004100, %d0 /* Invalidate cache cmd */
339 movec %d0, %CACR /* Invalidate cache */
340 move.l #0, %d0
341 movec %d0, %ACR0
342 movec %d0, %ACR1
343 movec %d0, %ACR2
344 movec %d0, %ACR3
345
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]346#ifdef CONFIG_SYS_CS0_BASE
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]347 /* Must disable global address */
348 move.l #0xFC008000, %a1
349 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
350 move.l #0xFC008008, %a1
351 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
352 move.l #0xFC008004, %a1
353 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
Angelo Dureghello7211b922017-05-15 00:17:48 +0200[diff] [blame]354#endif
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]355
356 /* NAND port configuration */
357 move.l #0xEC094048, %a1
358 move.b #0xFD, (%a1)+
359 move.b #0x5F, (%a1)+
360 move.b #0x04, (%a1)+
361
362 /* reset nand */
363 move.l #0xFC0FFF38, %a1 /* isr */
364 move.l #0x000e0000, (%a1)
365 move.l #0xFC0FFF08, %a2
366 move.l #0x00000000, (%a2)+ /* car */
367 move.l #0x11000000, (%a2)+ /* rar */
368 move.l #0x00000000, (%a2)+ /* rpt */
369 move.l #0x00000000, (%a2)+ /* rai */
370 move.l #0xFC0FFF2c, %a2 /* cfg */
371 move.l #0x00000000, (%a2)+ /* secsz */
372 move.l #0x000e0681, (%a2)+
373 move.l #0xFC0FFF04, %a2 /* cmd2 */
374 move.l #0xFF404001, (%a2)
375 move.l #0x000e0000, (%a1)
376
377 move.l #0x2000, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]378 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]379
380 /* setup nand */
381 move.l #0xFC0FFF00, %a1
382 move.l #0x30700000, (%a1)+ /* cmd1 */
383 move.l #0x007EF000, (%a1)+ /* cmd2 */
384
385 move.l #0xFC0FFF2C, %a1
386 move.l #0x00000841, (%a1)+ /* secsz */
387 move.l #0x000e0681, (%a1)+ /* cfg */
388
389 move.l #100, %d4 /* 100 pages ~200KB */
390 move.l #4, %d2 /* start at 4 */
391 move.l #0xFC0FFF04, %a0 /* cmd2 */
392 move.l #0xFC0FFF0C, %a1 /* rar */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]393 move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]394
395asm_nand_read:
396 move.l #0x11000000, %d0 /* rar */
397 or.l %d2, %d0
398 move.l %d0, (%a1)
399 add.l #1, %d2
400
401 move.l (%a0), %d0 /* cmd2 */
402 or.l #1, %d0
403 move.l %d0, (%a0)
404
405 move.l #0x200, %d1
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]406 bsr asm_delay
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]407
408asm_nand_chk_status:
409 move.l #0xFC0FFF38, %a4 /* isr */
410 move.l (%a4), %d0
411 and.l #0x40000000, %d0
412 tst.l %d0
413 beq asm_nand_chk_status
414
415 move.l #0xFC0FFF38, %a4 /* isr */
416 move.l (%a4), %d0
417 or.l #0x000E0000, %d0
418 move.l %d0, (%a4)
419
420 move.l #0x200, %d3
421 move.l #0xFC0FC000, %a3 /* buf 1 */
422asm_nand_copy:
423 move.l (%a3)+, (%a2)+
424 subq.l #1, %d3
425 bgt asm_nand_copy
426
427 subq.l #1, %d4
428 bgt asm_nand_read
429
430 /* jump to memory and execute */
Masahiro Yamada03390c62015-12-11 12:22:25 +0900[diff] [blame]431 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]432 jmp (%a0)
433
434#endif /* CONFIG_SYS_NAND_BOOT */
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]435
Angelo Dureghello89ae64c2017-05-14 21:42:27 +0200[diff] [blame]436.globl asm_delay
TsiChung Liewb78c9882009-06-11 15:39:57 +0000[diff] [blame]437asm_delay:
438 nop
439 subq.l #1, %d1
440 bne asm_delay
441 rts
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]442#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]443
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]444.text
TsiChung Liew23cf8fd2008-07-23 20:38:53 -0500[diff] [blame]445 . = 0x400
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]446.globl _start
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]447_start:
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]448#if !defined(CONFIG_SERIAL_BOOT)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]449 nop
450 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]451 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]452
453 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]454 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]455 movec %d0, %VBR
456
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]457 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew0573a7a2007-11-07 18:00:54 -0600[diff] [blame]458 movec %d0, %RAMBAR1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]459
460 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]461 move.l #0, %d0
462 move.l #(ICACHE_STATUS), %a1 /* icache */
463 move.l #(DCACHE_STATUS), %a2 /* dcache */
464 move.l %d0, (%a1)
465 move.l %d0, (%a2)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]466
467 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]468 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]469 movec %d0, %CACR /* Invalidate cache */
470 move.l #0, %d0
471 movec %d0, %ACR0
472 movec %d0, %ACR1
473 movec %d0, %ACR2
474 movec %d0, %ACR3
Alison Wangfdc2fb12012-10-18 19:25:51 +0000[diff] [blame]475#else
476 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
477 movec %d0, %RAMBAR1
478#endif
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]479
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]480 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]481 move.l #__got_start, %a5
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]482
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]483 /* setup stack initially on top of internal static ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]484 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]485
486 /*
487 * if configured, malloc_f arena will be reserved first,
488 * then (and always) gd struct space will be reserved
489 */
490 move.l %sp, -(%sp)
491 move.l #board_init_f_alloc_reserve, %a1
492 jsr (%a1)
493
494 /* update stack and frame-pointers */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]495 move.l %d0, %sp
496 move.l %sp, %fp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]497
498 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]499 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]500 move.l #board_init_f_init_reserve, %a1
501 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]502
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]503 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]504 move.l #cpu_init_f, %a1
505 jsr (%a1)
506
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]507 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]508 clr.l %sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]509 move.l #board_init_f, %a1
510 jsr (%a1)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]511
512 /* board_init_f() does not return */
513
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]514/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]515
516/*
Simon Glass284f71b2019-12-28 10:44:45 -0700[diff] [blame]517 * void relocate_code(addr_sp, gd, addr_moni)
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]518 *
519 * This "function" does not return, instead it continues in RAM
520 * after relocating the monitor code.
521 *
522 * r3 = dest
523 * r4 = src
524 * r5 = length in bytes
525 * r6 = cachelinesize
526 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]527.globl relocate_code
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]528relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]529 link.w %a6,#0
530 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]531
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]532 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
533 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]534
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]535 move.l #CONFIG_SYS_MONITOR_BASE, %a1
536 move.l #__init_end, %a2
537 move.l %a0, %a3
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]538
539 /* copy the code to RAM */
5401:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]541 move.l (%a1)+, (%a3)+
542 cmp.l %a1,%a2
543 bgt.s 1b
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]544
545/*
546 * We are done. Do not return, instead branch to second part of board
547 * initialization, now running from RAM.
548 */
549 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]550 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]551 jmp (%a1)
552
553in_ram:
554
555clear_bss:
556 /*
557 * Now clear BSS segment
558 */
559 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]560 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]561 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]562 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]5636:
564 clr.l (%a1)+
565 cmp.l %a1,%d1
566 bgt.s 6b
567
568 /*
569 * fix got table in RAM
570 */
571 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]572 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]573 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]574
575 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]576 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]577
5787:
579 move.l (%a1),%d1
580 sub.l #_start,%d1
581 add.l %a0,%d1
582 move.l %d1,(%a1)+
583 cmp.l %a2, %a1
584 bne 7b
585
586 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]587 move.l %a0, %a1
588 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]589
590 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]591 move.l %a0,-(%sp) /* dest_addr */
592 move.l %d0,-(%sp) /* gd */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]593 jsr (%a1)
594
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]595/******************************************************************************/
596
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]597/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]598.globl _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]599_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]600 bra _fault
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]601
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]602.globl _exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]603_exc_handler:
604 SAVE_ALL
605 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]606 bsr exc_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]607 addql #4,%sp
608 RESTORE_ALL
609
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]610.globl _int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]611_int_handler:
612 SAVE_ALL
613 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]614 bsr int_handler
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]615 addql #4,%sp
616 RESTORE_ALL
617
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]618/******************************************************************************/
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]619
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]620.globl version_string
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]621version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]622.ascii U_BOOT_VERSION_STRING, "\0"
623.align 4