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git01.mediatek.com / filogic / uboot / c934e5e2811ac645866a003c12c44d530589a51d / . / drivers / ddr / fsl / Kconfig
blob: 22400a9b8bab5d9db05a5a99d4b13349dc0b8c5e [file] [log] [blame]
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
Tom Rinie5404982021-05-14 21:34:26 -0400[diff] [blame]5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
6 Layerscape SoCs (such as ls2080a).
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
Tom Rini44b027d2022-06-15 12:03:47 -0400[diff] [blame]13config SYS_FSL_DDR_EMU
14 bool
15 help
16 Specify emulator support for DDR. Some DDR features such as deskew
17 training are not available.
18
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]19if SYS_FSL_DDR || SYS_FSL_MMDC
20
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]21config SYS_FSL_DDR_BE
22 bool
23 help
24 Access DDR registers in big-endian
25
26config SYS_FSL_DDR_LE
27 bool
28 help
29 Access DDR registers in little-endian
30
Rajesh Bhagatba2414f2019-02-01 05:22:01 +0000[diff] [blame]31config FSL_DDR_BIST
32 bool
33
34config FSL_DDR_INTERACTIVE
35 bool
36
37config FSL_DDR_SYNC_REFRESH
38 bool
39
40config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
41 bool
42
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]43menu "Freescale DDR controllers"
44 depends on SYS_FSL_DDR
45
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]46config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]47 int "Maximum DDR controllers"
48 default 3 if ARCH_LS2080A || \
49 ARCH_T4240
50 default 2 if ARCH_B4860 || \
51 ARCH_BSC9132 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]52 ARCH_P4080 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]53 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]54 ARCH_LX2160A || \
Tom Rinia7ffa3d2021-05-23 10:58:05 -0400[diff] [blame]55 ARCH_LX2162A
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]56 default 1
57
Tom Rini56184602022-02-25 11:19:53 -0500[diff] [blame]58config CHIP_SELECTS_PER_CTRL
59 int "Number of chip selects per controller"
60 default 4
61
Tom Rini3210bdc2022-03-30 18:07:31 -0400[diff] [blame]62config DIMM_SLOTS_PER_CTLR
63 int "Number of DIMM slots per controller"
64 default 1
65
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]66config SYS_FSL_DDR_VER
67 int
68 default 50 if SYS_FSL_DDR_VER_50
69 default 47 if SYS_FSL_DDR_VER_47
70 default 46 if SYS_FSL_DDR_VER_46
71 default 44 if SYS_FSL_DDR_VER_44
72
73config SYS_FSL_DDR_VER_50
74 bool
75
76config SYS_FSL_DDR_VER_47
77 bool
78
79config SYS_FSL_DDR_VER_46
80 bool
81
82config SYS_FSL_DDR_VER_44
83 bool
84
85config SYS_FSL_DDRC_GEN1
86 bool
87 help
88 Enable Freescale DDR controller.
89
90config SYS_FSL_DDRC_GEN2
91 bool
92 depends on !MPC86xx
93 help
94 Enable Freescale DDR2 controller.
95
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]96config SYS_FSL_DDRC_GEN3
97 bool
98 depends on PPC
99 help
100 Enable Freescale DDR3 controller for PowerPC SoCs.
101
102config SYS_FSL_DDRC_ARM_GEN3
103 bool
104 depends on ARM
105 help
106 Enable Freescale DDR3 controller for ARM SoCs.
107
108config SYS_FSL_DDRC_GEN4
109 bool
110 help
111 Enable Freescale DDR4 controller.
112
113config SYS_FSL_HAS_DDR4
114 bool
115
116config SYS_FSL_HAS_DDR3
117 bool
118
119config SYS_FSL_HAS_DDR2
120 bool
121
122config SYS_FSL_HAS_DDR1
123 bool
124
125choice
126 prompt "DDR technology"
127 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
128 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
129 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
130 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
131
132config SYS_FSL_DDR4
133 bool "Freescale DDR4 controller"
134 depends on SYS_FSL_HAS_DDR4
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]135 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]136 select SYS_FSL_DDRC_GEN4
137
138config SYS_FSL_DDR3
139 bool "Freescale DDR3 controller"
140 depends on SYS_FSL_HAS_DDR3
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]141 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]142 select SYS_FSL_DDRC_GEN3 if PPC
143 select SYS_FSL_DDRC_ARM_GEN3 if ARM
144
145config SYS_FSL_DDR2
146 bool "Freescale DDR2 controller"
147 depends on SYS_FSL_HAS_DDR2
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]148 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]149 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]150
151config SYS_FSL_DDR1
152 bool "Freescale DDR1 controller"
153 depends on SYS_FSL_HAS_DDR1
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]154 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]155 select SYS_FSL_DDRC_GEN1
156
157endchoice
158
159endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]160
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]161config FSL_DMA
162 def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
163
164config DDR_ECC
165 bool "ECC DDR memory support"
166
167config DDR_ECC_CMD
168 bool "Access the ECC features of the memory controller"
169 depends on DDR_ECC && MPC83xx
170 default y
171
172config ECC_INIT_VIA_DDRCONTROLLER
173 bool "DDR Memory controller initializes memory."
174 help
175 Use the DDR controller to auto initialize memory. If not enabled,
176 the DMA controller is responsible for doing this.
177
Tom Rini8e99f7d2022-06-15 12:03:55 -0400[diff] [blame]178config SYS_DDR_RAW_TIMING
179 bool "Get DDR timing information from something other than SPD"
180 help
181 This is common with soldered DDR chips onboard without SPD. DDR raw
182 timing parameters are extracted from datasheet and hard-coded into
183 header files or board specific files.
184
Tom Rinic934e5e2022-07-23 13:05:12 -0400[diff] [blame^]185config SYS_FSL_DDR_INTLV_256B
186 bool "Enforce 256-byte interleave"
187 help
188 DDR controller interleaving on 256-byte. This is a special
189 interleaving mode, handled by Dickens for Freescale layerscape SoCs
190 with ARM core.
191
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]192endif
193
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]194menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
195 depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
196
197config SYS_BR0_PRELIM_BOOL
198 bool "Define Bank 0"
199
200config SYS_BR0_PRELIM
201 hex "Preliminary value for BR0"
202 depends on SYS_BR0_PRELIM_BOOL
203
204config SYS_OR0_PRELIM
205 hex "Preliminary value for OR0"
206 depends on SYS_BR0_PRELIM_BOOL
207
208config SYS_BR1_PRELIM_BOOL
209 bool "Define Bank 1"
210
211config SYS_BR1_PRELIM
212 hex "Preliminary value for BR1"
213 depends on SYS_BR1_PRELIM_BOOL
214
215config SYS_OR1_PRELIM
216 hex "Preliminary value for OR1"
217 depends on SYS_BR1_PRELIM_BOOL
218
219config SYS_BR2_PRELIM_BOOL
220 bool "Define Bank 2"
221
222config SYS_BR2_PRELIM
223 hex "Preliminary value for BR2"
224 depends on SYS_BR2_PRELIM_BOOL
225
226config SYS_OR2_PRELIM
227 hex "Preliminary value for OR2"
228 depends on SYS_BR2_PRELIM_BOOL
229
230config SYS_BR3_PRELIM_BOOL
231 bool "Define Bank 3"
232
233config SYS_BR3_PRELIM
234 hex "Preliminary value for BR3"
235 depends on SYS_BR3_PRELIM_BOOL
236
237config SYS_OR3_PRELIM
238 hex "Preliminary value for OR3"
239 depends on SYS_BR3_PRELIM_BOOL
240
241config SYS_BR4_PRELIM_BOOL
242 bool "Define Bank 4"
243
244config SYS_BR4_PRELIM
245 hex "Preliminary value for BR4"
246 depends on SYS_BR4_PRELIM_BOOL
247
248config SYS_OR4_PRELIM
249 hex "Preliminary value for OR4"
250 depends on SYS_BR4_PRELIM_BOOL
251
252config SYS_BR5_PRELIM_BOOL
253 bool "Define Bank 5"
254
255config SYS_BR5_PRELIM
256 hex "Preliminary value for BR5"
257 depends on SYS_BR5_PRELIM_BOOL
258
259config SYS_OR5_PRELIM
260 hex "Preliminary value for OR5"
261 depends on SYS_BR5_PRELIM_BOOL
262
263config SYS_BR6_PRELIM_BOOL
264 bool "Define Bank 6"
265
266config SYS_BR6_PRELIM
267 hex "Preliminary value for BR6"
268 depends on SYS_BR6_PRELIM_BOOL
269
270config SYS_OR6_PRELIM
271 hex "Preliminary value for OR6"
272 depends on SYS_BR6_PRELIM_BOOL
273
274config SYS_BR7_PRELIM_BOOL
275 bool "Define Bank 7"
276
277config SYS_BR7_PRELIM
278 hex "Preliminary value for BR7"
279 depends on SYS_BR7_PRELIM_BOOL
280
281config SYS_OR7_PRELIM
282 hex "Preliminary value for OR7"
283 depends on SYS_BR7_PRELIM_BOOL
284endmenu
285
Tom Rinif8f6b322022-05-21 14:44:28 -0400[diff] [blame]286if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
287 TARGET_P1020RDB_PD || TARGET_P2020RDB
288
289config COMMON_INIT_DDR
290 bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
291
292config SPL_COMMON_INIT_DDR
293 bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
294
295config TPL_COMMON_INIT_DDR
296 bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
297
298endif
299
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]300config SYS_FSL_ERRATUM_A008378
301 bool
302
Joakim Tjernlund477602c2019-11-20 17:07:34 +0100[diff] [blame]303config SYS_FSL_ERRATUM_A008109
304 bool
305
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]306config SYS_FSL_ERRATUM_A008511
307 bool
308
309config SYS_FSL_ERRATUM_A009663
310 bool
311
312config SYS_FSL_ERRATUM_A009801
313 bool
314
315config SYS_FSL_ERRATUM_A009803
316 bool
317
318config SYS_FSL_ERRATUM_A009942
319 bool
320
321config SYS_FSL_ERRATUM_A010165
322 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]323
324config SYS_FSL_ERRATUM_NMG_DDR120
325 bool
326
327config SYS_FSL_ERRATUM_DDR_115
328 bool
329
330config SYS_FSL_ERRATUM_DDR111_DDR134
331 bool
332
333config SYS_FSL_ERRATUM_DDR_A003
334 bool
335
336config SYS_FSL_ERRATUM_DDR_A003474
337 bool