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git01.mediatek.com / filogic / uboot / a7ffa3d471c645c39c6ce8d3dcc5a8b38200ef8b / . / drivers / ddr / fsl / Kconfig
blob: 8246f627982c1ff27ad5c011ed2192e2bbd03dbe [file] [log] [blame]
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
Tom Rinie5404982021-05-14 21:34:26 -0400[diff] [blame]5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
6 Layerscape SoCs (such as ls2080a).
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
13config SYS_FSL_DDR_BE
14 bool
15 help
16 Access DDR registers in big-endian
17
18config SYS_FSL_DDR_LE
19 bool
20 help
21 Access DDR registers in little-endian
22
Rajesh Bhagatba2414f2019-02-01 05:22:01 +0000[diff] [blame]23config FSL_DDR_BIST
24 bool
25
26config FSL_DDR_INTERACTIVE
27 bool
28
29config FSL_DDR_SYNC_REFRESH
30 bool
31
32config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
33 bool
34
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]35menu "Freescale DDR controllers"
36 depends on SYS_FSL_DDR
37
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]38config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]39 int "Maximum DDR controllers"
40 default 3 if ARCH_LS2080A || \
41 ARCH_T4240
42 default 2 if ARCH_B4860 || \
43 ARCH_BSC9132 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]44 ARCH_P4080 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]45 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]46 ARCH_LX2160A || \
Tom Rinia7ffa3d2021-05-23 10:58:05 -0400[diff] [blame^]47 ARCH_LX2162A
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]48 default 1
49
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]50config SYS_FSL_DDR_VER
51 int
52 default 50 if SYS_FSL_DDR_VER_50
53 default 47 if SYS_FSL_DDR_VER_47
54 default 46 if SYS_FSL_DDR_VER_46
55 default 44 if SYS_FSL_DDR_VER_44
56
57config SYS_FSL_DDR_VER_50
58 bool
59
60config SYS_FSL_DDR_VER_47
61 bool
62
63config SYS_FSL_DDR_VER_46
64 bool
65
66config SYS_FSL_DDR_VER_44
67 bool
68
69config SYS_FSL_DDRC_GEN1
70 bool
71 help
72 Enable Freescale DDR controller.
73
74config SYS_FSL_DDRC_GEN2
75 bool
76 depends on !MPC86xx
77 help
78 Enable Freescale DDR2 controller.
79
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]80config SYS_FSL_DDRC_GEN3
81 bool
82 depends on PPC
83 help
84 Enable Freescale DDR3 controller for PowerPC SoCs.
85
86config SYS_FSL_DDRC_ARM_GEN3
87 bool
88 depends on ARM
89 help
90 Enable Freescale DDR3 controller for ARM SoCs.
91
92config SYS_FSL_DDRC_GEN4
93 bool
94 help
95 Enable Freescale DDR4 controller.
96
97config SYS_FSL_HAS_DDR4
98 bool
99
100config SYS_FSL_HAS_DDR3
101 bool
102
103config SYS_FSL_HAS_DDR2
104 bool
105
106config SYS_FSL_HAS_DDR1
107 bool
108
109choice
110 prompt "DDR technology"
111 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
112 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
113 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
114 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
115
116config SYS_FSL_DDR4
117 bool "Freescale DDR4 controller"
118 depends on SYS_FSL_HAS_DDR4
119 select SYS_FSL_DDRC_GEN4
120
121config SYS_FSL_DDR3
122 bool "Freescale DDR3 controller"
123 depends on SYS_FSL_HAS_DDR3
124 select SYS_FSL_DDRC_GEN3 if PPC
125 select SYS_FSL_DDRC_ARM_GEN3 if ARM
126
127config SYS_FSL_DDR2
128 bool "Freescale DDR2 controller"
129 depends on SYS_FSL_HAS_DDR2
130 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]131
132config SYS_FSL_DDR1
133 bool "Freescale DDR1 controller"
134 depends on SYS_FSL_HAS_DDR1
135 select SYS_FSL_DDRC_GEN1
136
137endchoice
138
139endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]140
141config SYS_FSL_ERRATUM_A008378
142 bool
143
Joakim Tjernlund477602c2019-11-20 17:07:34 +0100[diff] [blame]144config SYS_FSL_ERRATUM_A008109
145 bool
146
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]147config SYS_FSL_ERRATUM_A008511
148 bool
149
150config SYS_FSL_ERRATUM_A009663
151 bool
152
153config SYS_FSL_ERRATUM_A009801
154 bool
155
156config SYS_FSL_ERRATUM_A009803
157 bool
158
159config SYS_FSL_ERRATUM_A009942
160 bool
161
162config SYS_FSL_ERRATUM_A010165
163 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]164
165config SYS_FSL_ERRATUM_NMG_DDR120
166 bool
167
168config SYS_FSL_ERRATUM_DDR_115
169 bool
170
171config SYS_FSL_ERRATUM_DDR111_DDR134
172 bool
173
174config SYS_FSL_ERRATUM_DDR_A003
175 bool
176
177config SYS_FSL_ERRATUM_DDR_A003474
178 bool