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git01.mediatek.com / filogic / uboot / e540498b76d4e869c2327f4ae90fcd7fc96c5801 / . / drivers / ddr / fsl / Kconfig
blob: e6a51f560978e4fd52daf547b515601f6c7ce623 [file] [log] [blame]
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
Tom Rinie5404982021-05-14 21:34:26 -0400[diff] [blame^]5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
6 Layerscape SoCs (such as ls2080a).
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
13config SYS_FSL_DDR_BE
14 bool
15 help
16 Access DDR registers in big-endian
17
18config SYS_FSL_DDR_LE
19 bool
20 help
21 Access DDR registers in little-endian
22
Rajesh Bhagatba2414f2019-02-01 05:22:01 +0000[diff] [blame]23config FSL_DDR_BIST
24 bool
25
26config FSL_DDR_INTERACTIVE
27 bool
28
29config FSL_DDR_SYNC_REFRESH
30 bool
31
32config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
33 bool
34
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]35menu "Freescale DDR controllers"
36 depends on SYS_FSL_DDR
37
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]38config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]39 int "Maximum DDR controllers"
40 default 3 if ARCH_LS2080A || \
41 ARCH_T4240
42 default 2 if ARCH_B4860 || \
43 ARCH_BSC9132 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]44 ARCH_P4080 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]45 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]46 ARCH_LX2160A || \
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530[diff] [blame]47 ARCH_LX2162A || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]48 ARCH_T4160
49 default 1
50
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]51config SYS_FSL_DDR_VER
52 int
53 default 50 if SYS_FSL_DDR_VER_50
54 default 47 if SYS_FSL_DDR_VER_47
55 default 46 if SYS_FSL_DDR_VER_46
56 default 44 if SYS_FSL_DDR_VER_44
57
58config SYS_FSL_DDR_VER_50
59 bool
60
61config SYS_FSL_DDR_VER_47
62 bool
63
64config SYS_FSL_DDR_VER_46
65 bool
66
67config SYS_FSL_DDR_VER_44
68 bool
69
70config SYS_FSL_DDRC_GEN1
71 bool
72 help
73 Enable Freescale DDR controller.
74
75config SYS_FSL_DDRC_GEN2
76 bool
77 depends on !MPC86xx
78 help
79 Enable Freescale DDR2 controller.
80
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]81config SYS_FSL_DDRC_GEN3
82 bool
83 depends on PPC
84 help
85 Enable Freescale DDR3 controller for PowerPC SoCs.
86
87config SYS_FSL_DDRC_ARM_GEN3
88 bool
89 depends on ARM
90 help
91 Enable Freescale DDR3 controller for ARM SoCs.
92
93config SYS_FSL_DDRC_GEN4
94 bool
95 help
96 Enable Freescale DDR4 controller.
97
98config SYS_FSL_HAS_DDR4
99 bool
100
101config SYS_FSL_HAS_DDR3
102 bool
103
104config SYS_FSL_HAS_DDR2
105 bool
106
107config SYS_FSL_HAS_DDR1
108 bool
109
110choice
111 prompt "DDR technology"
112 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
113 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
114 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
115 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
116
117config SYS_FSL_DDR4
118 bool "Freescale DDR4 controller"
119 depends on SYS_FSL_HAS_DDR4
120 select SYS_FSL_DDRC_GEN4
121
122config SYS_FSL_DDR3
123 bool "Freescale DDR3 controller"
124 depends on SYS_FSL_HAS_DDR3
125 select SYS_FSL_DDRC_GEN3 if PPC
126 select SYS_FSL_DDRC_ARM_GEN3 if ARM
127
128config SYS_FSL_DDR2
129 bool "Freescale DDR2 controller"
130 depends on SYS_FSL_HAS_DDR2
131 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]132
133config SYS_FSL_DDR1
134 bool "Freescale DDR1 controller"
135 depends on SYS_FSL_HAS_DDR1
136 select SYS_FSL_DDRC_GEN1
137
138endchoice
139
140endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]141
142config SYS_FSL_ERRATUM_A008378
143 bool
144
Joakim Tjernlund477602c2019-11-20 17:07:34 +0100[diff] [blame]145config SYS_FSL_ERRATUM_A008109
146 bool
147
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]148config SYS_FSL_ERRATUM_A008511
149 bool
150
151config SYS_FSL_ERRATUM_A009663
152 bool
153
154config SYS_FSL_ERRATUM_A009801
155 bool
156
157config SYS_FSL_ERRATUM_A009803
158 bool
159
160config SYS_FSL_ERRATUM_A009942
161 bool
162
163config SYS_FSL_ERRATUM_A010165
164 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]165
166config SYS_FSL_ERRATUM_NMG_DDR120
167 bool
168
169config SYS_FSL_ERRATUM_DDR_115
170 bool
171
172config SYS_FSL_ERRATUM_DDR111_DDR134
173 bool
174
175config SYS_FSL_ERRATUM_DDR_A003
176 bool
177
178config SYS_FSL_ERRATUM_DDR_A003474
179 bool