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git01.mediatek.com / filogic / uboot / ccb5d5d65b190731587d7a7fb49049b620fa4311 / . / drivers / ddr / fsl / Kconfig
blob: 5f62489a90f6ab71d121252e431589911a02cebd [file] [log] [blame]
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
5 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
6 based Layerscape SoCs (such as ls2080a).
7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
13config SYS_FSL_DDR_BE
14 bool
15 help
16 Access DDR registers in big-endian
17
18config SYS_FSL_DDR_LE
19 bool
20 help
21 Access DDR registers in little-endian
22
Rajesh Bhagatba2414f2019-02-01 05:22:01 +0000[diff] [blame]23config FSL_DDR_BIST
24 bool
25
26config FSL_DDR_INTERACTIVE
27 bool
28
29config FSL_DDR_SYNC_REFRESH
30 bool
31
32config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
33 bool
34
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]35menu "Freescale DDR controllers"
36 depends on SYS_FSL_DDR
37
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]38config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]39 int "Maximum DDR controllers"
40 default 3 if ARCH_LS2080A || \
41 ARCH_T4240
42 default 2 if ARCH_B4860 || \
43 ARCH_BSC9132 || \
44 ARCH_MPC8572 || \
45 ARCH_MPC8641 || \
46 ARCH_P4080 || \
47 ARCH_P5020 || \
48 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]49 ARCH_LX2160A || \
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530[diff] [blame^]50 ARCH_LX2162A || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]51 ARCH_T4160
52 default 1
53
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]54config SYS_FSL_DDR_VER
55 int
56 default 50 if SYS_FSL_DDR_VER_50
57 default 47 if SYS_FSL_DDR_VER_47
58 default 46 if SYS_FSL_DDR_VER_46
59 default 44 if SYS_FSL_DDR_VER_44
60
61config SYS_FSL_DDR_VER_50
62 bool
63
64config SYS_FSL_DDR_VER_47
65 bool
66
67config SYS_FSL_DDR_VER_46
68 bool
69
70config SYS_FSL_DDR_VER_44
71 bool
72
73config SYS_FSL_DDRC_GEN1
74 bool
75 help
76 Enable Freescale DDR controller.
77
78config SYS_FSL_DDRC_GEN2
79 bool
80 depends on !MPC86xx
81 help
82 Enable Freescale DDR2 controller.
83
84config SYS_FSL_DDRC_86XX_GEN2
85 bool
86 depends on MPC86xx
87 help
88 Enable Freescale DDR2 controller for MPC86xx SoCs.
89
90config SYS_FSL_DDRC_GEN3
91 bool
92 depends on PPC
93 help
94 Enable Freescale DDR3 controller for PowerPC SoCs.
95
96config SYS_FSL_DDRC_ARM_GEN3
97 bool
98 depends on ARM
99 help
100 Enable Freescale DDR3 controller for ARM SoCs.
101
102config SYS_FSL_DDRC_GEN4
103 bool
104 help
105 Enable Freescale DDR4 controller.
106
107config SYS_FSL_HAS_DDR4
108 bool
109
110config SYS_FSL_HAS_DDR3
111 bool
112
113config SYS_FSL_HAS_DDR2
114 bool
115
116config SYS_FSL_HAS_DDR1
117 bool
118
119choice
120 prompt "DDR technology"
121 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
122 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
123 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
124 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
125
126config SYS_FSL_DDR4
127 bool "Freescale DDR4 controller"
128 depends on SYS_FSL_HAS_DDR4
129 select SYS_FSL_DDRC_GEN4
130
131config SYS_FSL_DDR3
132 bool "Freescale DDR3 controller"
133 depends on SYS_FSL_HAS_DDR3
134 select SYS_FSL_DDRC_GEN3 if PPC
135 select SYS_FSL_DDRC_ARM_GEN3 if ARM
136
137config SYS_FSL_DDR2
138 bool "Freescale DDR2 controller"
139 depends on SYS_FSL_HAS_DDR2
140 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
141 select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
142
143config SYS_FSL_DDR1
144 bool "Freescale DDR1 controller"
145 depends on SYS_FSL_HAS_DDR1
146 select SYS_FSL_DDRC_GEN1
147
148endchoice
149
150endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]151
152config SYS_FSL_ERRATUM_A008378
153 bool
154
Joakim Tjernlund477602c2019-11-20 17:07:34 +0100[diff] [blame]155config SYS_FSL_ERRATUM_A008109
156 bool
157
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]158config SYS_FSL_ERRATUM_A008511
159 bool
160
161config SYS_FSL_ERRATUM_A009663
162 bool
163
164config SYS_FSL_ERRATUM_A009801
165 bool
166
167config SYS_FSL_ERRATUM_A009803
168 bool
169
170config SYS_FSL_ERRATUM_A009942
171 bool
172
173config SYS_FSL_ERRATUM_A010165
174 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]175
176config SYS_FSL_ERRATUM_NMG_DDR120
177 bool
178
179config SYS_FSL_ERRATUM_DDR_115
180 bool
181
182config SYS_FSL_ERRATUM_DDR111_DDR134
183 bool
184
185config SYS_FSL_ERRATUM_DDR_A003
186 bool
187
188config SYS_FSL_ERRATUM_DDR_A003474
189 bool