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git01.mediatek.com / filogic / uboot / e1ef7088b4c602d50edd0ea02766b2382b11c214 / . / drivers / ddr / fsl / Kconfig
blob: 890e62190b1a81b1b698cc5d4fceee45b6e49184 [file] [log] [blame]
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
5 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
6 based Layerscape SoCs (such as ls2080a).
7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
13config SYS_FSL_DDR_BE
14 bool
15 help
16 Access DDR registers in big-endian
17
18config SYS_FSL_DDR_LE
19 bool
20 help
21 Access DDR registers in little-endian
22
Rajesh Bhagatba2414f2019-02-01 05:22:01 +0000[diff] [blame]23config FSL_DDR_BIST
24 bool
25
26config FSL_DDR_INTERACTIVE
27 bool
28
29config FSL_DDR_SYNC_REFRESH
30 bool
31
32config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
33 bool
34
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]35menu "Freescale DDR controllers"
36 depends on SYS_FSL_DDR
37
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]38config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]39 int "Maximum DDR controllers"
40 default 3 if ARCH_LS2080A || \
41 ARCH_T4240
42 default 2 if ARCH_B4860 || \
43 ARCH_BSC9132 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]44 ARCH_MPC8641 || \
45 ARCH_P4080 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]46 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]47 ARCH_LX2160A || \
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530[diff] [blame]48 ARCH_LX2162A || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]49 ARCH_T4160
50 default 1
51
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]52config SYS_FSL_DDR_VER
53 int
54 default 50 if SYS_FSL_DDR_VER_50
55 default 47 if SYS_FSL_DDR_VER_47
56 default 46 if SYS_FSL_DDR_VER_46
57 default 44 if SYS_FSL_DDR_VER_44
58
59config SYS_FSL_DDR_VER_50
60 bool
61
62config SYS_FSL_DDR_VER_47
63 bool
64
65config SYS_FSL_DDR_VER_46
66 bool
67
68config SYS_FSL_DDR_VER_44
69 bool
70
71config SYS_FSL_DDRC_GEN1
72 bool
73 help
74 Enable Freescale DDR controller.
75
76config SYS_FSL_DDRC_GEN2
77 bool
78 depends on !MPC86xx
79 help
80 Enable Freescale DDR2 controller.
81
82config SYS_FSL_DDRC_86XX_GEN2
83 bool
84 depends on MPC86xx
85 help
86 Enable Freescale DDR2 controller for MPC86xx SoCs.
87
88config SYS_FSL_DDRC_GEN3
89 bool
90 depends on PPC
91 help
92 Enable Freescale DDR3 controller for PowerPC SoCs.
93
94config SYS_FSL_DDRC_ARM_GEN3
95 bool
96 depends on ARM
97 help
98 Enable Freescale DDR3 controller for ARM SoCs.
99
100config SYS_FSL_DDRC_GEN4
101 bool
102 help
103 Enable Freescale DDR4 controller.
104
105config SYS_FSL_HAS_DDR4
106 bool
107
108config SYS_FSL_HAS_DDR3
109 bool
110
111config SYS_FSL_HAS_DDR2
112 bool
113
114config SYS_FSL_HAS_DDR1
115 bool
116
117choice
118 prompt "DDR technology"
119 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
120 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
121 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
122 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
123
124config SYS_FSL_DDR4
125 bool "Freescale DDR4 controller"
126 depends on SYS_FSL_HAS_DDR4
127 select SYS_FSL_DDRC_GEN4
128
129config SYS_FSL_DDR3
130 bool "Freescale DDR3 controller"
131 depends on SYS_FSL_HAS_DDR3
132 select SYS_FSL_DDRC_GEN3 if PPC
133 select SYS_FSL_DDRC_ARM_GEN3 if ARM
134
135config SYS_FSL_DDR2
136 bool "Freescale DDR2 controller"
137 depends on SYS_FSL_HAS_DDR2
138 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
139 select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
140
141config SYS_FSL_DDR1
142 bool "Freescale DDR1 controller"
143 depends on SYS_FSL_HAS_DDR1
144 select SYS_FSL_DDRC_GEN1
145
146endchoice
147
148endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]149
150config SYS_FSL_ERRATUM_A008378
151 bool
152
Joakim Tjernlund477602c2019-11-20 17:07:34 +0100[diff] [blame]153config SYS_FSL_ERRATUM_A008109
154 bool
155
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]156config SYS_FSL_ERRATUM_A008511
157 bool
158
159config SYS_FSL_ERRATUM_A009663
160 bool
161
162config SYS_FSL_ERRATUM_A009801
163 bool
164
165config SYS_FSL_ERRATUM_A009803
166 bool
167
168config SYS_FSL_ERRATUM_A009942
169 bool
170
171config SYS_FSL_ERRATUM_A010165
172 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]173
174config SYS_FSL_ERRATUM_NMG_DDR120
175 bool
176
177config SYS_FSL_ERRATUM_DDR_115
178 bool
179
180config SYS_FSL_ERRATUM_DDR111_DDR134
181 bool
182
183config SYS_FSL_ERRATUM_DDR_A003
184 bool
185
186config SYS_FSL_ERRATUM_DDR_A003474
187 bool