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git01.mediatek.com / filogic / uboot / f8f6b32629a9f20a7731a433b7175cd9720ca887 / . / drivers / ddr / fsl / Kconfig
blob: fe69bef3d3aea0afe0922a7898914f2857be2bef [file] [log] [blame]
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
Tom Rinie5404982021-05-14 21:34:26 -0400[diff] [blame]5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
6 Layerscape SoCs (such as ls2080a).
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]13if SYS_FSL_DDR || SYS_FSL_MMDC
14
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]15config SYS_FSL_DDR_BE
16 bool
17 help
18 Access DDR registers in big-endian
19
20config SYS_FSL_DDR_LE
21 bool
22 help
23 Access DDR registers in little-endian
24
Rajesh Bhagatba2414f2019-02-01 05:22:01 +0000[diff] [blame]25config FSL_DDR_BIST
26 bool
27
28config FSL_DDR_INTERACTIVE
29 bool
30
31config FSL_DDR_SYNC_REFRESH
32 bool
33
34config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
35 bool
36
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]37menu "Freescale DDR controllers"
38 depends on SYS_FSL_DDR
39
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]40config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]41 int "Maximum DDR controllers"
42 default 3 if ARCH_LS2080A || \
43 ARCH_T4240
44 default 2 if ARCH_B4860 || \
45 ARCH_BSC9132 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]46 ARCH_P4080 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]47 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]48 ARCH_LX2160A || \
Tom Rinia7ffa3d2021-05-23 10:58:05 -0400[diff] [blame]49 ARCH_LX2162A
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]50 default 1
51
Tom Rini56184602022-02-25 11:19:53 -0500[diff] [blame]52config CHIP_SELECTS_PER_CTRL
53 int "Number of chip selects per controller"
54 default 4
55
Tom Rini3210bdc2022-03-30 18:07:31 -0400[diff] [blame]56config DIMM_SLOTS_PER_CTLR
57 int "Number of DIMM slots per controller"
58 default 1
59
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]60config SYS_FSL_DDR_VER
61 int
62 default 50 if SYS_FSL_DDR_VER_50
63 default 47 if SYS_FSL_DDR_VER_47
64 default 46 if SYS_FSL_DDR_VER_46
65 default 44 if SYS_FSL_DDR_VER_44
66
67config SYS_FSL_DDR_VER_50
68 bool
69
70config SYS_FSL_DDR_VER_47
71 bool
72
73config SYS_FSL_DDR_VER_46
74 bool
75
76config SYS_FSL_DDR_VER_44
77 bool
78
79config SYS_FSL_DDRC_GEN1
80 bool
81 help
82 Enable Freescale DDR controller.
83
84config SYS_FSL_DDRC_GEN2
85 bool
86 depends on !MPC86xx
87 help
88 Enable Freescale DDR2 controller.
89
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]90config SYS_FSL_DDRC_GEN3
91 bool
92 depends on PPC
93 help
94 Enable Freescale DDR3 controller for PowerPC SoCs.
95
96config SYS_FSL_DDRC_ARM_GEN3
97 bool
98 depends on ARM
99 help
100 Enable Freescale DDR3 controller for ARM SoCs.
101
102config SYS_FSL_DDRC_GEN4
103 bool
104 help
105 Enable Freescale DDR4 controller.
106
107config SYS_FSL_HAS_DDR4
108 bool
109
110config SYS_FSL_HAS_DDR3
111 bool
112
113config SYS_FSL_HAS_DDR2
114 bool
115
116config SYS_FSL_HAS_DDR1
117 bool
118
119choice
120 prompt "DDR technology"
121 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
122 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
123 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
124 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
125
126config SYS_FSL_DDR4
127 bool "Freescale DDR4 controller"
128 depends on SYS_FSL_HAS_DDR4
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]129 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]130 select SYS_FSL_DDRC_GEN4
131
132config SYS_FSL_DDR3
133 bool "Freescale DDR3 controller"
134 depends on SYS_FSL_HAS_DDR3
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]135 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]136 select SYS_FSL_DDRC_GEN3 if PPC
137 select SYS_FSL_DDRC_ARM_GEN3 if ARM
138
139config SYS_FSL_DDR2
140 bool "Freescale DDR2 controller"
141 depends on SYS_FSL_HAS_DDR2
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]142 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]143 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]144
145config SYS_FSL_DDR1
146 bool "Freescale DDR1 controller"
147 depends on SYS_FSL_HAS_DDR1
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]148 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]149 select SYS_FSL_DDRC_GEN1
150
151endchoice
152
153endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]154
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]155config FSL_DMA
156 def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
157
158config DDR_ECC
159 bool "ECC DDR memory support"
160
161config DDR_ECC_CMD
162 bool "Access the ECC features of the memory controller"
163 depends on DDR_ECC && MPC83xx
164 default y
165
166config ECC_INIT_VIA_DDRCONTROLLER
167 bool "DDR Memory controller initializes memory."
168 help
169 Use the DDR controller to auto initialize memory. If not enabled,
170 the DMA controller is responsible for doing this.
171
172endif
173
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]174menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
175 depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
176
177config SYS_BR0_PRELIM_BOOL
178 bool "Define Bank 0"
179
180config SYS_BR0_PRELIM
181 hex "Preliminary value for BR0"
182 depends on SYS_BR0_PRELIM_BOOL
183
184config SYS_OR0_PRELIM
185 hex "Preliminary value for OR0"
186 depends on SYS_BR0_PRELIM_BOOL
187
188config SYS_BR1_PRELIM_BOOL
189 bool "Define Bank 1"
190
191config SYS_BR1_PRELIM
192 hex "Preliminary value for BR1"
193 depends on SYS_BR1_PRELIM_BOOL
194
195config SYS_OR1_PRELIM
196 hex "Preliminary value for OR1"
197 depends on SYS_BR1_PRELIM_BOOL
198
199config SYS_BR2_PRELIM_BOOL
200 bool "Define Bank 2"
201
202config SYS_BR2_PRELIM
203 hex "Preliminary value for BR2"
204 depends on SYS_BR2_PRELIM_BOOL
205
206config SYS_OR2_PRELIM
207 hex "Preliminary value for OR2"
208 depends on SYS_BR2_PRELIM_BOOL
209
210config SYS_BR3_PRELIM_BOOL
211 bool "Define Bank 3"
212
213config SYS_BR3_PRELIM
214 hex "Preliminary value for BR3"
215 depends on SYS_BR3_PRELIM_BOOL
216
217config SYS_OR3_PRELIM
218 hex "Preliminary value for OR3"
219 depends on SYS_BR3_PRELIM_BOOL
220
221config SYS_BR4_PRELIM_BOOL
222 bool "Define Bank 4"
223
224config SYS_BR4_PRELIM
225 hex "Preliminary value for BR4"
226 depends on SYS_BR4_PRELIM_BOOL
227
228config SYS_OR4_PRELIM
229 hex "Preliminary value for OR4"
230 depends on SYS_BR4_PRELIM_BOOL
231
232config SYS_BR5_PRELIM_BOOL
233 bool "Define Bank 5"
234
235config SYS_BR5_PRELIM
236 hex "Preliminary value for BR5"
237 depends on SYS_BR5_PRELIM_BOOL
238
239config SYS_OR5_PRELIM
240 hex "Preliminary value for OR5"
241 depends on SYS_BR5_PRELIM_BOOL
242
243config SYS_BR6_PRELIM_BOOL
244 bool "Define Bank 6"
245
246config SYS_BR6_PRELIM
247 hex "Preliminary value for BR6"
248 depends on SYS_BR6_PRELIM_BOOL
249
250config SYS_OR6_PRELIM
251 hex "Preliminary value for OR6"
252 depends on SYS_BR6_PRELIM_BOOL
253
254config SYS_BR7_PRELIM_BOOL
255 bool "Define Bank 7"
256
257config SYS_BR7_PRELIM
258 hex "Preliminary value for BR7"
259 depends on SYS_BR7_PRELIM_BOOL
260
261config SYS_OR7_PRELIM
262 hex "Preliminary value for OR7"
263 depends on SYS_BR7_PRELIM_BOOL
264endmenu
265
Tom Rinif8f6b322022-05-21 14:44:28 -0400[diff] [blame^]266if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
267 TARGET_P1020RDB_PD || TARGET_P2020RDB
268
269config COMMON_INIT_DDR
270 bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
271
272config SPL_COMMON_INIT_DDR
273 bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
274
275config TPL_COMMON_INIT_DDR
276 bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
277
278endif
279
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]280config SYS_FSL_ERRATUM_A008378
281 bool
282
Joakim Tjernlund477602c2019-11-20 17:07:34 +0100[diff] [blame]283config SYS_FSL_ERRATUM_A008109
284 bool
285
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]286config SYS_FSL_ERRATUM_A008511
287 bool
288
289config SYS_FSL_ERRATUM_A009663
290 bool
291
292config SYS_FSL_ERRATUM_A009801
293 bool
294
295config SYS_FSL_ERRATUM_A009803
296 bool
297
298config SYS_FSL_ERRATUM_A009942
299 bool
300
301config SYS_FSL_ERRATUM_A010165
302 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]303
304config SYS_FSL_ERRATUM_NMG_DDR120
305 bool
306
307config SYS_FSL_ERRATUM_DDR_115
308 bool
309
310config SYS_FSL_ERRATUM_DDR111_DDR134
311 bool
312
313config SYS_FSL_ERRATUM_DDR_A003
314 bool
315
316config SYS_FSL_ERRATUM_DDR_A003474
317 bool