Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010,2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | 74472ac | 2014-11-10 17:16:51 -0700 | [diff] [blame] | 9 | #include <dm.h> |
Simon Glass | 0655c91 | 2015-04-14 21:03:28 -0600 | [diff] [blame] | 10 | #include <errno.h> |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 11 | #include <ns16550.h> |
Simon Glass | 1502392 | 2017-06-12 06:21:39 -0600 | [diff] [blame] | 12 | #include <usb.h> |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 13 | #include <asm/io.h> |
Stephen Warren | 8d1fb31 | 2015-01-19 16:25:52 -0700 | [diff] [blame] | 14 | #include <asm/arch-tegra/ap.h> |
Tom Warren | ab37196 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 15 | #include <asm/arch-tegra/board.h> |
| 16 | #include <asm/arch-tegra/clk_rst.h> |
| 17 | #include <asm/arch-tegra/pmc.h> |
| 18 | #include <asm/arch-tegra/sys_proto.h> |
| 19 | #include <asm/arch-tegra/uart.h> |
| 20 | #include <asm/arch-tegra/warmboot.h> |
Alexandre Courbot | 7f936d4 | 2015-07-09 16:33:00 +0900 | [diff] [blame] | 21 | #include <asm/arch-tegra/gpu.h> |
Simon Glass | 1502392 | 2017-06-12 06:21:39 -0600 | [diff] [blame] | 22 | #include <asm/arch-tegra/usb.h> |
| 23 | #include <asm/arch-tegra/xusb-padctl.h> |
| 24 | #include <asm/arch/clock.h> |
| 25 | #include <asm/arch/funcmux.h> |
| 26 | #include <asm/arch/pinmux.h> |
| 27 | #include <asm/arch/pmu.h> |
| 28 | #include <asm/arch/tegra.h> |
Tom Warren | d32b2a4 | 2012-12-11 13:34:17 +0000 | [diff] [blame] | 29 | #ifdef CONFIG_TEGRA_CLOCK_SCALING |
| 30 | #include <asm/arch/emc.h> |
| 31 | #endif |
Simon Glass | 0655c91 | 2015-04-14 21:03:28 -0600 | [diff] [blame] | 32 | #include <power/as3722.h> |
Jimmy Zhang | a308d46 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 33 | #include "emc.h" |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 34 | |
| 35 | DECLARE_GLOBAL_DATA_PTR; |
| 36 | |
Simon Glass | 74472ac | 2014-11-10 17:16:51 -0700 | [diff] [blame] | 37 | #ifdef CONFIG_SPL_BUILD |
| 38 | /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ |
| 39 | U_BOOT_DEVICE(tegra_gpios) = { |
| 40 | "gpio_tegra" |
| 41 | }; |
| 42 | #endif |
| 43 | |
Jeroen Hofstee | 93dfae7 | 2014-10-08 22:57:46 +0200 | [diff] [blame] | 44 | __weak void pinmux_init(void) {} |
| 45 | __weak void pin_mux_usb(void) {} |
| 46 | __weak void pin_mux_spi(void) {} |
Stephen Warren | c044fe2 | 2016-09-13 10:45:47 -0600 | [diff] [blame] | 47 | __weak void pin_mux_mmc(void) {} |
Jeroen Hofstee | 93dfae7 | 2014-10-08 22:57:46 +0200 | [diff] [blame] | 48 | __weak void gpio_early_init_uart(void) {} |
| 49 | __weak void pin_mux_display(void) {} |
Tom Warren | f3035ca | 2015-02-20 12:22:22 -0700 | [diff] [blame] | 50 | __weak void start_cpu_fan(void) {} |
Lucas Stach | 18561f7 | 2012-09-25 20:21:14 +0000 | [diff] [blame] | 51 | |
Tom Warren | 6b33c83 | 2014-01-24 12:46:11 -0700 | [diff] [blame] | 52 | #if defined(CONFIG_TEGRA_NAND) |
Jeroen Hofstee | 93dfae7 | 2014-10-08 22:57:46 +0200 | [diff] [blame] | 53 | __weak void pin_mux_nand(void) |
Lucas Stach | 0458584 | 2012-09-29 10:02:09 +0000 | [diff] [blame] | 54 | { |
| 55 | funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); |
| 56 | } |
Tom Warren | 6b33c83 | 2014-01-24 12:46:11 -0700 | [diff] [blame] | 57 | #endif |
Lucas Stach | 0458584 | 2012-09-29 10:02:09 +0000 | [diff] [blame] | 58 | |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 59 | /* |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 60 | * Routine: power_det_init |
| 61 | * Description: turn off power detects |
| 62 | */ |
| 63 | static void power_det_init(void) |
| 64 | { |
Allen Martin | 55d98a1 | 2012-08-31 08:30:00 +0000 | [diff] [blame] | 65 | #if defined(CONFIG_TEGRA20) |
Tom Warren | 22562a4 | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 66 | struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 67 | |
| 68 | /* turn off power detects */ |
| 69 | writel(0, &pmc->pmc_pwr_det_latch); |
| 70 | writel(0, &pmc->pmc_pwr_det); |
| 71 | #endif |
| 72 | } |
Simon Glass | 675804d | 2015-04-14 21:03:24 -0600 | [diff] [blame] | 73 | |
Simon Glass | 69c93c7 | 2015-04-14 21:03:25 -0600 | [diff] [blame] | 74 | __weak int tegra_board_id(void) |
| 75 | { |
| 76 | return -1; |
| 77 | } |
| 78 | |
Simon Glass | 675804d | 2015-04-14 21:03:24 -0600 | [diff] [blame] | 79 | #ifdef CONFIG_DISPLAY_BOARDINFO |
| 80 | int checkboard(void) |
| 81 | { |
Simon Glass | 69c93c7 | 2015-04-14 21:03:25 -0600 | [diff] [blame] | 82 | int board_id = tegra_board_id(); |
| 83 | |
| 84 | printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); |
| 85 | if (board_id != -1) |
| 86 | printf(", ID: %d\n", board_id); |
| 87 | printf("\n"); |
Simon Glass | 675804d | 2015-04-14 21:03:24 -0600 | [diff] [blame] | 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | #endif /* CONFIG_DISPLAY_BOARDINFO */ |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 92 | |
Simon Glass | 0cf62dd | 2015-04-14 21:03:27 -0600 | [diff] [blame] | 93 | __weak int tegra_lcd_pmic_init(int board_it) |
| 94 | { |
| 95 | return 0; |
| 96 | } |
| 97 | |
Simon Glass | 44a6808 | 2015-06-05 14:39:42 -0600 | [diff] [blame] | 98 | __weak int nvidia_board_init(void) |
| 99 | { |
| 100 | return 0; |
| 101 | } |
| 102 | |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 103 | /* |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 104 | * Routine: board_init |
| 105 | * Description: Early hardware init. |
| 106 | */ |
| 107 | int board_init(void) |
| 108 | { |
Jimmy Zhang | a308d46 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 109 | __maybe_unused int err; |
Simon Glass | 0cf62dd | 2015-04-14 21:03:27 -0600 | [diff] [blame] | 110 | __maybe_unused int board_id; |
Jimmy Zhang | a308d46 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 111 | |
Simon Glass | 704e60d | 2011-11-05 04:46:51 +0000 | [diff] [blame] | 112 | /* Do clocks and UART first so that printf() works */ |
Simon Glass | c2ea5e4 | 2011-09-21 12:40:04 +0000 | [diff] [blame] | 113 | clock_init(); |
| 114 | clock_verify(); |
| 115 | |
Alexandre Courbot | f36729d | 2015-10-19 13:57:03 +0900 | [diff] [blame] | 116 | tegra_gpu_config(); |
Alexandre Courbot | 7f936d4 | 2015-07-09 16:33:00 +0900 | [diff] [blame] | 117 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 118 | #ifdef CONFIG_TEGRA_SPI |
Stephen Warren | d2f67fe | 2012-06-12 08:33:40 +0000 | [diff] [blame] | 119 | pin_mux_spi(); |
Tom Warren | ee554f8 | 2011-11-05 09:48:11 +0000 | [diff] [blame] | 120 | #endif |
Allen Martin | ba4fb9b | 2013-01-29 13:51:28 +0000 | [diff] [blame] | 121 | |
Masahiro Yamada | b2c8868 | 2017-01-10 13:32:07 +0900 | [diff] [blame] | 122 | #ifdef CONFIG_MMC_SDHCI_TEGRA |
Stephen Warren | c044fe2 | 2016-09-13 10:45:47 -0600 | [diff] [blame] | 123 | pin_mux_mmc(); |
| 124 | #endif |
| 125 | |
Simon Glass | eb21083 | 2016-01-30 16:37:48 -0700 | [diff] [blame] | 126 | /* Init is handled automatically in the driver-model case */ |
Simon Glass | d5f3613 | 2016-01-30 16:38:02 -0700 | [diff] [blame] | 127 | #if defined(CONFIG_DM_VIDEO) |
Marc Dietrich | 9bbe64b | 2012-11-25 11:26:11 +0000 | [diff] [blame] | 128 | pin_mux_display(); |
Simon Glass | 3e2b2d9 | 2016-01-30 16:37:49 -0700 | [diff] [blame] | 129 | #endif |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 130 | /* boot param addr */ |
| 131 | gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); |
Wei Ni | 39d45ed | 2012-04-02 13:18:58 +0000 | [diff] [blame] | 132 | |
| 133 | power_det_init(); |
| 134 | |
Simon Glass | 026fefb | 2012-10-30 07:28:53 +0000 | [diff] [blame] | 135 | #ifdef CONFIG_SYS_I2C_TEGRA |
Simon Glass | e772be8 | 2012-04-02 13:18:54 +0000 | [diff] [blame] | 136 | # ifdef CONFIG_TEGRA_PMU |
| 137 | if (pmu_set_nominal()) |
| 138 | debug("Failed to select nominal voltages\n"); |
Jimmy Zhang | a308d46 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 139 | # ifdef CONFIG_TEGRA_CLOCK_SCALING |
| 140 | err = board_emc_init(); |
| 141 | if (err) |
| 142 | debug("Memory controller init failed: %d\n", err); |
| 143 | # endif |
| 144 | # endif /* CONFIG_TEGRA_PMU */ |
Simon Glass | 81a3356 | 2017-04-26 22:27:44 -0600 | [diff] [blame] | 145 | #ifdef CONFIG_PMIC_AS3722 |
Simon Glass | 0655c91 | 2015-04-14 21:03:28 -0600 | [diff] [blame] | 146 | err = as3722_init(NULL); |
| 147 | if (err && err != -ENODEV) |
| 148 | return err; |
| 149 | #endif |
Simon Glass | 026fefb | 2012-10-30 07:28:53 +0000 | [diff] [blame] | 150 | #endif /* CONFIG_SYS_I2C_TEGRA */ |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 151 | |
Simon Glass | 5d73a8d | 2012-02-27 10:52:50 +0000 | [diff] [blame] | 152 | #ifdef CONFIG_USB_EHCI_TEGRA |
| 153 | pin_mux_usb(); |
Simon Glass | 5d73a8d | 2012-02-27 10:52:50 +0000 | [diff] [blame] | 154 | #endif |
Mateusz Zalega | d862f89 | 2013-10-04 19:22:26 +0200 | [diff] [blame] | 155 | |
Simon Glass | d5f3613 | 2016-01-30 16:38:02 -0700 | [diff] [blame] | 156 | #if defined(CONFIG_DM_VIDEO) |
Simon Glass | 0cf62dd | 2015-04-14 21:03:27 -0600 | [diff] [blame] | 157 | board_id = tegra_board_id(); |
| 158 | err = tegra_lcd_pmic_init(board_id); |
Simon Glass | 9d8271e | 2017-06-12 06:21:59 -0600 | [diff] [blame] | 159 | if (err) { |
| 160 | debug("Failed to set up LCD PMIC\n"); |
Simon Glass | 0cf62dd | 2015-04-14 21:03:27 -0600 | [diff] [blame] | 161 | return err; |
Simon Glass | 9d8271e | 2017-06-12 06:21:59 -0600 | [diff] [blame] | 162 | } |
Simon Glass | 3e2b2d9 | 2016-01-30 16:37:49 -0700 | [diff] [blame] | 163 | #endif |
Simon Glass | 5d73a8d | 2012-02-27 10:52:50 +0000 | [diff] [blame] | 164 | |
Lucas Stach | 0458584 | 2012-09-29 10:02:09 +0000 | [diff] [blame] | 165 | #ifdef CONFIG_TEGRA_NAND |
| 166 | pin_mux_nand(); |
| 167 | #endif |
| 168 | |
Thierry Reding | f202e02 | 2014-12-09 22:25:09 -0700 | [diff] [blame] | 169 | tegra_xusb_padctl_init(gd->fdt_blob); |
| 170 | |
Tom Warren | 22562a4 | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 171 | #ifdef CONFIG_TEGRA_LP0 |
Allen Martin | 0ca1a45 | 2012-08-31 08:30:11 +0000 | [diff] [blame] | 172 | /* save Sdram params to PMC 2, 4, and 24 for WB0 */ |
| 173 | warmboot_save_sdram_params(); |
| 174 | |
Simon Glass | 8cc8f61 | 2012-04-02 13:18:57 +0000 | [diff] [blame] | 175 | /* prepare the WB code to LP0 location */ |
| 176 | warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); |
| 177 | #endif |
Simon Glass | 44a6808 | 2015-06-05 14:39:42 -0600 | [diff] [blame] | 178 | return nvidia_board_init(); |
Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 179 | } |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 180 | |
| 181 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
Thierry Reding | 2fa4db0 | 2012-06-04 20:02:27 +0000 | [diff] [blame] | 182 | static void __gpio_early_init(void) |
| 183 | { |
| 184 | } |
| 185 | |
| 186 | void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); |
| 187 | |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 188 | int board_early_init_f(void) |
| 189 | { |
Simon Glass | 2b4029a | 2017-05-31 17:57:16 -0600 | [diff] [blame] | 190 | if (!clock_early_init_done()) |
| 191 | clock_early_init(); |
| 192 | |
Stephen Warren | 5a44ab4 | 2016-01-26 10:59:42 -0700 | [diff] [blame] | 193 | #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) |
| 194 | #define USBCMD_FS2 (1 << 15) |
| 195 | { |
| 196 | struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; |
| 197 | writel(USBCMD_FS2, &usbctlr->usb_cmd); |
| 198 | } |
| 199 | #endif |
| 200 | |
Thierry Reding | ff81d75 | 2015-07-28 11:35:53 +0200 | [diff] [blame] | 201 | /* Do any special system timer/TSC setup */ |
| 202 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) |
| 203 | if (!tegra_cpu_is_non_secure()) |
| 204 | #endif |
| 205 | arch_timer_init(); |
| 206 | |
Tom Warren | d32b2a4 | 2012-12-11 13:34:17 +0000 | [diff] [blame] | 207 | pinmux_init(); |
Simon Glass | a8ccc8b | 2011-11-28 15:04:40 +0000 | [diff] [blame] | 208 | board_init_uart_f(); |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 209 | |
| 210 | /* Initialize periph GPIOs */ |
Thierry Reding | 2fa4db0 | 2012-06-04 20:02:27 +0000 | [diff] [blame] | 211 | gpio_early_init(); |
Simon Glass | 704e60d | 2011-11-05 04:46:51 +0000 | [diff] [blame] | 212 | gpio_early_init_uart(); |
Lucas Stach | 18561f7 | 2012-09-25 20:21:14 +0000 | [diff] [blame] | 213 | |
Simon Glass | dfcee79 | 2011-09-21 12:40:03 +0000 | [diff] [blame] | 214 | return 0; |
| 215 | } |
| 216 | #endif /* EARLY_INIT */ |
Simon Glass | 4f476f3 | 2012-10-17 13:24:52 +0000 | [diff] [blame] | 217 | |
| 218 | int board_late_init(void) |
| 219 | { |
Stephen Warren | 8d1fb31 | 2015-01-19 16:25:52 -0700 | [diff] [blame] | 220 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) |
| 221 | if (tegra_cpu_is_non_secure()) { |
| 222 | printf("CPU is in NS mode\n"); |
| 223 | setenv("cpu_ns_mode", "1"); |
| 224 | } else { |
| 225 | setenv("cpu_ns_mode", ""); |
| 226 | } |
| 227 | #endif |
Tom Warren | f3035ca | 2015-02-20 12:22:22 -0700 | [diff] [blame] | 228 | start_cpu_fan(); |
| 229 | |
Simon Glass | 4f476f3 | 2012-10-17 13:24:52 +0000 | [diff] [blame] | 230 | return 0; |
| 231 | } |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 232 | |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 233 | /* |
| 234 | * In some SW environments, a memory carve-out exists to house a secure |
| 235 | * monitor, a trusted OS, and/or various statically allocated media buffers. |
| 236 | * |
| 237 | * This carveout exists at the highest possible address that is within a |
| 238 | * 32-bit physical address space. |
| 239 | * |
| 240 | * This function returns the total size of this carve-out. At present, the |
| 241 | * returned value is hard-coded for simplicity. In the future, it may be |
| 242 | * possible to determine the carve-out size: |
| 243 | * - By querying some run-time information source, such as: |
| 244 | * - A structure passed to U-Boot by earlier boot software. |
| 245 | * - SoC registers. |
| 246 | * - A call into the secure monitor. |
| 247 | * - In the per-board U-Boot configuration header, based on knowledge of the |
| 248 | * SW environment that U-Boot is being built for. |
| 249 | * |
| 250 | * For now, we support two configurations in U-Boot: |
| 251 | * - 32-bit ports without any form of carve-out. |
| 252 | * - 64 bit ports which are assumed to use a carve-out of a conservatively |
| 253 | * hard-coded size. |
| 254 | */ |
| 255 | static ulong carveout_size(void) |
| 256 | { |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 257 | #ifdef CONFIG_ARM64 |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 258 | return SZ_512M; |
| 259 | #else |
| 260 | return 0; |
| 261 | #endif |
| 262 | } |
| 263 | |
| 264 | /* |
| 265 | * Determine the amount of usable RAM below 4GiB, taking into account any |
| 266 | * carve-out that may be assigned. |
| 267 | */ |
| 268 | static ulong usable_ram_size_below_4g(void) |
| 269 | { |
| 270 | ulong total_size_below_4g; |
| 271 | ulong usable_size_below_4g; |
| 272 | |
| 273 | /* |
| 274 | * The total size of RAM below 4GiB is the lesser address of: |
| 275 | * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). |
| 276 | * (b) The size RAM physically present in the system. |
| 277 | */ |
| 278 | if (gd->ram_size < SZ_2G) |
| 279 | total_size_below_4g = gd->ram_size; |
| 280 | else |
| 281 | total_size_below_4g = SZ_2G; |
| 282 | |
| 283 | /* Calculate usable RAM by subtracting out any carve-out size */ |
| 284 | usable_size_below_4g = total_size_below_4g - carveout_size(); |
| 285 | |
| 286 | return usable_size_below_4g; |
| 287 | } |
| 288 | |
| 289 | /* |
| 290 | * Represent all available RAM in either one or two banks. |
| 291 | * |
| 292 | * The first bank describes any usable RAM below 4GiB. |
| 293 | * The second bank describes any RAM above 4GiB. |
| 294 | * |
| 295 | * This split is driven by the following requirements: |
| 296 | * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg |
| 297 | * property for memory below and above the 4GiB boundary. The layout of that |
| 298 | * DT property is directly driven by the entries in the U-Boot bank array. |
| 299 | * - The potential existence of a carve-out at the end of RAM below 4GiB can |
| 300 | * only be represented using multiple banks. |
| 301 | * |
| 302 | * Explicitly removing the carve-out RAM from the bank entries makes the RAM |
| 303 | * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot |
| 304 | * command-line. |
| 305 | * |
| 306 | * This does mean that the DT U-Boot passes to the Linux kernel will not |
| 307 | * include this RAM in /memory/reg at all. An alternative would be to include |
| 308 | * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node |
| 309 | * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the |
| 310 | * Linux kernel will ever need to access any RAM in* the carve-out via a CPU |
| 311 | * mapping, so either way is acceptable. |
| 312 | * |
| 313 | * On 32-bit systems, we never define a bank for RAM above 4GiB, since the |
| 314 | * start address of that bank cannot be represented in the 32-bit .size |
| 315 | * field. |
| 316 | */ |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 317 | int dram_init_banksize(void) |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 318 | { |
| 319 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
| 320 | gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); |
| 321 | |
Simon Glass | 46fcfc1 | 2015-11-19 20:27:02 -0700 | [diff] [blame] | 322 | #ifdef CONFIG_PCI |
| 323 | gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; |
| 324 | #endif |
| 325 | |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 326 | #ifdef CONFIG_PHYS_64BIT |
| 327 | if (gd->ram_size > SZ_2G) { |
| 328 | gd->bd->bi_dram[1].start = 0x100000000; |
| 329 | gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; |
| 330 | } else |
| 331 | #endif |
| 332 | { |
| 333 | gd->bd->bi_dram[1].start = 0; |
| 334 | gd->bd->bi_dram[1].size = 0; |
| 335 | } |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 336 | |
| 337 | return 0; |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 338 | } |
| 339 | |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 340 | /* |
| 341 | * Most hardware on 64-bit Tegra is still restricted to DMA to the lower |
| 342 | * 32-bits of the physical address space. Cap the maximum usable RAM area |
| 343 | * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 344 | * boundary that most devices can address. Also, don't let U-Boot use any |
| 345 | * carve-out, as mentioned above. |
Stephen Warren | 30d1966 | 2015-07-29 13:47:58 -0600 | [diff] [blame] | 346 | * |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 347 | * This function is called before dram_init_banksize(), so we can't simply |
| 348 | * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 349 | */ |
| 350 | ulong board_get_usable_ram_top(ulong total_size) |
| 351 | { |
Stephen Warren | 3ffd090 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 352 | return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); |
Thierry Reding | 6d835fa | 2015-07-27 11:45:24 -0600 | [diff] [blame] | 353 | } |