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Tom Warren41b68382011-01-27 10:58:05 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Tom Warren41b68382011-01-27 10:58:05 +00006 */
7
8#include <common.h>
Simon Glass74472ac2014-11-10 17:16:51 -07009#include <dm.h>
Simon Glass0655c912015-04-14 21:03:28 -060010#include <errno.h>
Tom Warren41b68382011-01-27 10:58:05 +000011#include <ns16550.h>
Simon Glass15023922017-06-12 06:21:39 -060012#include <usb.h>
Tom Warren41b68382011-01-27 10:58:05 +000013#include <asm/io.h>
Stephen Warren8d1fb312015-01-19 16:25:52 -070014#include <asm/arch-tegra/ap.h>
Tom Warrenab371962012-09-19 15:50:56 -070015#include <asm/arch-tegra/board.h>
16#include <asm/arch-tegra/clk_rst.h>
17#include <asm/arch-tegra/pmc.h>
18#include <asm/arch-tegra/sys_proto.h>
19#include <asm/arch-tegra/uart.h>
20#include <asm/arch-tegra/warmboot.h>
Alexandre Courbot7f936d42015-07-09 16:33:00 +090021#include <asm/arch-tegra/gpu.h>
Simon Glass15023922017-06-12 06:21:39 -060022#include <asm/arch-tegra/usb.h>
23#include <asm/arch-tegra/xusb-padctl.h>
24#include <asm/arch/clock.h>
25#include <asm/arch/funcmux.h>
26#include <asm/arch/pinmux.h>
27#include <asm/arch/pmu.h>
28#include <asm/arch/tegra.h>
Tom Warrend32b2a42012-12-11 13:34:17 +000029#ifdef CONFIG_TEGRA_CLOCK_SCALING
30#include <asm/arch/emc.h>
31#endif
Simon Glass0655c912015-04-14 21:03:28 -060032#include <power/as3722.h>
Jimmy Zhanga308d462012-04-10 05:17:06 +000033#include "emc.h"
Tom Warren41b68382011-01-27 10:58:05 +000034
35DECLARE_GLOBAL_DATA_PTR;
36
Simon Glass74472ac2014-11-10 17:16:51 -070037#ifdef CONFIG_SPL_BUILD
38/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
39U_BOOT_DEVICE(tegra_gpios) = {
40 "gpio_tegra"
41};
42#endif
43
Jeroen Hofstee93dfae72014-10-08 22:57:46 +020044__weak void pinmux_init(void) {}
45__weak void pin_mux_usb(void) {}
46__weak void pin_mux_spi(void) {}
Stephen Warrenc044fe22016-09-13 10:45:47 -060047__weak void pin_mux_mmc(void) {}
Jeroen Hofstee93dfae72014-10-08 22:57:46 +020048__weak void gpio_early_init_uart(void) {}
49__weak void pin_mux_display(void) {}
Tom Warrenf3035ca2015-02-20 12:22:22 -070050__weak void start_cpu_fan(void) {}
Lucas Stach18561f72012-09-25 20:21:14 +000051
Tom Warren6b33c832014-01-24 12:46:11 -070052#if defined(CONFIG_TEGRA_NAND)
Jeroen Hofstee93dfae72014-10-08 22:57:46 +020053__weak void pin_mux_nand(void)
Lucas Stach04585842012-09-29 10:02:09 +000054{
55 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
56}
Tom Warren6b33c832014-01-24 12:46:11 -070057#endif
Lucas Stach04585842012-09-29 10:02:09 +000058
Tom Warren41b68382011-01-27 10:58:05 +000059/*
Wei Ni39d45ed2012-04-02 13:18:58 +000060 * Routine: power_det_init
61 * Description: turn off power detects
62 */
63static void power_det_init(void)
64{
Allen Martin55d98a12012-08-31 08:30:00 +000065#if defined(CONFIG_TEGRA20)
Tom Warren22562a42012-09-04 17:00:24 -070066 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
Wei Ni39d45ed2012-04-02 13:18:58 +000067
68 /* turn off power detects */
69 writel(0, &pmc->pmc_pwr_det_latch);
70 writel(0, &pmc->pmc_pwr_det);
71#endif
72}
Simon Glass675804d2015-04-14 21:03:24 -060073
Simon Glass69c93c72015-04-14 21:03:25 -060074__weak int tegra_board_id(void)
75{
76 return -1;
77}
78
Simon Glass675804d2015-04-14 21:03:24 -060079#ifdef CONFIG_DISPLAY_BOARDINFO
80int checkboard(void)
81{
Simon Glass69c93c72015-04-14 21:03:25 -060082 int board_id = tegra_board_id();
83
84 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
85 if (board_id != -1)
86 printf(", ID: %d\n", board_id);
87 printf("\n");
Simon Glass675804d2015-04-14 21:03:24 -060088
89 return 0;
90}
91#endif /* CONFIG_DISPLAY_BOARDINFO */
Wei Ni39d45ed2012-04-02 13:18:58 +000092
Simon Glass0cf62dd2015-04-14 21:03:27 -060093__weak int tegra_lcd_pmic_init(int board_it)
94{
95 return 0;
96}
97
Simon Glass44a68082015-06-05 14:39:42 -060098__weak int nvidia_board_init(void)
99{
100 return 0;
101}
102
Wei Ni39d45ed2012-04-02 13:18:58 +0000103/*
Tom Warren41b68382011-01-27 10:58:05 +0000104 * Routine: board_init
105 * Description: Early hardware init.
106 */
107int board_init(void)
108{
Jimmy Zhanga308d462012-04-10 05:17:06 +0000109 __maybe_unused int err;
Simon Glass0cf62dd2015-04-14 21:03:27 -0600110 __maybe_unused int board_id;
Jimmy Zhanga308d462012-04-10 05:17:06 +0000111
Simon Glass704e60d2011-11-05 04:46:51 +0000112 /* Do clocks and UART first so that printf() works */
Simon Glassc2ea5e42011-09-21 12:40:04 +0000113 clock_init();
114 clock_verify();
115
Alexandre Courbotf36729d2015-10-19 13:57:03 +0900116 tegra_gpu_config();
Alexandre Courbot7f936d42015-07-09 16:33:00 +0900117
Simon Glass1121b1b2014-10-13 23:42:13 -0600118#ifdef CONFIG_TEGRA_SPI
Stephen Warrend2f67fe2012-06-12 08:33:40 +0000119 pin_mux_spi();
Tom Warrenee554f82011-11-05 09:48:11 +0000120#endif
Allen Martinba4fb9b2013-01-29 13:51:28 +0000121
Masahiro Yamadab2c88682017-01-10 13:32:07 +0900122#ifdef CONFIG_MMC_SDHCI_TEGRA
Stephen Warrenc044fe22016-09-13 10:45:47 -0600123 pin_mux_mmc();
124#endif
125
Simon Glasseb210832016-01-30 16:37:48 -0700126 /* Init is handled automatically in the driver-model case */
Simon Glassd5f36132016-01-30 16:38:02 -0700127#if defined(CONFIG_DM_VIDEO)
Marc Dietrich9bbe64b2012-11-25 11:26:11 +0000128 pin_mux_display();
Simon Glass3e2b2d92016-01-30 16:37:49 -0700129#endif
Tom Warren41b68382011-01-27 10:58:05 +0000130 /* boot param addr */
131 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
Wei Ni39d45ed2012-04-02 13:18:58 +0000132
133 power_det_init();
134
Simon Glass026fefb2012-10-30 07:28:53 +0000135#ifdef CONFIG_SYS_I2C_TEGRA
Simon Glasse772be82012-04-02 13:18:54 +0000136# ifdef CONFIG_TEGRA_PMU
137 if (pmu_set_nominal())
138 debug("Failed to select nominal voltages\n");
Jimmy Zhanga308d462012-04-10 05:17:06 +0000139# ifdef CONFIG_TEGRA_CLOCK_SCALING
140 err = board_emc_init();
141 if (err)
142 debug("Memory controller init failed: %d\n", err);
143# endif
144# endif /* CONFIG_TEGRA_PMU */
Simon Glass81a33562017-04-26 22:27:44 -0600145#ifdef CONFIG_PMIC_AS3722
Simon Glass0655c912015-04-14 21:03:28 -0600146 err = as3722_init(NULL);
147 if (err && err != -ENODEV)
148 return err;
149#endif
Simon Glass026fefb2012-10-30 07:28:53 +0000150#endif /* CONFIG_SYS_I2C_TEGRA */
Tom Warren41b68382011-01-27 10:58:05 +0000151
Simon Glass5d73a8d2012-02-27 10:52:50 +0000152#ifdef CONFIG_USB_EHCI_TEGRA
153 pin_mux_usb();
Simon Glass5d73a8d2012-02-27 10:52:50 +0000154#endif
Mateusz Zalegad862f892013-10-04 19:22:26 +0200155
Simon Glassd5f36132016-01-30 16:38:02 -0700156#if defined(CONFIG_DM_VIDEO)
Simon Glass0cf62dd2015-04-14 21:03:27 -0600157 board_id = tegra_board_id();
158 err = tegra_lcd_pmic_init(board_id);
Simon Glass9d8271e2017-06-12 06:21:59 -0600159 if (err) {
160 debug("Failed to set up LCD PMIC\n");
Simon Glass0cf62dd2015-04-14 21:03:27 -0600161 return err;
Simon Glass9d8271e2017-06-12 06:21:59 -0600162 }
Simon Glass3e2b2d92016-01-30 16:37:49 -0700163#endif
Simon Glass5d73a8d2012-02-27 10:52:50 +0000164
Lucas Stach04585842012-09-29 10:02:09 +0000165#ifdef CONFIG_TEGRA_NAND
166 pin_mux_nand();
167#endif
168
Thierry Redingf202e022014-12-09 22:25:09 -0700169 tegra_xusb_padctl_init(gd->fdt_blob);
170
Tom Warren22562a42012-09-04 17:00:24 -0700171#ifdef CONFIG_TEGRA_LP0
Allen Martin0ca1a452012-08-31 08:30:11 +0000172 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
173 warmboot_save_sdram_params();
174
Simon Glass8cc8f612012-04-02 13:18:57 +0000175 /* prepare the WB code to LP0 location */
176 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
177#endif
Simon Glass44a68082015-06-05 14:39:42 -0600178 return nvidia_board_init();
Tom Warren41b68382011-01-27 10:58:05 +0000179}
Simon Glassdfcee792011-09-21 12:40:03 +0000180
181#ifdef CONFIG_BOARD_EARLY_INIT_F
Thierry Reding2fa4db02012-06-04 20:02:27 +0000182static void __gpio_early_init(void)
183{
184}
185
186void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
187
Simon Glassdfcee792011-09-21 12:40:03 +0000188int board_early_init_f(void)
189{
Simon Glass2b4029a2017-05-31 17:57:16 -0600190 if (!clock_early_init_done())
191 clock_early_init();
192
Stephen Warren5a44ab42016-01-26 10:59:42 -0700193#if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
194#define USBCMD_FS2 (1 << 15)
195 {
196 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
197 writel(USBCMD_FS2, &usbctlr->usb_cmd);
198 }
199#endif
200
Thierry Redingff81d752015-07-28 11:35:53 +0200201 /* Do any special system timer/TSC setup */
202#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
203 if (!tegra_cpu_is_non_secure())
204#endif
205 arch_timer_init();
206
Tom Warrend32b2a42012-12-11 13:34:17 +0000207 pinmux_init();
Simon Glassa8ccc8b2011-11-28 15:04:40 +0000208 board_init_uart_f();
Simon Glassdfcee792011-09-21 12:40:03 +0000209
210 /* Initialize periph GPIOs */
Thierry Reding2fa4db02012-06-04 20:02:27 +0000211 gpio_early_init();
Simon Glass704e60d2011-11-05 04:46:51 +0000212 gpio_early_init_uart();
Lucas Stach18561f72012-09-25 20:21:14 +0000213
Simon Glassdfcee792011-09-21 12:40:03 +0000214 return 0;
215}
216#endif /* EARLY_INIT */
Simon Glass4f476f32012-10-17 13:24:52 +0000217
218int board_late_init(void)
219{
Stephen Warren8d1fb312015-01-19 16:25:52 -0700220#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
221 if (tegra_cpu_is_non_secure()) {
222 printf("CPU is in NS mode\n");
223 setenv("cpu_ns_mode", "1");
224 } else {
225 setenv("cpu_ns_mode", "");
226 }
227#endif
Tom Warrenf3035ca2015-02-20 12:22:22 -0700228 start_cpu_fan();
229
Simon Glass4f476f32012-10-17 13:24:52 +0000230 return 0;
231}
Thierry Reding6d835fa2015-07-27 11:45:24 -0600232
Stephen Warren3ffd0902015-08-07 16:12:45 -0600233/*
234 * In some SW environments, a memory carve-out exists to house a secure
235 * monitor, a trusted OS, and/or various statically allocated media buffers.
236 *
237 * This carveout exists at the highest possible address that is within a
238 * 32-bit physical address space.
239 *
240 * This function returns the total size of this carve-out. At present, the
241 * returned value is hard-coded for simplicity. In the future, it may be
242 * possible to determine the carve-out size:
243 * - By querying some run-time information source, such as:
244 * - A structure passed to U-Boot by earlier boot software.
245 * - SoC registers.
246 * - A call into the secure monitor.
247 * - In the per-board U-Boot configuration header, based on knowledge of the
248 * SW environment that U-Boot is being built for.
249 *
250 * For now, we support two configurations in U-Boot:
251 * - 32-bit ports without any form of carve-out.
252 * - 64 bit ports which are assumed to use a carve-out of a conservatively
253 * hard-coded size.
254 */
255static ulong carveout_size(void)
256{
Thierry Reding6d835fa2015-07-27 11:45:24 -0600257#ifdef CONFIG_ARM64
Stephen Warren3ffd0902015-08-07 16:12:45 -0600258 return SZ_512M;
259#else
260 return 0;
261#endif
262}
263
264/*
265 * Determine the amount of usable RAM below 4GiB, taking into account any
266 * carve-out that may be assigned.
267 */
268static ulong usable_ram_size_below_4g(void)
269{
270 ulong total_size_below_4g;
271 ulong usable_size_below_4g;
272
273 /*
274 * The total size of RAM below 4GiB is the lesser address of:
275 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
276 * (b) The size RAM physically present in the system.
277 */
278 if (gd->ram_size < SZ_2G)
279 total_size_below_4g = gd->ram_size;
280 else
281 total_size_below_4g = SZ_2G;
282
283 /* Calculate usable RAM by subtracting out any carve-out size */
284 usable_size_below_4g = total_size_below_4g - carveout_size();
285
286 return usable_size_below_4g;
287}
288
289/*
290 * Represent all available RAM in either one or two banks.
291 *
292 * The first bank describes any usable RAM below 4GiB.
293 * The second bank describes any RAM above 4GiB.
294 *
295 * This split is driven by the following requirements:
296 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
297 * property for memory below and above the 4GiB boundary. The layout of that
298 * DT property is directly driven by the entries in the U-Boot bank array.
299 * - The potential existence of a carve-out at the end of RAM below 4GiB can
300 * only be represented using multiple banks.
301 *
302 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
303 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
304 * command-line.
305 *
306 * This does mean that the DT U-Boot passes to the Linux kernel will not
307 * include this RAM in /memory/reg at all. An alternative would be to include
308 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
309 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
310 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
311 * mapping, so either way is acceptable.
312 *
313 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
314 * start address of that bank cannot be represented in the 32-bit .size
315 * field.
316 */
Simon Glass2f949c32017-03-31 08:40:32 -0600317int dram_init_banksize(void)
Stephen Warren3ffd0902015-08-07 16:12:45 -0600318{
319 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
320 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
321
Simon Glass46fcfc12015-11-19 20:27:02 -0700322#ifdef CONFIG_PCI
323 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
324#endif
325
Stephen Warren3ffd0902015-08-07 16:12:45 -0600326#ifdef CONFIG_PHYS_64BIT
327 if (gd->ram_size > SZ_2G) {
328 gd->bd->bi_dram[1].start = 0x100000000;
329 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
330 } else
331#endif
332 {
333 gd->bd->bi_dram[1].start = 0;
334 gd->bd->bi_dram[1].size = 0;
335 }
Simon Glass2f949c32017-03-31 08:40:32 -0600336
337 return 0;
Stephen Warren3ffd0902015-08-07 16:12:45 -0600338}
339
Thierry Reding6d835fa2015-07-27 11:45:24 -0600340/*
341 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
342 * 32-bits of the physical address space. Cap the maximum usable RAM area
343 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
Stephen Warren3ffd0902015-08-07 16:12:45 -0600344 * boundary that most devices can address. Also, don't let U-Boot use any
345 * carve-out, as mentioned above.
Stephen Warren30d19662015-07-29 13:47:58 -0600346 *
Stephen Warren3ffd0902015-08-07 16:12:45 -0600347 * This function is called before dram_init_banksize(), so we can't simply
348 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
Thierry Reding6d835fa2015-07-27 11:45:24 -0600349 */
350ulong board_get_usable_ram_top(ulong total_size)
351{
Stephen Warren3ffd0902015-08-07 16:12:45 -0600352 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
Thierry Reding6d835fa2015-07-27 11:45:24 -0600353}