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git01.mediatek.com / filogic / uboot / c3dc99f2cd71c948a14f1baf6ee347ede220c525 / . / arch / mips / mach-mtmips / Kconfig
blob: 737de2cb8e28b212e75f1ed2d53b43fcfa65b85b [file] [log] [blame]
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]1menu "MediaTek MIPS platforms"
developer89f051b2019-04-30 11:13:58 +0800[diff] [blame]2 depends on ARCH_MTMIPS
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]3
4config SYS_MALLOC_F_LEN
5 default 0x1000
6
7config SYS_SOC
developer89f051b2019-04-30 11:13:58 +0800[diff] [blame]8 default "mt7628" if SOC_MT7628
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]9
developer26f763e2020-04-21 09:28:26 +0200[diff] [blame]10config SYS_DCACHE_SIZE
11 default 32768
12
13config SYS_DCACHE_LINE_SIZE
14 default 32
15
16config SYS_ICACHE_SIZE
17 default 65536
18
19config SYS_ICACHE_LINE_SIZE
20 default 32
21
developer29b37c52020-04-21 09:28:34 +0200[diff] [blame]22config SYS_TEXT_BASE
developer19d572e2020-04-21 09:28:47 +0200[diff] [blame]23 default 0x9c000000 if !SPL
24 default 0x80200000 if SPL
25
26config SPL_TEXT_BASE
developer29b37c52020-04-21 09:28:34 +0200[diff] [blame]27 default 0x9c000000
28
developer19d572e2020-04-21 09:28:47 +0200[diff] [blame]29config SPL_PAYLOAD
30 default "u-boot-lzma.img" if SPL_LZMA
31
32config BUILD_TARGET
33 default "u-boot-with-spl.bin" if SPL
34
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]35choice
36 prompt "MediaTek MIPS SoC select"
37
developer89f051b2019-04-30 11:13:58 +0800[diff] [blame]38config SOC_MT7628
39 bool "MT7628"
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]40 select MIPS_L1_CACHE_SHIFT_5
developer29b37c52020-04-21 09:28:34 +0200[diff] [blame]41 select MIPS_INIT_STACK_IN_SRAM
42 select MIPS_SRAM_INIT
43 select SYS_MIPS_CACHE_INIT_RAM_LOAD
developer591826e2019-09-25 17:45:43 +0800[diff] [blame]44 select PINCTRL_MT7628
45 select MTK_SERIAL
developer3b3015f2020-04-21 09:28:30 +0200[diff] [blame]46 select SYSRESET_RESETCTL
developer19d572e2020-04-21 09:28:47 +0200[diff] [blame]47 select SPL_SEPARATE_BSS if SPL
48 select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
49 select SPL_LOADER_SUPPORT if SPL
50 select SPL_OF_CONTROL if SPL_DM
51 select SPL_SIMPLE_BUS if SPL_DM
52 select SPL_DM_SERIAL if SPL_DM
53 select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT
54 select SPL_SYSRESET if SPL_DM
55 select SPL_OF_LIBFDT if SPL_OF_CONTROL
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]56 help
developer89f051b2019-04-30 11:13:58 +0800[diff] [blame]57 This supports MediaTek MT7628/MT7688.
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]58
59endchoice
60
61choice
62 prompt "Board select"
63
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]64config BOARD_GARDENA_SMART_GATEWAY_MT7688
Stefan Roesef08cc082019-03-15 09:09:34 +0100[diff] [blame]65 bool "GARDENA smart Gateway"
developer89f051b2019-04-30 11:13:58 +0800[diff] [blame]66 depends on SOC_MT7628
Stefan Roesed0fdd672018-10-09 08:59:13 +0200[diff] [blame]67 select BOARD_LATE_INIT
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]68 help
Stefan Roesef08cc082019-03-15 09:09:34 +0100[diff] [blame]69 GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]70 and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
71
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]72config BOARD_LINKIT_SMART_7688
73 bool "LinkIt Smart 7688"
developer89f051b2019-04-30 11:13:58 +0800[diff] [blame]74 depends on SOC_MT7628
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]75 help
76 Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM
77 and 32 MiB of flash (SPI).
78 Between its different peripherals there's an integrated switch with 4
79 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
80 a MT7688 (PCIe).
81
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]82config BOARD_MT7628_RFB
83 bool "MediaTek MT7628 RFB"
84 depends on SOC_MT7628
85 help
86 The reference design of MT7628. The board has 128 MiB DDR2, 8 MiB
87 SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host,
88 1 SDXC, 1 PCIe socket and JTAG pins.
89
Mauro Condarelli83ae2ce2020-02-18 09:34:48 +0100[diff] [blame]90config BOARD_VOCORE2
91 bool "VoCore2"
92 depends on SOC_MT7628
93 select SPL_SERIAL_SUPPORT
94 select SPL_UART2_SPIS_PINMUX
95 help
96 VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM
97 and 16 MiB of flash (SPI).
98
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]99endchoice
100
developer19d572e2020-04-21 09:28:47 +0200[diff] [blame]101config SPL_UART2_SPIS_PINMUX
102 bool "Use alternative pinmux for UART2 in SPL stage"
103 depends on SPL_SERIAL_SUPPORT
104 default n
105 help
106 Select this if the UART2 of your board is connected to GPIO 16/17
107 (shared with SPIS) rather than the usual GPIO 20/21.
108
Stefan Roese115802d2018-08-16 15:27:31 +0200[diff] [blame]109source "board/gardena/smart-gateway-mt7688/Kconfig"
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]110source "board/mediatek/mt7628/Kconfig"
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]111source "board/seeed/linkit-smart-7688/Kconfig"
Mauro Condarelli83ae2ce2020-02-18 09:34:48 +0100[diff] [blame]112source "board/vocore/vocore2/Kconfig"
Stefan Roese2052a932018-08-16 15:27:30 +0200[diff] [blame]113
Stefan Roese65da15e2018-09-05 15:12:35 +0200[diff] [blame]114endmenu