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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbell6efe3692014-05-05 11:52:26 +01002/*
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 *
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * Some init for sunxi platform.
Ian Campbell6efe3692014-05-05 11:52:26 +010010 */
11
12#include <common.h>
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +020013#include <mmc.h>
Hans de Goede3352b222014-06-13 22:55:49 +020014#include <i2c.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010015#include <serial.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010016#include <spl.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010017#include <asm/gpio.h>
18#include <asm/io.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/gpio.h>
Bernhard Nortmannead498a2015-09-17 18:52:52 +020021#include <asm/arch/spl.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010022#include <asm/arch/sys_proto.h>
23#include <asm/arch/timer.h>
Chen-Yu Tsaifcc7b702015-08-25 10:49:19 +080024#include <asm/arch/tzpc.h>
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +020025#include <asm/arch/mmc.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010026
Ian Campbelld41e2f672014-07-06 20:03:20 +010027#include <linux/compiler.h>
28
Simon Glass5debe1f2015-02-07 10:47:30 -070029struct fel_stash {
30 uint32_t sp;
31 uint32_t lr;
Siarhei Siamashka7ef91f02015-02-16 10:23:59 +020032 uint32_t cpsr;
33 uint32_t sctlr;
34 uint32_t vbar;
35 uint32_t cr;
Simon Glass5debe1f2015-02-07 10:47:30 -070036};
37
38struct fel_stash fel_stash __attribute__((section(".data")));
39
Andre Przywara3a63c232017-02-16 01:20:24 +000040#ifdef CONFIG_ARM64
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +020041#include <asm/armv8/mmu.h>
42
43static struct mm_region sunxi_mem_map[] = {
44 {
45 /* SRAM, MMIO regions */
York Sunc7104e52016-06-24 16:46:22 -070046 .virt = 0x0UL,
47 .phys = 0x0UL,
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +020048 .size = 0x40000000UL,
49 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
50 PTE_BLOCK_NON_SHARE
51 }, {
52 /* RAM */
York Sunc7104e52016-06-24 16:46:22 -070053 .virt = 0x40000000UL,
54 .phys = 0x40000000UL,
Icenowy Zheng9bc6bec2018-10-25 17:23:05 +080055 .size = 0xC0000000UL,
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +020056 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
57 PTE_BLOCK_INNER_SHARE
58 }, {
59 /* List terminator */
60 0,
61 }
62};
63struct mm_region *mem_map = sunxi_mem_map;
64#endif
65
Simon Glass87356822014-12-23 12:04:52 -070066static int gpio_init(void)
Ian Campbell6efe3692014-05-05 11:52:26 +010067{
Icenowy Zheng112c8862019-04-24 13:44:12 +080068 __maybe_unused uint val;
Chen-Yu Tsaid4ea92b2014-10-22 16:47:42 +080069#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
Chen-Yu Tsaicc2605e2016-11-30 14:57:32 +080070#if defined(CONFIG_MACH_SUN4I) || \
71 defined(CONFIG_MACH_SUN7I) || \
72 defined(CONFIG_MACH_SUN8I_R40)
Chen-Yu Tsaid4ea92b2014-10-22 16:47:42 +080073 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
74 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
75 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
76#endif
Chen-Yu Tsaicc2605e2016-11-30 14:57:32 +080077#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
Chen-Yu Tsaida2f3332015-06-23 19:57:23 +080078 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
79 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
Paul Kocialkowskiae358a42015-03-22 18:12:22 +010080#else
Chen-Yu Tsaida2f3332015-06-23 19:57:23 +080081 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
82 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
Paul Kocialkowskiae358a42015-03-22 18:12:22 +010083#endif
Chen-Yu Tsaid4ea92b2014-10-22 16:47:42 +080084 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
Chen-Yu Tsaicc2605e2016-11-30 14:57:32 +080085#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
86 defined(CONFIG_MACH_SUN7I) || \
87 defined(CONFIG_MACH_SUN8I_R40))
Paul Kocialkowskiae358a42015-03-22 18:12:22 +010088 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
Chen-Yu Tsai4e526e22014-10-03 20:16:21 +080090 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
Ian Campbell8f32aaa2014-10-24 21:20:47 +010091#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +010092 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
Chen-Yu Tsai4e526e22014-10-03 20:16:21 +080094 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
Ian Campbell8f32aaa2014-10-24 21:20:47 +010095#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +010096 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
Maxime Ripardf139f1e2014-10-03 20:16:28 +080098 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
Chen-Yu Tsai28b71922015-06-23 19:57:25 +080099#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
100 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
102 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Andre Przywara5fb97432017-02-16 01:20:27 +0000103#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
Jens Kuskef9770722015-11-17 15:12:58 +0100104 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
106 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200107#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
110 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
Icenowy Zhenga78bb072018-07-21 16:20:28 +0800111#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
112 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
114 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
vishnupatekar133bfbe2015-11-29 01:07:20 +0800115#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
116 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
117 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
118 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
Icenowy Zheng52e61882017-04-08 15:30:12 +0800119#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
120 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
121 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
122 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100123#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
124 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
125 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
126 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
Ian Campbell8f32aaa2014-10-24 21:20:47 +0100127#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100128 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
129 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
Chen-Yu Tsai4e526e22014-10-03 20:16:21 +0800130 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
Laurent Itti20dfe002015-05-05 17:02:00 -0700131#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
132 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
133 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
134 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Ian Campbell8f32aaa2014-10-24 21:20:47 +0100135#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100136 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
137 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
Chen-Yu Tsai6ee63882014-10-22 16:47:47 +0800138 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
Hans de Goede8c1c7822014-06-09 11:36:58 +0200139#else
140#error Unsupported console port number. Please fix pin mux settings in board.c
141#endif
Ian Campbell6efe3692014-05-05 11:52:26 +0100142
Icenowy Zheng112c8862019-04-24 13:44:12 +0800143#ifdef CONFIG_MACH_SUN50I_H6
144 /* Update PIO power bias configuration by copy hardware detected value */
145 val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
146 writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
147 val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
148 writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
149#endif
150
Ian Campbell6efe3692014-05-05 11:52:26 +0100151 return 0;
152}
Simon Glass87356822014-12-23 12:04:52 -0700153
Andre Przywaraa563adc2017-01-02 11:48:45 +0000154#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
Simon Glassee306792016-09-24 18:20:13 -0600155static int spl_board_load_image(struct spl_image_info *spl_image,
156 struct spl_boot_device *bootdev)
Simon Glass5debe1f2015-02-07 10:47:30 -0700157{
158 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
159 return_to_fel(fel_stash.sp, fel_stash.lr);
Nikita Kiryanov33eefe42015-11-08 17:11:49 +0200160
161 return 0;
Simon Glass5debe1f2015-02-07 10:47:30 -0700162}
Simon Glass4fc1f252016-11-30 15:30:50 -0700163SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
Simon Glassa4996482016-09-24 18:20:12 -0600164#endif
Simon Glass5debe1f2015-02-07 10:47:30 -0700165
Hans de Goedeb42b04d2015-01-21 16:24:05 +0100166void s_init(void)
Simon Glass87356822014-12-23 12:04:52 -0700167{
Hans de Goedeb88d0ab2016-03-04 10:57:34 +0100168 /*
169 * Undocumented magic taken from boot0, without this DRAM
170 * access gets messed up (seems cache related).
171 * The boot0 sources describe this as: "config ema for cache sram"
172 */
173#if defined CONFIG_MACH_SUN6I
Simon Glass87356822014-12-23 12:04:52 -0700174 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
Hans de Goedec62f8da2016-03-24 22:37:08 +0100175#elif defined CONFIG_MACH_SUN8I
176 __maybe_unused uint version;
Hans de Goedeb88d0ab2016-03-04 10:57:34 +0100177
178 /* Unlock sram version info reg, read it, relock */
179 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
Hans de Goedec62f8da2016-03-24 22:37:08 +0100180 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
Hans de Goedeb88d0ab2016-03-04 10:57:34 +0100181 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
182
Hans de Goedec62f8da2016-03-24 22:37:08 +0100183 /*
184 * Ideally this would be a switch case, but we do not know exactly
185 * which versions there are and which version needs which settings,
186 * so reproduce the per SoC code from the BSP.
187 */
188#if defined CONFIG_MACH_SUN8I_A23
189 if (version == 0x1650)
Hans de Goedeb88d0ab2016-03-04 10:57:34 +0100190 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
191 else /* 0x1661 ? */
192 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
Hans de Goedec62f8da2016-03-24 22:37:08 +0100193#elif defined CONFIG_MACH_SUN8I_A33
194 if (version != 0x1667)
195 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
196#endif
197 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
198 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
Simon Glass87356822014-12-23 12:04:52 -0700199#endif
Hans de Goedeb88d0ab2016-03-04 10:57:34 +0100200
Andre Przywara4330eb92017-02-16 01:20:21 +0000201#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
Simon Glass87356822014-12-23 12:04:52 -0700202 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
203 asm volatile(
204 "mrc p15, 0, r0, c1, c0, 1\n"
205 "orr r0, r0, #1 << 6\n"
Andre Przywaracd975a42017-02-16 01:20:18 +0000206 "mcr p15, 0, r0, c1, c0, 1\n"
207 ::: "r0");
Simon Glass87356822014-12-23 12:04:52 -0700208#endif
Chen-Yu Tsai0932b632016-01-06 15:13:06 +0800209#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
210 /* Enable non-secure access to some peripherals */
Chen-Yu Tsaifcc7b702015-08-25 10:49:19 +0800211 tzpc_init();
212#endif
Simon Glass87356822014-12-23 12:04:52 -0700213
214 clock_init();
215 timer_init();
216 gpio_init();
Jernej Skrabec9220d502017-04-27 00:03:36 +0200217#ifndef CONFIG_DM_I2C
Simon Glass87356822014-12-23 12:04:52 -0700218 i2c_init_board();
Jernej Skrabec9220d502017-04-27 00:03:36 +0200219#endif
Hans de Goede42cbbe32016-03-17 13:53:03 +0100220 eth_init_board();
Hans de Goedeb42b04d2015-01-21 16:24:05 +0100221}
Simon Glass87356822014-12-23 12:04:52 -0700222
Hans de Goedeb42b04d2015-01-21 16:24:05 +0100223/* The sunxi internal brom will try to loader external bootloader
224 * from mmc0, nand flash, mmc2.
Hans de Goedeb42b04d2015-01-21 16:24:05 +0100225 */
Maxime Ripard1941be82017-08-23 10:06:30 +0200226uint32_t sunxi_get_boot_device(void)
Hans de Goedeb42b04d2015-01-21 16:24:05 +0100227{
Hans de Goede6527fa22016-07-09 15:31:47 +0200228 int boot_source;
229
Siarhei Siamashka7ef91f02015-02-16 10:23:59 +0200230 /*
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +0200231 * When booting from the SD card or NAND memory, the "eGON.BT0"
232 * signature is expected to be found in memory at the address 0x0004
233 * (see the "mksunxiboot" tool, which generates this header).
Siarhei Siamashka7ef91f02015-02-16 10:23:59 +0200234 *
235 * When booting in the FEL mode over USB, this signature is patched in
236 * memory and replaced with something else by the 'fel' tool. This other
237 * signature is selected in such a way, that it can't be present in a
238 * valid bootable SD card image (because the BROM would refuse to
239 * execute the SPL in this case).
240 *
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +0200241 * This checks for the signature and if it is not found returns to
242 * the FEL code in the BROM to wait and receive the main u-boot
243 * binary over USB. If it is found, it determines where SPL was
244 * read from.
Siarhei Siamashka7ef91f02015-02-16 10:23:59 +0200245 */
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200246 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
Simon Glass5debe1f2015-02-07 10:47:30 -0700247 return BOOT_DEVICE_BOARD;
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +0200248
Hans de Goede6527fa22016-07-09 15:31:47 +0200249 boot_source = readb(SPL_ADDR + 0x28);
250 switch (boot_source) {
251 case SUNXI_BOOTED_FROM_MMC0:
Andre Przywara946e9db2018-12-16 02:04:58 +0000252 case SUNXI_BOOTED_FROM_MMC0_HIGH:
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +0200253 return BOOT_DEVICE_MMC1;
Hans de Goede6527fa22016-07-09 15:31:47 +0200254 case SUNXI_BOOTED_FROM_NAND:
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +0200255 return BOOT_DEVICE_NAND;
Hans de Goede6527fa22016-07-09 15:31:47 +0200256 case SUNXI_BOOTED_FROM_MMC2:
Andre Przywara946e9db2018-12-16 02:04:58 +0000257 case SUNXI_BOOTED_FROM_MMC2_HIGH:
Hans de Goede6527fa22016-07-09 15:31:47 +0200258 return BOOT_DEVICE_MMC2;
259 case SUNXI_BOOTED_FROM_SPI:
260 return BOOT_DEVICE_SPI;
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +0200261 }
262
Hans de Goede6527fa22016-07-09 15:31:47 +0200263 panic("Unknown boot source %d\n", boot_source);
Daniel Kochmańskie8b97e22015-05-29 16:55:42 +0200264 return -1; /* Never reached */
Hans de Goedeb42b04d2015-01-21 16:24:05 +0100265}
266
Maxime Ripard1941be82017-08-23 10:06:30 +0200267#ifdef CONFIG_SPL_BUILD
268u32 spl_boot_device(void)
269{
270 return sunxi_get_boot_device();
271}
272
Hans de Goedeb42b04d2015-01-21 16:24:05 +0100273void board_init_f(ulong dummy)
274{
Hans de Goede76fa0b22015-09-13 12:31:24 +0200275 spl_init();
Simon Glass87356822014-12-23 12:04:52 -0700276 preloader_console_init();
277
278#ifdef CONFIG_SPL_I2C_SUPPORT
279 /* Needed early by sunxi_board_init if PMU is enabled */
280 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
281#endif
282 sunxi_board_init();
Simon Glass87356822014-12-23 12:04:52 -0700283}
284#endif
Ian Campbell6efe3692014-05-05 11:52:26 +0100285
286void reset_cpu(ulong addr)
287{
Chen-Yu Tsai84f3bb42016-11-30 16:27:14 +0800288#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
Hans de Goede1374e892014-06-09 11:36:56 +0200289 static const struct sunxi_wdog *wdog =
290 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
291
292 /* Set the watchdog for its shortest interval (.5s) and wait */
293 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
294 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedefa43a6e2014-06-13 22:55:52 +0200295
296 while (1) {
297 /* sun5i sometimes gets stuck without this */
298 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
299 }
Icenowy Zheng5a76cdd2018-07-21 16:20:27 +0800300#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
Clément Péron33445442019-04-17 19:41:05 +0200301#if defined(CONFIG_MACH_SUN50I_H6)
302 /* WDOG is broken for some H6 rev. use the R_WDOG instead */
303 static const struct sunxi_wdog *wdog =
304 (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
305#else
Chen-Yu Tsai1275c482014-10-04 20:37:28 +0800306 static const struct sunxi_wdog *wdog =
Clément Péron33445442019-04-17 19:41:05 +0200307 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
308#endif
Chen-Yu Tsai1275c482014-10-04 20:37:28 +0800309 /* Set the watchdog for its shortest interval (.5s) and wait */
310 writel(WDT_CFG_RESET, &wdog->cfg);
311 writel(WDT_MODE_EN, &wdog->mode);
312 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedeb25d3c92015-06-14 16:53:15 +0200313 while (1) { }
Chen-Yu Tsai1275c482014-10-04 20:37:28 +0800314#endif
Ian Campbell6efe3692014-05-05 11:52:26 +0100315}
316
Trevor Woerner43ec7e02019-05-03 09:41:00 -0400317#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
Ian Campbell6efe3692014-05-05 11:52:26 +0100318void enable_caches(void)
319{
320 /* Enable D-cache. I-cache is already enabled in start.S */
321 dcache_enable();
322}
323#endif