Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> |
| 4 | * |
| 5 | * (C) Copyright 2007-2011 |
| 6 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 7 | * Tom Cubie <tangliang@allwinnertech.com> |
| 8 | * |
| 9 | * Some init for sunxi platform. |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 13 | #include <mmc.h> |
Hans de Goede | 3352b22 | 2014-06-13 22:55:49 +0200 | [diff] [blame] | 14 | #include <i2c.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 15 | #include <serial.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 16 | #include <spl.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 17 | #include <asm/gpio.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <asm/arch/clock.h> |
| 20 | #include <asm/arch/gpio.h> |
Bernhard Nortmann | ead498a | 2015-09-17 18:52:52 +0200 | [diff] [blame] | 21 | #include <asm/arch/spl.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 22 | #include <asm/arch/sys_proto.h> |
| 23 | #include <asm/arch/timer.h> |
Chen-Yu Tsai | fcc7b70 | 2015-08-25 10:49:19 +0800 | [diff] [blame] | 24 | #include <asm/arch/tzpc.h> |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 25 | #include <asm/arch/mmc.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 26 | |
Ian Campbell | d41e2f67 | 2014-07-06 20:03:20 +0100 | [diff] [blame] | 27 | #include <linux/compiler.h> |
| 28 | |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 29 | struct fel_stash { |
| 30 | uint32_t sp; |
| 31 | uint32_t lr; |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 32 | uint32_t cpsr; |
| 33 | uint32_t sctlr; |
| 34 | uint32_t vbar; |
| 35 | uint32_t cr; |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 36 | }; |
| 37 | |
| 38 | struct fel_stash fel_stash __attribute__((section(".data"))); |
| 39 | |
Andre Przywara | 3a63c23 | 2017-02-16 01:20:24 +0000 | [diff] [blame] | 40 | #ifdef CONFIG_ARM64 |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 41 | #include <asm/armv8/mmu.h> |
| 42 | |
| 43 | static struct mm_region sunxi_mem_map[] = { |
| 44 | { |
| 45 | /* SRAM, MMIO regions */ |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 46 | .virt = 0x0UL, |
| 47 | .phys = 0x0UL, |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 48 | .size = 0x40000000UL, |
| 49 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 50 | PTE_BLOCK_NON_SHARE |
| 51 | }, { |
| 52 | /* RAM */ |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 53 | .virt = 0x40000000UL, |
| 54 | .phys = 0x40000000UL, |
Icenowy Zheng | 9bc6bec | 2018-10-25 17:23:05 +0800 | [diff] [blame] | 55 | .size = 0xC0000000UL, |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 56 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 57 | PTE_BLOCK_INNER_SHARE |
| 58 | }, { |
| 59 | /* List terminator */ |
| 60 | 0, |
| 61 | } |
| 62 | }; |
| 63 | struct mm_region *mem_map = sunxi_mem_map; |
| 64 | #endif |
| 65 | |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 66 | static int gpio_init(void) |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 67 | { |
Icenowy Zheng | 112c886 | 2019-04-24 13:44:12 +0800 | [diff] [blame] | 68 | __maybe_unused uint val; |
Chen-Yu Tsai | d4ea92b | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 69 | #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 70 | #if defined(CONFIG_MACH_SUN4I) || \ |
| 71 | defined(CONFIG_MACH_SUN7I) || \ |
| 72 | defined(CONFIG_MACH_SUN8I_R40) |
Chen-Yu Tsai | d4ea92b | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 73 | /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ |
| 74 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); |
| 75 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); |
| 76 | #endif |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 77 | #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40) |
Chen-Yu Tsai | da2f333 | 2015-06-23 19:57:23 +0800 | [diff] [blame] | 78 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); |
| 79 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 80 | #else |
Chen-Yu Tsai | da2f333 | 2015-06-23 19:57:23 +0800 | [diff] [blame] | 81 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); |
| 82 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 83 | #endif |
Chen-Yu Tsai | d4ea92b | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 84 | sunxi_gpio_set_pull(SUNXI_GPF(4), 1); |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 85 | #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ |
| 86 | defined(CONFIG_MACH_SUN7I) || \ |
| 87 | defined(CONFIG_MACH_SUN8I_R40)) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 88 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); |
| 89 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 90 | sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 91 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 92 | sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); |
| 93 | sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 94 | sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 95 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 96 | sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); |
| 97 | sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); |
Maxime Ripard | f139f1e | 2014-10-03 20:16:28 +0800 | [diff] [blame] | 98 | sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); |
Chen-Yu Tsai | 28b7192 | 2015-06-23 19:57:25 +0800 | [diff] [blame] | 99 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) |
| 100 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); |
| 101 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); |
| 102 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); |
Andre Przywara | 5fb9743 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 103 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) |
Jens Kuske | f977072 | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 104 | sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); |
| 105 | sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); |
| 106 | sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 107 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) |
| 108 | sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); |
| 109 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); |
| 110 | sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); |
Icenowy Zheng | a78bb07 | 2018-07-21 16:20:28 +0800 | [diff] [blame] | 111 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6) |
| 112 | sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); |
| 113 | sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); |
| 114 | sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); |
vishnupatekar | 133bfbe | 2015-11-29 01:07:20 +0800 | [diff] [blame] | 115 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) |
| 116 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); |
| 117 | sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); |
| 118 | sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); |
Icenowy Zheng | 52e6188 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 119 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) |
| 120 | sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); |
| 121 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); |
| 122 | sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); |
Hans de Goede | 7bfe2bb | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 123 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) |
| 124 | sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); |
| 125 | sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); |
| 126 | sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 127 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 128 | sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); |
| 129 | sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 130 | sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); |
Laurent Itti | 20dfe00 | 2015-05-05 17:02:00 -0700 | [diff] [blame] | 131 | #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) |
| 132 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); |
| 133 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); |
| 134 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 135 | #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 136 | sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); |
| 137 | sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); |
Chen-Yu Tsai | 6ee6388 | 2014-10-22 16:47:47 +0800 | [diff] [blame] | 138 | sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); |
Hans de Goede | 8c1c782 | 2014-06-09 11:36:58 +0200 | [diff] [blame] | 139 | #else |
| 140 | #error Unsupported console port number. Please fix pin mux settings in board.c |
| 141 | #endif |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 142 | |
Icenowy Zheng | 112c886 | 2019-04-24 13:44:12 +0800 | [diff] [blame] | 143 | #ifdef CONFIG_MACH_SUN50I_H6 |
| 144 | /* Update PIO power bias configuration by copy hardware detected value */ |
| 145 | val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); |
| 146 | writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); |
| 147 | val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); |
| 148 | writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); |
| 149 | #endif |
| 150 | |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 151 | return 0; |
| 152 | } |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 153 | |
Andre Przywara | a563adc | 2017-01-02 11:48:45 +0000 | [diff] [blame] | 154 | #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD) |
Simon Glass | ee30679 | 2016-09-24 18:20:13 -0600 | [diff] [blame] | 155 | static int spl_board_load_image(struct spl_image_info *spl_image, |
| 156 | struct spl_boot_device *bootdev) |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 157 | { |
| 158 | debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); |
| 159 | return_to_fel(fel_stash.sp, fel_stash.lr); |
Nikita Kiryanov | 33eefe4 | 2015-11-08 17:11:49 +0200 | [diff] [blame] | 160 | |
| 161 | return 0; |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 162 | } |
Simon Glass | 4fc1f25 | 2016-11-30 15:30:50 -0700 | [diff] [blame] | 163 | SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); |
Simon Glass | a499648 | 2016-09-24 18:20:12 -0600 | [diff] [blame] | 164 | #endif |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 165 | |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 166 | void s_init(void) |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 167 | { |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 168 | /* |
| 169 | * Undocumented magic taken from boot0, without this DRAM |
| 170 | * access gets messed up (seems cache related). |
| 171 | * The boot0 sources describe this as: "config ema for cache sram" |
| 172 | */ |
| 173 | #if defined CONFIG_MACH_SUN6I |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 174 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); |
Hans de Goede | c62f8da | 2016-03-24 22:37:08 +0100 | [diff] [blame] | 175 | #elif defined CONFIG_MACH_SUN8I |
| 176 | __maybe_unused uint version; |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 177 | |
| 178 | /* Unlock sram version info reg, read it, relock */ |
| 179 | setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); |
Hans de Goede | c62f8da | 2016-03-24 22:37:08 +0100 | [diff] [blame] | 180 | version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 181 | clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); |
| 182 | |
Hans de Goede | c62f8da | 2016-03-24 22:37:08 +0100 | [diff] [blame] | 183 | /* |
| 184 | * Ideally this would be a switch case, but we do not know exactly |
| 185 | * which versions there are and which version needs which settings, |
| 186 | * so reproduce the per SoC code from the BSP. |
| 187 | */ |
| 188 | #if defined CONFIG_MACH_SUN8I_A23 |
| 189 | if (version == 0x1650) |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 190 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); |
| 191 | else /* 0x1661 ? */ |
| 192 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); |
Hans de Goede | c62f8da | 2016-03-24 22:37:08 +0100 | [diff] [blame] | 193 | #elif defined CONFIG_MACH_SUN8I_A33 |
| 194 | if (version != 0x1667) |
| 195 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); |
| 196 | #endif |
| 197 | /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ |
| 198 | /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 199 | #endif |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 200 | |
Andre Przywara | 4330eb9 | 2017-02-16 01:20:21 +0000 | [diff] [blame] | 201 | #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 202 | /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ |
| 203 | asm volatile( |
| 204 | "mrc p15, 0, r0, c1, c0, 1\n" |
| 205 | "orr r0, r0, #1 << 6\n" |
Andre Przywara | cd975a4 | 2017-02-16 01:20:18 +0000 | [diff] [blame] | 206 | "mcr p15, 0, r0, c1, c0, 1\n" |
| 207 | ::: "r0"); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 208 | #endif |
Chen-Yu Tsai | 0932b63 | 2016-01-06 15:13:06 +0800 | [diff] [blame] | 209 | #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 |
| 210 | /* Enable non-secure access to some peripherals */ |
Chen-Yu Tsai | fcc7b70 | 2015-08-25 10:49:19 +0800 | [diff] [blame] | 211 | tzpc_init(); |
| 212 | #endif |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 213 | |
| 214 | clock_init(); |
| 215 | timer_init(); |
| 216 | gpio_init(); |
Jernej Skrabec | 9220d50 | 2017-04-27 00:03:36 +0200 | [diff] [blame] | 217 | #ifndef CONFIG_DM_I2C |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 218 | i2c_init_board(); |
Jernej Skrabec | 9220d50 | 2017-04-27 00:03:36 +0200 | [diff] [blame] | 219 | #endif |
Hans de Goede | 42cbbe3 | 2016-03-17 13:53:03 +0100 | [diff] [blame] | 220 | eth_init_board(); |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 221 | } |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 222 | |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 223 | /* The sunxi internal brom will try to loader external bootloader |
| 224 | * from mmc0, nand flash, mmc2. |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 225 | */ |
Maxime Ripard | 1941be8 | 2017-08-23 10:06:30 +0200 | [diff] [blame] | 226 | uint32_t sunxi_get_boot_device(void) |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 227 | { |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 228 | int boot_source; |
| 229 | |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 230 | /* |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 231 | * When booting from the SD card or NAND memory, the "eGON.BT0" |
| 232 | * signature is expected to be found in memory at the address 0x0004 |
| 233 | * (see the "mksunxiboot" tool, which generates this header). |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 234 | * |
| 235 | * When booting in the FEL mode over USB, this signature is patched in |
| 236 | * memory and replaced with something else by the 'fel' tool. This other |
| 237 | * signature is selected in such a way, that it can't be present in a |
| 238 | * valid bootable SD card image (because the BROM would refuse to |
| 239 | * execute the SPL in this case). |
| 240 | * |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 241 | * This checks for the signature and if it is not found returns to |
| 242 | * the FEL code in the BROM to wait and receive the main u-boot |
| 243 | * binary over USB. If it is found, it determines where SPL was |
| 244 | * read from. |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 245 | */ |
Bernhard Nortmann | ead498a | 2015-09-17 18:52:52 +0200 | [diff] [blame] | 246 | if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 247 | return BOOT_DEVICE_BOARD; |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 248 | |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 249 | boot_source = readb(SPL_ADDR + 0x28); |
| 250 | switch (boot_source) { |
| 251 | case SUNXI_BOOTED_FROM_MMC0: |
Andre Przywara | 946e9db | 2018-12-16 02:04:58 +0000 | [diff] [blame] | 252 | case SUNXI_BOOTED_FROM_MMC0_HIGH: |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 253 | return BOOT_DEVICE_MMC1; |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 254 | case SUNXI_BOOTED_FROM_NAND: |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 255 | return BOOT_DEVICE_NAND; |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 256 | case SUNXI_BOOTED_FROM_MMC2: |
Andre Przywara | 946e9db | 2018-12-16 02:04:58 +0000 | [diff] [blame] | 257 | case SUNXI_BOOTED_FROM_MMC2_HIGH: |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 258 | return BOOT_DEVICE_MMC2; |
| 259 | case SUNXI_BOOTED_FROM_SPI: |
| 260 | return BOOT_DEVICE_SPI; |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 261 | } |
| 262 | |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 263 | panic("Unknown boot source %d\n", boot_source); |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 264 | return -1; /* Never reached */ |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 265 | } |
| 266 | |
Maxime Ripard | 1941be8 | 2017-08-23 10:06:30 +0200 | [diff] [blame] | 267 | #ifdef CONFIG_SPL_BUILD |
| 268 | u32 spl_boot_device(void) |
| 269 | { |
| 270 | return sunxi_get_boot_device(); |
| 271 | } |
| 272 | |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 273 | void board_init_f(ulong dummy) |
| 274 | { |
Hans de Goede | 76fa0b2 | 2015-09-13 12:31:24 +0200 | [diff] [blame] | 275 | spl_init(); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 276 | preloader_console_init(); |
| 277 | |
| 278 | #ifdef CONFIG_SPL_I2C_SUPPORT |
| 279 | /* Needed early by sunxi_board_init if PMU is enabled */ |
| 280 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 281 | #endif |
| 282 | sunxi_board_init(); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 283 | } |
| 284 | #endif |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 285 | |
| 286 | void reset_cpu(ulong addr) |
| 287 | { |
Chen-Yu Tsai | 84f3bb4 | 2016-11-30 16:27:14 +0800 | [diff] [blame] | 288 | #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) |
Hans de Goede | 1374e89 | 2014-06-09 11:36:56 +0200 | [diff] [blame] | 289 | static const struct sunxi_wdog *wdog = |
| 290 | &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; |
| 291 | |
| 292 | /* Set the watchdog for its shortest interval (.5s) and wait */ |
| 293 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); |
| 294 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); |
Hans de Goede | fa43a6e | 2014-06-13 22:55:52 +0200 | [diff] [blame] | 295 | |
| 296 | while (1) { |
| 297 | /* sun5i sometimes gets stuck without this */ |
| 298 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); |
| 299 | } |
Icenowy Zheng | 5a76cdd | 2018-07-21 16:20:27 +0800 | [diff] [blame] | 300 | #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) |
Clément Péron | 3344544 | 2019-04-17 19:41:05 +0200 | [diff] [blame] | 301 | #if defined(CONFIG_MACH_SUN50I_H6) |
| 302 | /* WDOG is broken for some H6 rev. use the R_WDOG instead */ |
| 303 | static const struct sunxi_wdog *wdog = |
| 304 | (struct sunxi_wdog *)SUNXI_R_WDOG_BASE; |
| 305 | #else |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 306 | static const struct sunxi_wdog *wdog = |
Clément Péron | 3344544 | 2019-04-17 19:41:05 +0200 | [diff] [blame] | 307 | ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; |
| 308 | #endif |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 309 | /* Set the watchdog for its shortest interval (.5s) and wait */ |
| 310 | writel(WDT_CFG_RESET, &wdog->cfg); |
| 311 | writel(WDT_MODE_EN, &wdog->mode); |
| 312 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); |
Hans de Goede | b25d3c9 | 2015-06-14 16:53:15 +0200 | [diff] [blame] | 313 | while (1) { } |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 314 | #endif |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 315 | } |
| 316 | |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 317 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 318 | void enable_caches(void) |
| 319 | { |
| 320 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 321 | dcache_enable(); |
| 322 | } |
| 323 | #endif |