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git01.mediatek.com / filogic / uboot / bf7c0cee160adfa8cbea76491b51fb492d1bf9ba / . / arch / arm / dts / imx93-phyboard-segin-u-boot.dtsi
blob: 0c3ca2961c98db476f5aae57c547aa46ffa63c12 [file] [log] [blame]
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 * Christoph Stoidner <c.stoidner@phytec.de>
Christoph Stoidnerd2e9fc22024-11-20 17:31:43 +0100[diff] [blame]5 * Copyright (C) 2024 PHYTEC Messtechnik GmbH
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]6 *
7 * Product homepage:
Christoph Stoidnerd2e9fc22024-11-20 17:31:43 +0100[diff] [blame]8 https://www.phytec.de/produkte/system-on-modules/phycore-imx-91-93/
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]9 */
10
11#include "imx93-u-boot.dtsi"
12
13/ {
Christoph Stoidnerd2e9fc22024-11-20 17:31:43 +0100[diff] [blame]14 /*
15 * The phyCORE-i.MX93 u-boot uses the imx93-phyboard-segin.dts as
16 * reference, but does only make use of its SoM (phyCORE) contained
17 * periphery.
18 */
19 model = "PHYTEC phyCORE-i.MX93";
20
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]21 wdt-reboot {
22 compatible = "wdt-reboot";
23 wdt = <&wdog3>;
24 bootph-pre-ram;
25 bootph-some-ram;
26 };
27
28 aliases {
29 ethernet0 = &fec;
30 ethernet1 = &eqos;
31 };
32
33 firmware {
34 optee {
35 compatible = "linaro,optee-tz";
36 method = "smc";
37 };
38 };
39};
40
41&{/soc@0} {
42 bootph-all;
43 bootph-pre-ram;
44};
45
46&aips1 {
47 bootph-pre-ram;
48 bootph-all;
49};
50
51&aips2 {
52 bootph-pre-ram;
53 bootph-some-ram;
54};
55
56&aips3 {
57 bootph-pre-ram;
58 bootph-some-ram;
59};
60
61&iomuxc {
62 bootph-pre-ram;
63 bootph-some-ram;
64};
65
66&reg_usdhc2_vmmc {
67 u-boot,off-on-delay-us = <20000>;
68 bootph-pre-ram;
69 bootph-some-ram;
70};
71
72&pinctrl_reg_usdhc2_vmmc {
73 bootph-pre-ram;
74};
75
76&pinctrl_uart1 {
77 bootph-pre-ram;
78 bootph-some-ram;
79};
80
81&pinctrl_usdhc1 {
82 bootph-pre-ram;
83 bootph-some-ram;
84};
85
86&pinctrl_usdhc2_cd {
87 bootph-pre-ram;
88 bootph-some-ram;
89};
90
91&pinctrl_usdhc2_default {
92 bootph-pre-ram;
93 bootph-some-ram;
94};
95
96&pinctrl_usdhc2_100mhz {
97 bootph-pre-ram;
98 bootph-some-ram;
99};
100
101&pinctrl_usdhc2_200mhz {
102 bootph-pre-ram;
103 bootph-some-ram;
104};
105
106&gpio1 {
107 bootph-pre-ram;
108 bootph-some-ram;
109};
110
111&gpio2 {
112 bootph-pre-ram;
113 bootph-some-ram;
114};
115
116&gpio3 {
117 bootph-pre-ram;
118 bootph-some-ram;
119};
120
121&gpio4 {
122 bootph-pre-ram;
123 bootph-some-ram;
124};
125
126&lpuart1 {
127 bootph-pre-ram;
128 bootph-some-ram;
129};
130
Mathieu Othacehe713df352024-03-21 15:45:39 +0100[diff] [blame]131/*
132 * Remove once USB support is added to imx93-phyboard-segin.dts upstream.
133 */
134&usbotg1 {
135 disable-over-current;
136 dr_mode = "otg";
137 status = "okay";
138};
139
140&usbotg2 {
141 disable-over-current;
142 dr_mode = "host";
143 status = "okay";
144};
145
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]146&usdhc1 {
147 bootph-pre-ram;
148 bootph-some-ram;
Christoph Stoidner5b7d7012024-11-20 17:31:42 +0100[diff] [blame]149 /*
150 * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
151 */
152 pinctrl-names = "default", "state_100mhz", "state_200mhz";
153 pinctrl-0 = <&pinctrl_usdhc1>;
154 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
155 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]156};
157
158&usdhc2 {
159 bootph-pre-ram;
160 bootph-some-ram;
161 fsl,signal-voltage-switch-extra-delay-ms = <8>;
162};
163
164&lpi2c1 {
165 bootph-pre-ram;
166 bootph-some-ram;
167};
168
169&lpi2c2 {
170 bootph-pre-ram;
171 bootph-some-ram;
172};
173
174&lpi2c3 {
175 bootph-pre-ram;
176 bootph-some-ram;
177};
178
179&s4muap {
180 bootph-pre-ram;
181 bootph-some-ram;
182 status = "okay";
183};
184
185&clk {
186 bootph-all;
187 bootph-pre-ram;
188 /delete-property/ assigned-clocks;
189 /delete-property/ assigned-clock-rates;
190 /delete-property/ assigned-clock-parents;
191};
192
193&osc_32k {
194 bootph-all;
195 bootph-pre-ram;
196};
197
198&osc_24m {
199 bootph-all;
200 bootph-pre-ram;
201};
202
203&clk_ext1 {
204 bootph-all;
205 bootph-pre-ram;
206};
207
208&wdog3 {
209 bootph-all;
210 bootph-pre-ram;
211};
212
213/*
214 * The two nodes below won't be needed once nxp,pca9451a
215 * support is added to the Linux kernel.
216 */
217&iomuxc {
218 pinctrl_lpi2c3: lpi2c3grp {
219 bootph-pre-ram;
220 fsl,pins = <
221 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
222 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
223 >;
224 };
225
226 pinctrl_pmic: pmicgrp {
227 bootph-pre-ram;
228 fsl,pins = <
229 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
230 >;
231 };
Christoph Stoidner5b7d7012024-11-20 17:31:42 +0100[diff] [blame]232
233 /*
234 * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
235 * are added to imx93-phycore-som.dtsi
236 */
237 /* need to config the SION for data and cmd pad, refer to ERR052021 */
238 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
239 bootph-pre-ram;
240 bootph-some-ram;
241 fsl,pins = <
242 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
243 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
244 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
245 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
246 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
247 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
248 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
249 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
250 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
251 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
252 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
253 >;
254 };
255
256 /* need to config the SION for data and cmd pad, refer to ERR052021 */
257 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
258 bootph-pre-ram;
259 bootph-some-ram;
260 fsl,pins = <
261 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
262 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
263 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
264 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
265 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
266 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
267 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
268 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
269 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
270 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
271 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
272 >;
273 };
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]274};
275
276&lpi2c3 {
277 bootph-pre-ram;
278 bootph-some-ram;
279 clock-frequency = <400000>;
280 pinctrl-names = "default", "sleep";
281 pinctrl-0 = <&pinctrl_lpi2c3>;
282 pinctrl-1 = <&pinctrl_lpi2c3>;
283 status = "okay";
284
285 pmic@25 {
286 bootph-pre-ram;
287 bootph-some-ram;
288 compatible = "nxp,pca9451a";
289 reg = <0x25>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_pmic>;
292 interrupt-parent = <&gpio4>;
293 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
294
295 regulators {
296 bootph-pre-ram;
297 bootph-some-ram;
298 buck1: BUCK1 {
299 regulator-name = "VDD_SOC";
300 regulator-min-microvolt = <610000>;
301 regulator-max-microvolt = <950000>;
302 regulator-boot-on;
303 regulator-always-on;
304 regulator-ramp-delay = <3125>;
305 };
306
307 buck2: BUCK2 {
308 regulator-name = "VDDQ_0V6";
309 regulator-min-microvolt = <600000>;
310 regulator-max-microvolt = <600000>;
311 regulator-boot-on;
312 regulator-always-on;
313 };
314
315 buck4: BUCK4 {
316 regulator-name = "VDD_3V3_BUCK";
317 regulator-min-microvolt = <3300000>;
318 regulator-max-microvolt = <3300000>;
319 regulator-boot-on;
320 regulator-always-on;
321 };
322
323 buck5: BUCK5 {
324 regulator-name = "VDD_1V8";
325 regulator-min-microvolt = <1800000>;
326 regulator-max-microvolt = <1800000>;
327 regulator-boot-on;
328 regulator-always-on;
329 };
330
331 buck6: BUCK6 {
332 regulator-name = "VDD_1V1";
333 regulator-min-microvolt = <1100000>;
334 regulator-max-microvolt = <1100000>;
335 regulator-boot-on;
336 regulator-always-on;
337 };
338
339 ldo1: LDO1 {
340 regulator-name = "PMIC_SNVS_1V8";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <1800000>;
343 regulator-boot-on;
344 regulator-always-on;
345 };
346
347 ldo4: LDO4 {
348 regulator-name = "VDD_0V8";
349 regulator-min-microvolt = <800000>;
350 regulator-max-microvolt = <800000>;
351 regulator-boot-on;
352 regulator-always-on;
353 };
354
355 ldo5: LDO5 {
356 regulator-name = "NVCC_SD2";
357 regulator-min-microvolt = <1800000>;
358 regulator-max-microvolt = <3300000>;
359 regulator-boot-on;
360 regulator-always-on;
361 };
362 };
363 };
Christoph Stoidner5b7d7012024-11-20 17:31:42 +0100[diff] [blame]364
365 eeprom@50 {
366 bootph-pre-ram;
367 bootph-some-ram;
368 compatible = "atmel,24c32";
369 reg = <0x50>;
370 pagesize = <32>;
371 vcc-supply = <&buck4>;
372 };
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]373};