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git01.mediatek.com / filogic / uboot / 9bfca75e8d166b06bf6417370e29b0f15e38a670 / . / arch / arm / dts / imx93-phyboard-segin-u-boot.dtsi
blob: 8bf28c2de87c86dc89015224644c531e25974315 [file] [log] [blame]
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 * Christoph Stoidner <c.stoidner@phytec.de>
5 *
6 * Product homepage:
7 * phyBOARD-Segin carrier board is reused for the i.MX93 design.
8 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
9 */
10
11#include "imx93-u-boot.dtsi"
12
13/ {
14 wdt-reboot {
15 compatible = "wdt-reboot";
16 wdt = <&wdog3>;
17 bootph-pre-ram;
18 bootph-some-ram;
19 };
20
21 aliases {
22 ethernet0 = &fec;
23 ethernet1 = &eqos;
24 };
25
26 firmware {
27 optee {
28 compatible = "linaro,optee-tz";
29 method = "smc";
30 };
31 };
32};
33
34&{/soc@0} {
35 bootph-all;
36 bootph-pre-ram;
37};
38
39&aips1 {
40 bootph-pre-ram;
41 bootph-all;
42};
43
44&aips2 {
45 bootph-pre-ram;
46 bootph-some-ram;
47};
48
49&aips3 {
50 bootph-pre-ram;
51 bootph-some-ram;
52};
53
54&iomuxc {
55 bootph-pre-ram;
56 bootph-some-ram;
57};
58
59&reg_usdhc2_vmmc {
60 u-boot,off-on-delay-us = <20000>;
61 bootph-pre-ram;
62 bootph-some-ram;
63};
64
65&pinctrl_reg_usdhc2_vmmc {
66 bootph-pre-ram;
67};
68
69&pinctrl_uart1 {
70 bootph-pre-ram;
71 bootph-some-ram;
72};
73
74&pinctrl_usdhc1 {
75 bootph-pre-ram;
76 bootph-some-ram;
77};
78
79&pinctrl_usdhc2_cd {
80 bootph-pre-ram;
81 bootph-some-ram;
82};
83
84&pinctrl_usdhc2_default {
85 bootph-pre-ram;
86 bootph-some-ram;
87};
88
89&pinctrl_usdhc2_100mhz {
90 bootph-pre-ram;
91 bootph-some-ram;
92};
93
94&pinctrl_usdhc2_200mhz {
95 bootph-pre-ram;
96 bootph-some-ram;
97};
98
99&gpio1 {
100 bootph-pre-ram;
101 bootph-some-ram;
102};
103
104&gpio2 {
105 bootph-pre-ram;
106 bootph-some-ram;
107};
108
109&gpio3 {
110 bootph-pre-ram;
111 bootph-some-ram;
112};
113
114&gpio4 {
115 bootph-pre-ram;
116 bootph-some-ram;
117};
118
119&lpuart1 {
120 bootph-pre-ram;
121 bootph-some-ram;
122};
123
124&usdhc1 {
125 bootph-pre-ram;
126 bootph-some-ram;
127};
128
129&usdhc2 {
130 bootph-pre-ram;
131 bootph-some-ram;
132 fsl,signal-voltage-switch-extra-delay-ms = <8>;
133};
134
135&lpi2c1 {
136 bootph-pre-ram;
137 bootph-some-ram;
138};
139
140&lpi2c2 {
141 bootph-pre-ram;
142 bootph-some-ram;
143};
144
145&lpi2c3 {
146 bootph-pre-ram;
147 bootph-some-ram;
148};
149
150&s4muap {
151 bootph-pre-ram;
152 bootph-some-ram;
153 status = "okay";
154};
155
156&clk {
157 bootph-all;
158 bootph-pre-ram;
159 /delete-property/ assigned-clocks;
160 /delete-property/ assigned-clock-rates;
161 /delete-property/ assigned-clock-parents;
162};
163
164&osc_32k {
165 bootph-all;
166 bootph-pre-ram;
167};
168
169&osc_24m {
170 bootph-all;
171 bootph-pre-ram;
172};
173
174&clk_ext1 {
175 bootph-all;
176 bootph-pre-ram;
177};
178
179&wdog3 {
180 bootph-all;
181 bootph-pre-ram;
182};
183
184/*
185 * The two nodes below won't be needed once nxp,pca9451a
186 * support is added to the Linux kernel.
187 */
188&iomuxc {
189 pinctrl_lpi2c3: lpi2c3grp {
190 bootph-pre-ram;
191 fsl,pins = <
192 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
193 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
194 >;
195 };
196
197 pinctrl_pmic: pmicgrp {
198 bootph-pre-ram;
199 fsl,pins = <
200 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
201 >;
202 };
203};
204
205&lpi2c3 {
206 bootph-pre-ram;
207 bootph-some-ram;
208 clock-frequency = <400000>;
209 pinctrl-names = "default", "sleep";
210 pinctrl-0 = <&pinctrl_lpi2c3>;
211 pinctrl-1 = <&pinctrl_lpi2c3>;
212 status = "okay";
213
214 pmic@25 {
215 bootph-pre-ram;
216 bootph-some-ram;
217 compatible = "nxp,pca9451a";
218 reg = <0x25>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_pmic>;
221 interrupt-parent = <&gpio4>;
222 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
223
224 regulators {
225 bootph-pre-ram;
226 bootph-some-ram;
227 buck1: BUCK1 {
228 regulator-name = "VDD_SOC";
229 regulator-min-microvolt = <610000>;
230 regulator-max-microvolt = <950000>;
231 regulator-boot-on;
232 regulator-always-on;
233 regulator-ramp-delay = <3125>;
234 };
235
236 buck2: BUCK2 {
237 regulator-name = "VDDQ_0V6";
238 regulator-min-microvolt = <600000>;
239 regulator-max-microvolt = <600000>;
240 regulator-boot-on;
241 regulator-always-on;
242 };
243
244 buck4: BUCK4 {
245 regulator-name = "VDD_3V3_BUCK";
246 regulator-min-microvolt = <3300000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-boot-on;
249 regulator-always-on;
250 };
251
252 buck5: BUCK5 {
253 regulator-name = "VDD_1V8";
254 regulator-min-microvolt = <1800000>;
255 regulator-max-microvolt = <1800000>;
256 regulator-boot-on;
257 regulator-always-on;
258 };
259
260 buck6: BUCK6 {
261 regulator-name = "VDD_1V1";
262 regulator-min-microvolt = <1100000>;
263 regulator-max-microvolt = <1100000>;
264 regulator-boot-on;
265 regulator-always-on;
266 };
267
268 ldo1: LDO1 {
269 regulator-name = "PMIC_SNVS_1V8";
270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <1800000>;
272 regulator-boot-on;
273 regulator-always-on;
274 };
275
276 ldo4: LDO4 {
277 regulator-name = "VDD_0V8";
278 regulator-min-microvolt = <800000>;
279 regulator-max-microvolt = <800000>;
280 regulator-boot-on;
281 regulator-always-on;
282 };
283
284 ldo5: LDO5 {
285 regulator-name = "NVCC_SD2";
286 regulator-min-microvolt = <1800000>;
287 regulator-max-microvolt = <3300000>;
288 regulator-boot-on;
289 regulator-always-on;
290 };
291 };
292 };
293};