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git01.mediatek.com / filogic / uboot / 5b7d70187bcc701a217c1b5501deacb68c2a4c72 / . / arch / arm / dts / imx93-phyboard-segin-u-boot.dtsi
blob: 702d86f4e03f295419bb8f5669511d2160f061ab [file] [log] [blame]
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 * Christoph Stoidner <c.stoidner@phytec.de>
5 *
6 * Product homepage:
7 * phyBOARD-Segin carrier board is reused for the i.MX93 design.
8 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
9 */
10
11#include "imx93-u-boot.dtsi"
12
13/ {
14 wdt-reboot {
15 compatible = "wdt-reboot";
16 wdt = <&wdog3>;
17 bootph-pre-ram;
18 bootph-some-ram;
19 };
20
21 aliases {
22 ethernet0 = &fec;
23 ethernet1 = &eqos;
24 };
25
26 firmware {
27 optee {
28 compatible = "linaro,optee-tz";
29 method = "smc";
30 };
31 };
32};
33
34&{/soc@0} {
35 bootph-all;
36 bootph-pre-ram;
37};
38
39&aips1 {
40 bootph-pre-ram;
41 bootph-all;
42};
43
44&aips2 {
45 bootph-pre-ram;
46 bootph-some-ram;
47};
48
49&aips3 {
50 bootph-pre-ram;
51 bootph-some-ram;
52};
53
54&iomuxc {
55 bootph-pre-ram;
56 bootph-some-ram;
57};
58
59&reg_usdhc2_vmmc {
60 u-boot,off-on-delay-us = <20000>;
61 bootph-pre-ram;
62 bootph-some-ram;
63};
64
65&pinctrl_reg_usdhc2_vmmc {
66 bootph-pre-ram;
67};
68
69&pinctrl_uart1 {
70 bootph-pre-ram;
71 bootph-some-ram;
72};
73
74&pinctrl_usdhc1 {
75 bootph-pre-ram;
76 bootph-some-ram;
77};
78
79&pinctrl_usdhc2_cd {
80 bootph-pre-ram;
81 bootph-some-ram;
82};
83
84&pinctrl_usdhc2_default {
85 bootph-pre-ram;
86 bootph-some-ram;
87};
88
89&pinctrl_usdhc2_100mhz {
90 bootph-pre-ram;
91 bootph-some-ram;
92};
93
94&pinctrl_usdhc2_200mhz {
95 bootph-pre-ram;
96 bootph-some-ram;
97};
98
99&gpio1 {
100 bootph-pre-ram;
101 bootph-some-ram;
102};
103
104&gpio2 {
105 bootph-pre-ram;
106 bootph-some-ram;
107};
108
109&gpio3 {
110 bootph-pre-ram;
111 bootph-some-ram;
112};
113
114&gpio4 {
115 bootph-pre-ram;
116 bootph-some-ram;
117};
118
119&lpuart1 {
120 bootph-pre-ram;
121 bootph-some-ram;
122};
123
Mathieu Othacehe713df352024-03-21 15:45:39 +0100[diff] [blame]124/*
125 * Remove once USB support is added to imx93-phyboard-segin.dts upstream.
126 */
127&usbotg1 {
128 disable-over-current;
129 dr_mode = "otg";
130 status = "okay";
131};
132
133&usbotg2 {
134 disable-over-current;
135 dr_mode = "host";
136 status = "okay";
137};
138
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]139&usdhc1 {
140 bootph-pre-ram;
141 bootph-some-ram;
Christoph Stoidner5b7d7012024-11-20 17:31:42 +0100[diff] [blame^]142 /*
143 * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
144 */
145 pinctrl-names = "default", "state_100mhz", "state_200mhz";
146 pinctrl-0 = <&pinctrl_usdhc1>;
147 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
148 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]149};
150
151&usdhc2 {
152 bootph-pre-ram;
153 bootph-some-ram;
154 fsl,signal-voltage-switch-extra-delay-ms = <8>;
155};
156
157&lpi2c1 {
158 bootph-pre-ram;
159 bootph-some-ram;
160};
161
162&lpi2c2 {
163 bootph-pre-ram;
164 bootph-some-ram;
165};
166
167&lpi2c3 {
168 bootph-pre-ram;
169 bootph-some-ram;
170};
171
172&s4muap {
173 bootph-pre-ram;
174 bootph-some-ram;
175 status = "okay";
176};
177
178&clk {
179 bootph-all;
180 bootph-pre-ram;
181 /delete-property/ assigned-clocks;
182 /delete-property/ assigned-clock-rates;
183 /delete-property/ assigned-clock-parents;
184};
185
186&osc_32k {
187 bootph-all;
188 bootph-pre-ram;
189};
190
191&osc_24m {
192 bootph-all;
193 bootph-pre-ram;
194};
195
196&clk_ext1 {
197 bootph-all;
198 bootph-pre-ram;
199};
200
201&wdog3 {
202 bootph-all;
203 bootph-pre-ram;
204};
205
206/*
207 * The two nodes below won't be needed once nxp,pca9451a
208 * support is added to the Linux kernel.
209 */
210&iomuxc {
211 pinctrl_lpi2c3: lpi2c3grp {
212 bootph-pre-ram;
213 fsl,pins = <
214 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
215 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
216 >;
217 };
218
219 pinctrl_pmic: pmicgrp {
220 bootph-pre-ram;
221 fsl,pins = <
222 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
223 >;
224 };
Christoph Stoidner5b7d7012024-11-20 17:31:42 +0100[diff] [blame^]225
226 /*
227 * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
228 * are added to imx93-phycore-som.dtsi
229 */
230 /* need to config the SION for data and cmd pad, refer to ERR052021 */
231 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
232 bootph-pre-ram;
233 bootph-some-ram;
234 fsl,pins = <
235 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
236 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
237 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
238 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
239 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
240 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
241 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
242 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
243 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
244 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
245 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
246 >;
247 };
248
249 /* need to config the SION for data and cmd pad, refer to ERR052021 */
250 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
251 bootph-pre-ram;
252 bootph-some-ram;
253 fsl,pins = <
254 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
255 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
256 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
257 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
258 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
259 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
260 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
261 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
262 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
263 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
264 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
265 >;
266 };
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]267};
268
269&lpi2c3 {
270 bootph-pre-ram;
271 bootph-some-ram;
272 clock-frequency = <400000>;
273 pinctrl-names = "default", "sleep";
274 pinctrl-0 = <&pinctrl_lpi2c3>;
275 pinctrl-1 = <&pinctrl_lpi2c3>;
276 status = "okay";
277
278 pmic@25 {
279 bootph-pre-ram;
280 bootph-some-ram;
281 compatible = "nxp,pca9451a";
282 reg = <0x25>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_pmic>;
285 interrupt-parent = <&gpio4>;
286 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
287
288 regulators {
289 bootph-pre-ram;
290 bootph-some-ram;
291 buck1: BUCK1 {
292 regulator-name = "VDD_SOC";
293 regulator-min-microvolt = <610000>;
294 regulator-max-microvolt = <950000>;
295 regulator-boot-on;
296 regulator-always-on;
297 regulator-ramp-delay = <3125>;
298 };
299
300 buck2: BUCK2 {
301 regulator-name = "VDDQ_0V6";
302 regulator-min-microvolt = <600000>;
303 regulator-max-microvolt = <600000>;
304 regulator-boot-on;
305 regulator-always-on;
306 };
307
308 buck4: BUCK4 {
309 regulator-name = "VDD_3V3_BUCK";
310 regulator-min-microvolt = <3300000>;
311 regulator-max-microvolt = <3300000>;
312 regulator-boot-on;
313 regulator-always-on;
314 };
315
316 buck5: BUCK5 {
317 regulator-name = "VDD_1V8";
318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <1800000>;
320 regulator-boot-on;
321 regulator-always-on;
322 };
323
324 buck6: BUCK6 {
325 regulator-name = "VDD_1V1";
326 regulator-min-microvolt = <1100000>;
327 regulator-max-microvolt = <1100000>;
328 regulator-boot-on;
329 regulator-always-on;
330 };
331
332 ldo1: LDO1 {
333 regulator-name = "PMIC_SNVS_1V8";
334 regulator-min-microvolt = <1800000>;
335 regulator-max-microvolt = <1800000>;
336 regulator-boot-on;
337 regulator-always-on;
338 };
339
340 ldo4: LDO4 {
341 regulator-name = "VDD_0V8";
342 regulator-min-microvolt = <800000>;
343 regulator-max-microvolt = <800000>;
344 regulator-boot-on;
345 regulator-always-on;
346 };
347
348 ldo5: LDO5 {
349 regulator-name = "NVCC_SD2";
350 regulator-min-microvolt = <1800000>;
351 regulator-max-microvolt = <3300000>;
352 regulator-boot-on;
353 regulator-always-on;
354 };
355 };
356 };
Christoph Stoidner5b7d7012024-11-20 17:31:42 +0100[diff] [blame^]357
358 eeprom@50 {
359 bootph-pre-ram;
360 bootph-some-ram;
361 compatible = "atmel,24c32";
362 reg = <0x50>;
363 pagesize = <32>;
364 vcc-supply = <&buck4>;
365 };
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]366};