Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 713df351e181b3fdd9ae0b6aa948168a627cb55c / . / arch / arm / dts / imx93-phyboard-segin-u-boot.dtsi
blob: 6897c91f4d925a45a28bce824afaeb1ab697d415 [file] [log] [blame]
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH
4 * Christoph Stoidner <c.stoidner@phytec.de>
5 *
6 * Product homepage:
7 * phyBOARD-Segin carrier board is reused for the i.MX93 design.
8 * https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/
9 */
10
11#include "imx93-u-boot.dtsi"
12
13/ {
14 wdt-reboot {
15 compatible = "wdt-reboot";
16 wdt = <&wdog3>;
17 bootph-pre-ram;
18 bootph-some-ram;
19 };
20
21 aliases {
22 ethernet0 = &fec;
23 ethernet1 = &eqos;
24 };
25
26 firmware {
27 optee {
28 compatible = "linaro,optee-tz";
29 method = "smc";
30 };
31 };
32};
33
34&{/soc@0} {
35 bootph-all;
36 bootph-pre-ram;
37};
38
39&aips1 {
40 bootph-pre-ram;
41 bootph-all;
42};
43
44&aips2 {
45 bootph-pre-ram;
46 bootph-some-ram;
47};
48
49&aips3 {
50 bootph-pre-ram;
51 bootph-some-ram;
52};
53
54&iomuxc {
55 bootph-pre-ram;
56 bootph-some-ram;
57};
58
59&reg_usdhc2_vmmc {
60 u-boot,off-on-delay-us = <20000>;
61 bootph-pre-ram;
62 bootph-some-ram;
63};
64
65&pinctrl_reg_usdhc2_vmmc {
66 bootph-pre-ram;
67};
68
69&pinctrl_uart1 {
70 bootph-pre-ram;
71 bootph-some-ram;
72};
73
74&pinctrl_usdhc1 {
75 bootph-pre-ram;
76 bootph-some-ram;
77};
78
79&pinctrl_usdhc2_cd {
80 bootph-pre-ram;
81 bootph-some-ram;
82};
83
84&pinctrl_usdhc2_default {
85 bootph-pre-ram;
86 bootph-some-ram;
87};
88
89&pinctrl_usdhc2_100mhz {
90 bootph-pre-ram;
91 bootph-some-ram;
92};
93
94&pinctrl_usdhc2_200mhz {
95 bootph-pre-ram;
96 bootph-some-ram;
97};
98
99&gpio1 {
100 bootph-pre-ram;
101 bootph-some-ram;
102};
103
104&gpio2 {
105 bootph-pre-ram;
106 bootph-some-ram;
107};
108
109&gpio3 {
110 bootph-pre-ram;
111 bootph-some-ram;
112};
113
114&gpio4 {
115 bootph-pre-ram;
116 bootph-some-ram;
117};
118
119&lpuart1 {
120 bootph-pre-ram;
121 bootph-some-ram;
122};
123
Mathieu Othacehe713df352024-03-21 15:45:39 +0100[diff] [blame^]124/*
125 * Remove once USB support is added to imx93-phyboard-segin.dts upstream.
126 */
127&usbotg1 {
128 disable-over-current;
129 dr_mode = "otg";
130 status = "okay";
131};
132
133&usbotg2 {
134 disable-over-current;
135 dr_mode = "host";
136 status = "okay";
137};
138
Mathieu Othacehe9bfca752024-01-30 15:50:37 +0100[diff] [blame]139&usdhc1 {
140 bootph-pre-ram;
141 bootph-some-ram;
142};
143
144&usdhc2 {
145 bootph-pre-ram;
146 bootph-some-ram;
147 fsl,signal-voltage-switch-extra-delay-ms = <8>;
148};
149
150&lpi2c1 {
151 bootph-pre-ram;
152 bootph-some-ram;
153};
154
155&lpi2c2 {
156 bootph-pre-ram;
157 bootph-some-ram;
158};
159
160&lpi2c3 {
161 bootph-pre-ram;
162 bootph-some-ram;
163};
164
165&s4muap {
166 bootph-pre-ram;
167 bootph-some-ram;
168 status = "okay";
169};
170
171&clk {
172 bootph-all;
173 bootph-pre-ram;
174 /delete-property/ assigned-clocks;
175 /delete-property/ assigned-clock-rates;
176 /delete-property/ assigned-clock-parents;
177};
178
179&osc_32k {
180 bootph-all;
181 bootph-pre-ram;
182};
183
184&osc_24m {
185 bootph-all;
186 bootph-pre-ram;
187};
188
189&clk_ext1 {
190 bootph-all;
191 bootph-pre-ram;
192};
193
194&wdog3 {
195 bootph-all;
196 bootph-pre-ram;
197};
198
199/*
200 * The two nodes below won't be needed once nxp,pca9451a
201 * support is added to the Linux kernel.
202 */
203&iomuxc {
204 pinctrl_lpi2c3: lpi2c3grp {
205 bootph-pre-ram;
206 fsl,pins = <
207 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
208 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
209 >;
210 };
211
212 pinctrl_pmic: pmicgrp {
213 bootph-pre-ram;
214 fsl,pins = <
215 MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
216 >;
217 };
218};
219
220&lpi2c3 {
221 bootph-pre-ram;
222 bootph-some-ram;
223 clock-frequency = <400000>;
224 pinctrl-names = "default", "sleep";
225 pinctrl-0 = <&pinctrl_lpi2c3>;
226 pinctrl-1 = <&pinctrl_lpi2c3>;
227 status = "okay";
228
229 pmic@25 {
230 bootph-pre-ram;
231 bootph-some-ram;
232 compatible = "nxp,pca9451a";
233 reg = <0x25>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_pmic>;
236 interrupt-parent = <&gpio4>;
237 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
238
239 regulators {
240 bootph-pre-ram;
241 bootph-some-ram;
242 buck1: BUCK1 {
243 regulator-name = "VDD_SOC";
244 regulator-min-microvolt = <610000>;
245 regulator-max-microvolt = <950000>;
246 regulator-boot-on;
247 regulator-always-on;
248 regulator-ramp-delay = <3125>;
249 };
250
251 buck2: BUCK2 {
252 regulator-name = "VDDQ_0V6";
253 regulator-min-microvolt = <600000>;
254 regulator-max-microvolt = <600000>;
255 regulator-boot-on;
256 regulator-always-on;
257 };
258
259 buck4: BUCK4 {
260 regulator-name = "VDD_3V3_BUCK";
261 regulator-min-microvolt = <3300000>;
262 regulator-max-microvolt = <3300000>;
263 regulator-boot-on;
264 regulator-always-on;
265 };
266
267 buck5: BUCK5 {
268 regulator-name = "VDD_1V8";
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <1800000>;
271 regulator-boot-on;
272 regulator-always-on;
273 };
274
275 buck6: BUCK6 {
276 regulator-name = "VDD_1V1";
277 regulator-min-microvolt = <1100000>;
278 regulator-max-microvolt = <1100000>;
279 regulator-boot-on;
280 regulator-always-on;
281 };
282
283 ldo1: LDO1 {
284 regulator-name = "PMIC_SNVS_1V8";
285 regulator-min-microvolt = <1800000>;
286 regulator-max-microvolt = <1800000>;
287 regulator-boot-on;
288 regulator-always-on;
289 };
290
291 ldo4: LDO4 {
292 regulator-name = "VDD_0V8";
293 regulator-min-microvolt = <800000>;
294 regulator-max-microvolt = <800000>;
295 regulator-boot-on;
296 regulator-always-on;
297 };
298
299 ldo5: LDO5 {
300 regulator-name = "NVCC_SD2";
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <3300000>;
303 regulator-boot-on;
304 regulator-always-on;
305 };
306 };
307 };
308};