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git01.mediatek.com / filogic / uboot / 5c05da77a56cd94d6ddc2e39ca789248549dc406 / . / arch / arm / include / asm / arch-am33xx / ddr_defs.h
blob: f56d1e07cc8b1f0f4fefaa86a038e1f1c16e203c [file] [log] [blame]
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]1/*
2 * ddr_defs.h
3 *
4 * ddr specific header
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]9 */
10
11#ifndef _DDR_DEFS_H
12#define _DDR_DEFS_H
13
14#include <asm/arch/hardware.h>
Tom Rinib668ae42012-07-24 14:55:38 -0700[diff] [blame]15#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]16
17/* AM335X EMIF Register values */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]18#define VTP_CTRL_READY (0x1 << 5)
19#define VTP_CTRL_ENABLE (0x1 << 6)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]20#define VTP_CTRL_START_EN (0x1)
Tom Rinif4914f92012-07-24 13:05:10 -0700[diff] [blame]21#define PHY_DLL_LOCK_DIFF 0x0
Tom Rinide3c5702012-07-24 14:03:24 -0700[diff] [blame]22#define DDR_CKE_CTRL_NORMAL 0x1
Vaibhav Hiremathc30d57b2013-03-14 21:11:16 +0000[diff] [blame]23#define PHY_EN_DYN_PWRDN (0x1 << 20)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]24
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]25/* Micron MT47H128M16RT-25E */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]26#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
27#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
28#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
29#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
30#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
31#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
32#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
33#define MT47H128M16RT25E_RATIO 0x80
34#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
35#define MT47H128M16RT25E_RD_DQS 0x12
36#define MT47H128M16RT25E_WR_DQS 0x00
37#define MT47H128M16RT25E_PHY_WRLVL 0x00
38#define MT47H128M16RT25E_PHY_GATELVL 0x00
39#define MT47H128M16RT25E_PHY_WR_DATA 0x40
40#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
41#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
42#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]43
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]44/* Micron MT41J128M16JT-125 */
Peter Korsgaard3adb8272012-10-18 01:21:13 +0000[diff] [blame]45#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
46#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
47#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
48#define MT41J128MJT125_EMIF_TIM3 0x501F830F
49#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
50#define MT41J128MJT125_EMIF_SDREF 0x0000093B
51#define MT41J128MJT125_ZQ_CFG 0x50074BE4
52#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
53#define MT41J128MJT125_RATIO 0x40
54#define MT41J128MJT125_INVERT_CLKOUT 0x1
55#define MT41J128MJT125_RD_DQS 0x3B
56#define MT41J128MJT125_WR_DQS 0x85
57#define MT41J128MJT125_PHY_WR_DATA 0xC1
58#define MT41J128MJT125_PHY_FIFO_WE 0x100
59#define MT41J128MJT125_IOCTRL_VALUE 0x18B
Tom Rini323315a2012-07-30 14:49:50 -0700[diff] [blame]60
Ilya Ledvich791ca182013-11-07 07:57:33 +0200[diff] [blame]61/* Micron MT41J64M16JT-125 */
62#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
63
64/* Micron MT41J256M16JT-125 */
65#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
66
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]67/* Micron MT41J256M8HX-15E */
68#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
69#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
70#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
71#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
72#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
73#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
74#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
75#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
76#define MT41J256M8HX15E_RATIO 0x40
77#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
78#define MT41J256M8HX15E_RD_DQS 0x3B
79#define MT41J256M8HX15E_WR_DQS 0x85
80#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
81#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
82#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
83
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]84/* Micron MT41K256M16HA-125E */
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]85#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
86#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]87#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
88#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
89#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]90#define MT41K256M16HA125E_EMIF_SDREF 0xC30
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]91#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
92#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
Tom Rini8939ec32013-04-10 15:10:54 +0200[diff] [blame]93#define MT41K256M16HA125E_RATIO 0x80
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]94#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
Tom Rini05acd822013-04-12 12:38:16 -0400[diff] [blame]95#define MT41K256M16HA125E_RD_DQS 0x38
96#define MT41K256M16HA125E_WR_DQS 0x44
97#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
98#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
Tom Rini385bc752013-03-21 04:30:02 +0000[diff] [blame]99#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
100
Jeff Lance7c03a222013-01-14 05:32:20 +0000[diff] [blame]101/* Micron MT41J512M8RH-125 on EVM v1.5 */
102#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
103#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
104#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
105#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
106#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
107#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
108#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
109#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
110#define MT41J512M8RH125_RATIO 0x80
111#define MT41J512M8RH125_INVERT_CLKOUT 0x0
112#define MT41J512M8RH125_RD_DQS 0x3B
113#define MT41J512M8RH125_WR_DQS 0x3C
114#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
115#define MT41J512M8RH125_PHY_WR_DATA 0x74
116#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
Lars Poeschel67b4a792013-01-11 00:53:31 +0000[diff] [blame]117
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]118/* Samsung K4B2G1646E-BIH9 */
Enric Balletbo i Serra177db362013-09-10 11:12:26 +0200[diff] [blame]119#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
120#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
121#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
122#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
123#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
124#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]125#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
126#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
Enric Balletbo i Serra177db362013-09-10 11:12:26 +0200[diff] [blame]127#define K4B2G1646EBIH9_RATIO 0x80
128#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
129#define K4B2G1646EBIH9_RD_DQS 0x35
130#define K4B2G1646EBIH9_WR_DQS 0x3A
131#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
132#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
Enric Balletbo i Serrad8efff12013-04-04 22:27:57 +0000[diff] [blame]133#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
134
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]135/**
Matt Porter40355102013-03-15 10:07:07 +0000[diff] [blame]136 * Configure DMM
137 */
138void config_dmm(const struct dmm_lisa_map_regs *regs);
139
140/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]141 * Configure SDRAM
142 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]143void config_sdram(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]144
145/**
146 * Set SDRAM timings
147 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]148void set_sdram_timings(const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]149
150/**
151 * Configure DDR PHY
152 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]153void config_ddr_phy(const struct emif_regs *regs, int nr);
154
155struct ddr_cmd_regs {
156 unsigned int resv0[7];
157 unsigned int cm0csratio; /* offset 0x01C */
158 unsigned int resv1[2];
159 unsigned int cm0dldiff; /* offset 0x028 */
160 unsigned int cm0iclkout; /* offset 0x02C */
161 unsigned int resv2[8];
162 unsigned int cm1csratio; /* offset 0x050 */
163 unsigned int resv3[2];
164 unsigned int cm1dldiff; /* offset 0x05C */
165 unsigned int cm1iclkout; /* offset 0x060 */
166 unsigned int resv4[8];
167 unsigned int cm2csratio; /* offset 0x084 */
168 unsigned int resv5[2];
169 unsigned int cm2dldiff; /* offset 0x090 */
170 unsigned int cm2iclkout; /* offset 0x094 */
171 unsigned int resv6[3];
172};
173
174struct ddr_data_regs {
175 unsigned int dt0rdsratio0; /* offset 0x0C8 */
176 unsigned int resv1[4];
177 unsigned int dt0wdsratio0; /* offset 0x0DC */
178 unsigned int resv2[4];
179 unsigned int dt0wiratio0; /* offset 0x0F0 */
180 unsigned int resv3;
181 unsigned int dt0wimode0; /* offset 0x0F8 */
182 unsigned int dt0giratio0; /* offset 0x0FC */
183 unsigned int resv4;
184 unsigned int dt0gimode0; /* offset 0x104 */
185 unsigned int dt0fwsratio0; /* offset 0x108 */
186 unsigned int resv5[4];
187 unsigned int dt0dqoffset; /* offset 0x11C */
188 unsigned int dt0wrsratio0; /* offset 0x120 */
189 unsigned int resv6[4];
190 unsigned int dt0rdelays0; /* offset 0x134 */
191 unsigned int dt0dldiff0; /* offset 0x138 */
192 unsigned int resv7[12];
193};
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]194
195/**
196 * This structure represents the DDR registers on AM33XX devices.
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]197 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
198 * correspond to DATA1 registers defined here.
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]199 */
200struct ddr_regs {
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]201 unsigned int resv0[3];
202 unsigned int cm0config; /* offset 0x00C */
203 unsigned int cm0configclk; /* offset 0x010 */
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]204 unsigned int resv1[2];
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]205 unsigned int cm0csratio; /* offset 0x01C */
206 unsigned int resv2[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]207 unsigned int cm0dldiff; /* offset 0x028 */
208 unsigned int cm0iclkout; /* offset 0x02C */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]209 unsigned int resv3[4];
210 unsigned int cm1config; /* offset 0x040 */
211 unsigned int cm1configclk; /* offset 0x044 */
212 unsigned int resv4[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]213 unsigned int cm1csratio; /* offset 0x050 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]214 unsigned int resv5[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]215 unsigned int cm1dldiff; /* offset 0x05C */
216 unsigned int cm1iclkout; /* offset 0x060 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]217 unsigned int resv6[4];
218 unsigned int cm2config; /* offset 0x074 */
219 unsigned int cm2configclk; /* offset 0x078 */
220 unsigned int resv7[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]221 unsigned int cm2csratio; /* offset 0x084 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]222 unsigned int resv8[2];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]223 unsigned int cm2dldiff; /* offset 0x090 */
224 unsigned int cm2iclkout; /* offset 0x094 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]225 unsigned int resv9[12];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]226 unsigned int dt0rdsratio0; /* offset 0x0C8 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]227 unsigned int resv10[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]228 unsigned int dt0wdsratio0; /* offset 0x0DC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]229 unsigned int resv11[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]230 unsigned int dt0wiratio0; /* offset 0x0F0 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]231 unsigned int resv12;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]232 unsigned int dt0wimode0; /* offset 0x0F8 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]233 unsigned int dt0giratio0; /* offset 0x0FC */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]234 unsigned int resv13;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]235 unsigned int dt0gimode0; /* offset 0x104 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]236 unsigned int dt0fwsratio0; /* offset 0x108 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]237 unsigned int resv14[4];
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]238 unsigned int dt0dqoffset; /* offset 0x11C */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]239 unsigned int dt0wrsratio0; /* offset 0x120 */
TENART Antoine35c7e522013-07-02 12:05:59 +0200[diff] [blame]240 unsigned int resv15[4];
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]241 unsigned int dt0rdelays0; /* offset 0x134 */
242 unsigned int dt0dldiff0; /* offset 0x138 */
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]243};
244
245/**
246 * Encapsulates DDR CMD control registers.
247 */
248struct cmd_control {
249 unsigned long cmd0csratio;
250 unsigned long cmd0csforce;
251 unsigned long cmd0csdelay;
252 unsigned long cmd0dldiff;
253 unsigned long cmd0iclkout;
254 unsigned long cmd1csratio;
255 unsigned long cmd1csforce;
256 unsigned long cmd1csdelay;
257 unsigned long cmd1dldiff;
258 unsigned long cmd1iclkout;
259 unsigned long cmd2csratio;
260 unsigned long cmd2csforce;
261 unsigned long cmd2csdelay;
262 unsigned long cmd2dldiff;
263 unsigned long cmd2iclkout;
264};
265
266/**
267 * Encapsulates DDR DATA registers.
268 */
269struct ddr_data {
270 unsigned long datardsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]271 unsigned long datawdsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]272 unsigned long datawiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]273 unsigned long datagiratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]274 unsigned long datafwsratio0;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]275 unsigned long datawrsratio0;
Tom Rini3e444582012-07-30 11:49:47 -0700[diff] [blame]276 unsigned long datauserank0delay;
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]277 unsigned long datadldiff0;
278};
279
280/**
281 * Configure DDR CMD control registers
282 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]283void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]284
285/**
286 * Configure DDR DATA registers
287 */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]288void config_ddr_data(const struct ddr_data *data, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]289
290/**
291 * This structure represents the DDR io control on AM33XX devices.
292 */
293struct ddr_cmdtctrl {
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]294 unsigned int cm0ioctl;
295 unsigned int cm1ioctl;
296 unsigned int cm2ioctl;
297 unsigned int resv2[12];
298 unsigned int dt0ioctl;
299 unsigned int dt1ioctl;
300};
301
302/**
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]303 * Configure DDR io control registers
304 */
Tom Rinib239b3b2012-07-24 16:31:26 -0700[diff] [blame]305void config_io_ctrl(unsigned long val);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]306
307struct ddr_ctrl {
308 unsigned int ddrioctrl;
309 unsigned int resv1[325];
310 unsigned int ddrckectrl;
311};
312
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]313void config_ddr(unsigned int pll, unsigned int ioctrl,
314 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]315 const struct emif_regs *regs, int nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]316
317#endif /* _DDR_DEFS_H */