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git01.mediatek.com / filogic / uboot / bbe79a2b348c0cc351ded57202d9614745d1a2c0 / . / include / configs / ti_omap3_common.h
blob: d607f407fdf9b42cadd05dc202814a914a706a41 [file] [log] [blame]
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]1/*
2 * ti_omap3_common.h
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * For more details, please see the technical documents listed at
9 * http://www.ti.com/product/omap3530
10 * http://www.ti.com/product/omap3630
11 * http://www.ti.com/product/dm3730
12 */
13
14#ifndef __CONFIG_TI_OMAP3_COMMON_H__
15#define __CONFIG_TI_OMAP3_COMMON_H__
16
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +0100[diff] [blame]17/*
18 * High Level Configuration Options
19 */
20
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]21#include <asm/arch/cpu.h>
Nishanth Menonfa96c962015-03-09 17:12:04 -0500[diff] [blame]22#include <asm/arch/omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]23
Nishanth Menon3e46e3e2015-03-09 17:12:08 -0500[diff] [blame]24/* Common ARM Erratas */
25#define CONFIG_ARM_ERRATA_454179
26#define CONFIG_ARM_ERRATA_430973
27#define CONFIG_ARM_ERRATA_621766
28
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]29/* The chip has SDRC controller */
30#define CONFIG_SDRC
31
32/* Clock Defines */
33#define V_OSCK 26000000 /* Clock output from T2 */
34#define V_SCLK (V_OSCK >> 1)
35
36/* NS16550 Configuration */
37#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
Thomas Chou52ac4432015-11-19 21:48:12 +0800[diff] [blame]38#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]39#ifdef CONFIG_SPL_BUILD
40# define CONFIG_SYS_NS16550_SERIAL
41# define CONFIG_SYS_NS16550_REG_SIZE (-4)
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]42#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]43#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
44 115200}
45
46/* Select serial console configuration */
47#define CONFIG_CONS_INDEX 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]48#ifdef CONFIG_SPL_BUILD
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]49#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
50#define CONFIG_SERIAL3 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]51#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]52
53/* Physical Memory Map */
54#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
55#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
56
57/*
58 * OMAP3 has 12 GP timers, they can be driven by the system clock
59 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
60 * This rate is divided by a local divisor.
61 */
62#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
63
64#define CONFIG_SYS_MONITOR_LEN (256 << 10)
65
66/* TWL4030 */
Igor Grinberg48b034a2015-10-08 21:12:25 +0300[diff] [blame]67#define CONFIG_TWL4030_POWER
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]68
69/* SPL */
70#define CONFIG_SPL_TEXT_BASE 0x40200800
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]71#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
Tom Rinid9f808d2014-04-03 07:52:53 -0400[diff] [blame]72#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
73 (64 << 20))
74
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]75#ifdef CONFIG_NAND
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]76#define CONFIG_SPL_NAND_SIMPLE
Tom Rinie10247f2014-04-03 15:17:15 -0400[diff] [blame]77#define CONFIG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]78#endif
79
80/* Now bring in the rest of the common code. */
Nishanth Menonad63dd72015-07-22 18:05:41 -0500[diff] [blame]81#include <configs/ti_armv7_omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]82
83#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */