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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stübner5c91e2b2016-07-16 00:17:15 +02003config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +05305 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +08006 select SUPPORT_SPL
7 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +08008 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020010 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
Kever Yangaa827752017-11-28 16:04:16 +080016config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053018 select CPU_V7A
Kever Yangaa827752017-11-28 16:04:16 +080019 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
Heiko Stübneref6db5e2017-02-18 19:46:36 +010025config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053027 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080028 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010029 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010030 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020031 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020032 select SPL_REGMAP
33 select SPL_SYSCON
34 select SPL_RAM
35 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich16c689c2017-10-10 16:21:15 +020036 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangd2af98b2018-11-29 10:07:38 +080037 select DEBUG_UART_BOARD_INIT
Heiko Stübner015f69a2017-04-06 00:19:36 +020038 select BOARD_LATE_INIT
Heiko Stübneref6db5e2017-02-18 19:46:36 +010039 select ROCKCHIP_BROM_HELPER
40 help
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
43 video interfaces, several memory options and video codec support.
44 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
45 UART, SPI, I2C and PWMs.
46
Kever Yang57d4dbf2017-06-23 17:17:52 +080047config ROCKCHIP_RK322X
48 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053049 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080050 select SUPPORT_SPL
51 select SPL
52 select ROCKCHIP_BROM_HELPER
53 select DEBUG_UART_BOARD_INIT
54 help
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
57 and video codec support. Peripherals include Gigabit Ethernet,
58 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
59
Simon Glass2cffe662015-08-30 16:55:38 -060060config ROCKCHIP_RK3288
61 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053062 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080063 select SPL_BOARD_INIT if SPL
Kever Yang0d3d7832016-07-19 21:16:59 +080064 select SUPPORT_SPL
65 select SPL
Eddie Caib3501fe2017-12-15 08:17:13 +080066 imply USB_FUNCTION_ROCKUSB
67 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -060068 help
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
71 video interfaces supporting HDMI and eDP, several DDR3 options
72 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +010073 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -060074
Jagan Tekie5df8342018-02-23 13:13:10 +053075if ROCKCHIP_RK3288
76
Jagan Teki843ac352018-02-23 13:13:11 +053077config TPL_TEXT_BASE
78 default 0xff704000
79
Tom Rinie34a2f32019-01-22 17:09:25 -050080config TPL_MAX_SIZE
81 default 32768
82
Jagan Tekie5df8342018-02-23 13:13:10 +053083endif
84
Kever Yangec02b3c2017-02-23 15:37:51 +080085config ROCKCHIP_RK3328
86 bool "Support Rockchip RK3328"
87 select ARM64
88 help
89 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
90 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
91 video interfaces supporting HDMI and eDP, several DDR3 options
92 and video codec support. Peripherals include Gigabit Ethernet,
93 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
94
Andreas Färber9e3ad682017-05-15 17:51:18 +080095config ROCKCHIP_RK3368
96 bool "Support Rockchip RK3368"
97 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +020098 select SUPPORT_SPL
99 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200100 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
101 select TPL_NEEDS_SEPARATE_STACK if TPL
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200102 imply SPL_SEPARATE_BSS
103 imply SPL_SERIAL_SUPPORT
104 imply TPL_SERIAL_SUPPORT
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200105 select DEBUG_UART_BOARD_INIT
Andreas Färber9e3ad682017-05-15 17:51:18 +0800106 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200107 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
108 into a big and little cluster with 4 cores each) Cortex-A53 including
109 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
110 (for the little cluster), PowerVR G6110 based graphics, one video
111 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
112 video codec support.
113
114 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
115 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800116
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200117if ROCKCHIP_RK3368
118
Philipp Tomsich7d1319b2017-07-28 20:20:41 +0200119config TPL_TEXT_BASE
120 default 0xff8c1000
121
122config TPL_MAX_SIZE
123 default 28672
124
125config TPL_STACK
126 default 0xff8cffff
127
Philipp Tomsichcbacb402017-08-02 21:26:18 +0200128endif
129
Kever Yang0d3d7832016-07-19 21:16:59 +0800130config ROCKCHIP_RK3399
131 bool "Support Rockchip RK3399"
132 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800133 select SUPPORT_SPL
134 select SPL
135 select SPL_SEPARATE_BSS
Philipp Tomsichd17d8cf2017-07-26 12:29:01 +0200136 select SPL_SERIAL_SUPPORT
137 select SPL_DRIVERS_MISC_SUPPORT
Philipp Tomsich41029e62017-04-01 12:59:25 +0200138 select DEBUG_UART_BOARD_INIT
Andy Yan70378cb2017-10-11 15:00:16 +0800139 select BOARD_LATE_INIT
Andy Yand2349d92017-10-11 15:00:49 +0800140 select ROCKCHIP_BROM_HELPER
Kever Yang0d3d7832016-07-19 21:16:59 +0800141 help
142 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
143 and quad-core Cortex-A53.
144 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
145 video interfaces supporting HDMI and eDP, several DDR3 options
146 and video codec support. Peripherals include Gigabit Ethernet,
147 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
148
Andy Yan2d982da2017-06-01 18:00:55 +0800149config ROCKCHIP_RV1108
150 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530151 select CPU_V7A
Andy Yan2d982da2017-06-01 18:00:55 +0800152 help
153 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
154 and a DSP.
155
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200156config ROCKCHIP_USB_UART
157 bool "Route uart output to usb pins"
158 help
159 Rockchip SoCs have the ability to route the signals of the debug
160 uart through the d+ and d- pins of a specific usb phy to enable
161 some form of closed-case debugging. With this option supported
162 SoCs will enable this routing as a debug measure.
163
Philipp Tomsich798370f2017-06-29 11:21:15 +0200164config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800165 bool "SPL returns to bootrom"
166 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100167 select ROCKCHIP_BROM_HELPER
Philipp Tomsich798370f2017-06-29 11:21:15 +0200168 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800169 help
170 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
171 SPL will return to the boot rom, which will then load the U-Boot
172 binary to keep going on.
173
Philipp Tomsich798370f2017-06-29 11:21:15 +0200174config TPL_ROCKCHIP_BACK_TO_BROM
175 bool "TPL returns to bootrom"
176 default y if ROCKCHIP_RK3368
177 select ROCKCHIP_BROM_HELPER
178 depends on TPL
179 help
180 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
181 SPL will return to the boot rom, which will then load the U-Boot
182 binary to keep going on.
183
Andy Yan70378cb2017-10-11 15:00:16 +0800184config ROCKCHIP_BOOT_MODE_REG
185 hex "Rockchip boot mode flag register address"
186 default 0x200081c8 if ROCKCHIP_RK3036
187 default 0x20004040 if ROCKCHIP_RK3188
188 default 0x110005c8 if ROCKCHIP_RK322X
189 default 0xff730094 if ROCKCHIP_RK3288
190 default 0xff738200 if ROCKCHIP_RK3368
191 default 0xff320300 if ROCKCHIP_RK3399
192 default 0x10300580 if ROCKCHIP_RV1108
193 default 0
194 help
195 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
196 according to the value from this register.
197
Kever Yange484f772017-04-20 17:03:46 +0800198config ROCKCHIP_SPL_RESERVE_IRAM
199 hex "Size of IRAM reserved in SPL"
Kever Yang60a50072017-12-18 15:13:19 +0800200 default 0
Kever Yange484f772017-04-20 17:03:46 +0800201 help
202 SPL may need reserve memory for firmware loaded by SPL, whose load
203 address is in IRAM and may overlay with SPL text area if not
204 reserved.
205
Heiko Stübner355a8802017-02-18 19:46:25 +0100206config ROCKCHIP_BROM_HELPER
207 bool
208
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200209config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
210 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
211 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
212 help
213 Some Rockchip BROM variants (e.g. on the RK3188) load the
214 first stage in segments and enter multiple times. E.g. on
215 the RK3188, the first 1KB of the first stage are loaded
216 first and entered; after returning to the BROM, the
217 remainder of the first stage is loaded, but the BROM
218 re-enters at the same address/to the same code as previously.
219
220 This enables support code in the BOOT0 hook for the SPL stage
221 to allow multiple entries.
222
223config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
224 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
225 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
226 help
227 Some Rockchip BROM variants (e.g. on the RK3188) load the
228 first stage in segments and enter multiple times. E.g. on
229 the RK3188, the first 1KB of the first stage are loaded
230 first and entered; after returning to the BROM, the
231 remainder of the first stage is loaded, but the BROM
232 re-enters at the same address/to the same code as previously.
233
234 This enables support code in the BOOT0 hook for the TPL stage
235 to allow multiple entries.
236
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400237config SPL_MMC_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200238 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400239
huang lin1115b642015-11-17 14:20:27 +0800240source "arch/arm/mach-rockchip/rk3036/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800241source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100242source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800243source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200244source "arch/arm/mach-rockchip/rk3288/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800245source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800246source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800247source "arch/arm/mach-rockchip/rk3399/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800248source "arch/arm/mach-rockchip/rv1108/Kconfig"
Simon Glass2cffe662015-08-30 16:55:38 -0600249endif