Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 3 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 8 | * MPC5121ADS board configuration file |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 14 | #define CONFIG_MPC5121ADS 1 |
Anatolij Gustschin | 5aca67b | 2014-10-21 13:46:59 +0200 | [diff] [blame] | 15 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 16 | /* |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 17 | * Memory map for the MPC5121ADS board: |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 18 | * |
| 19 | * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) |
| 20 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) |
| 21 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) |
| 22 | * 0x8200_0000 - 0x8200_001F CPLD (32 B) |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 23 | * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) |
| 24 | * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) |
| 25 | * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 26 | * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) |
| 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * High Level Configuration Options |
| 31 | */ |
| 32 | #define CONFIG_E300 1 /* E300 Family */ |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 33 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 34 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| 35 | |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 36 | /* video */ |
Timur Tabi | 020edd2 | 2011-02-15 17:09:19 -0600 | [diff] [blame] | 37 | #ifdef CONFIG_FSL_DIU_FB |
| 38 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) |
Timur Tabi | e604463 | 2010-08-31 19:56:43 -0500 | [diff] [blame] | 39 | #define CONFIG_CMD_BMP |
Timur Tabi | e604463 | 2010-08-31 19:56:43 -0500 | [diff] [blame] | 40 | #define CONFIG_VIDEO_LOGO |
| 41 | #define CONFIG_VIDEO_BMP_LOGO |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 42 | #endif |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 43 | |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 44 | /* CONFIG_PCI is defined at config time */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 45 | |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 46 | #ifdef CONFIG_MPC5121ADS_REV2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 48 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 50 | #endif |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 51 | |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 52 | #define CONFIG_MISC_INIT_R |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 53 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | #define CONFIG_SYS_IMMR 0x80000000 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 55 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 57 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 58 | |
| 59 | /* |
| 60 | * DDR Setup - manually set all parameters as there's no SPD etc. |
| 61 | */ |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 62 | #ifdef CONFIG_MPC5121ADS_REV2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 63 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 64 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 66 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 68 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
Anatolij Gustschin | 4c6d349 | 2010-04-24 19:27:08 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 70 | |
Anatolij Gustschin | 007a817 | 2010-04-24 19:27:07 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 |
| 72 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 73 | /* DDR Controller Configuration |
Wolfgang Denk | 530181f | 2007-08-02 21:27:46 +0200 | [diff] [blame] | 74 | * |
| 75 | * SYS_CFG: |
| 76 | * [31:31] MDDRC Soft Reset: Diabled |
| 77 | * [30:30] DRAM CKE pin: Enabled |
| 78 | * [29:29] DRAM CLK: Enabled |
| 79 | * [28:28] Command Mode: Enabled (For initialization only) |
| 80 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] |
| 81 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] |
| 82 | * [20:19] Read Test: DON'T USE |
| 83 | * [18:18] Self Refresh: Enabled |
| 84 | * [17:17] 16bit Mode: Disabled |
| 85 | * [16:13] Ready Delay: 2 |
| 86 | * [12:12] Half DQS Delay: Disabled |
| 87 | * [11:11] Quarter DQS Delay: Disabled |
| 88 | * [10:08] Write Delay: 2 |
| 89 | * [07:07] Early ODT: Disabled |
| 90 | * [06:06] On DIE Termination: Disabled |
| 91 | * [05:05] FIFO Overflow Clear: DON'T USE here |
| 92 | * [04:04] FIFO Underflow Clear: DON'T USE here |
| 93 | * [03:03] FIFO Overflow Pending: DON'T USE here |
| 94 | * [02:02] FIFO Underlfow Pending: DON'T USE here |
| 95 | * [01:01] FIFO Overlfow Enabled: Enabled |
| 96 | * [00:00] FIFO Underflow Enabled: Enabled |
| 97 | * TIME_CFG0 |
| 98 | * [31:16] DRAM Refresh Time: 0 CSB clocks |
| 99 | * [15:8] DRAM Command Time: 0 CSB clocks |
| 100 | * [07:00] DRAM Precharge Time: 0 CSB clocks |
| 101 | * TIME_CFG1 |
| 102 | * [31:26] DRAM tRFC: |
| 103 | * [25:21] DRAM tWR1: |
| 104 | * [20:17] DRAM tWRT1: |
| 105 | * [16:11] DRAM tDRR: |
| 106 | * [10:05] DRAM tRC: |
| 107 | * [04:00] DRAM tRAS: |
| 108 | * TIME_CFG2 |
| 109 | * [31:28] DRAM tRCD: |
| 110 | * [27:23] DRAM tFAW: |
| 111 | * [22:19] DRAM tRTW1: |
| 112 | * [18:15] DRAM tCCD: |
| 113 | * [14:10] DRAM tRTP: |
| 114 | * [09:05] DRAM tRP: |
| 115 | * [04:00] DRAM tRPA |
| 116 | */ |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 117 | #ifdef CONFIG_MPC5121ADS_REV2 |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 118 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 |
| 120 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 121 | #else |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 122 | #define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 |
| 123 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 |
| 124 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 125 | #endif |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 126 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 127 | |
Martha M Stan | ff8c0df | 2009-09-21 14:08:00 -0400 | [diff] [blame] | 128 | #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 |
| 129 | #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 |
| 130 | #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 |
| 131 | |
Martha M Stan | c12ecae | 2009-09-21 14:07:14 -0400 | [diff] [blame] | 132 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
| 133 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 |
| 134 | #define CONFIG_SYS_DDRCMD_EM2 0x01020000 |
| 135 | #define CONFIG_SYS_DDRCMD_EM3 0x01030000 |
| 136 | #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 |
| 137 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 |
Martha M Stan | ff8c0df | 2009-09-21 14:08:00 -0400 | [diff] [blame] | 138 | |
| 139 | #define DDRCMD_EMR_OCD(pr, ohm) ( \ |
| 140 | (1 << 24) | /* MDDRC Command Request */ \ |
| 141 | (1 << 16) | /* MODE Reg BA[2:0] */ \ |
| 142 | (0 << 12) | /* Outputs 0=Enabled */ \ |
| 143 | (0 << 11) | /* RDQS */ \ |
| 144 | (1 << 10) | /* DQS# */ \ |
| 145 | (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ |
| 146 | /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ |
| 147 | ((ohm & 0x2) << 5)| /* Rtt1 */ \ |
| 148 | (0 << 3) | /* additive posted CAS# */ \ |
| 149 | ((ohm & 0x1) << 2)| /* Rtt0 */ \ |
| 150 | (0 << 0) | /* Output Drive Strength */ \ |
| 151 | (0 << 0)) /* DLL Enable 0=Normal */ |
| 152 | |
| 153 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) |
| 154 | #define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) |
| 155 | |
| 156 | #define DDRCMD_MODE_REG(cas, wr) ( \ |
| 157 | (1 << 24) | /* MDDRC Command Request */ \ |
| 158 | (0 << 16) | /* MODE Reg BA[2:0] */ \ |
| 159 | ((wr-1) << 9)| /* Write Recovery */ \ |
| 160 | (cas << 4) | /* CAS */ \ |
| 161 | (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ |
| 162 | (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ |
| 163 | |
| 164 | #define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) |
| 165 | #define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) |
| 166 | #define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 167 | |
| 168 | /* DDR Priority Manager Configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 169 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 |
| 170 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 |
| 171 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 |
| 172 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC |
| 173 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA |
| 174 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 |
| 175 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 |
| 176 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 |
| 177 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 |
| 178 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 |
| 179 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 |
| 180 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 |
| 181 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 |
| 182 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa |
| 183 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa |
| 184 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 |
| 185 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 |
| 186 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 |
| 187 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 |
| 188 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 |
| 189 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 |
| 190 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 |
| 191 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 192 | |
| 193 | /* |
| 194 | * NOR FLASH on the Local Bus |
| 195 | */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 196 | #undef CONFIG_BKUP_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 197 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 198 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 199 | #ifdef CONFIG_BKUP_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
| 201 | #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 202 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ |
| 204 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 205 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 207 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 208 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
| 209 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 210 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | #undef CONFIG_SYS_FLASH_CHECKSUM |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 212 | |
| 213 | /* |
Stefan Roese | 406e95a | 2009-06-09 16:57:47 +0200 | [diff] [blame] | 214 | * NAND FLASH |
Wolfgang Denk | b6e99b4 | 2009-06-14 20:58:50 +0200 | [diff] [blame] | 215 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) |
Stefan Roese | 406e95a | 2009-06-09 16:57:47 +0200 | [diff] [blame] | 216 | */ |
Wolfgang Denk | 21d523c | 2009-06-14 20:58:53 +0200 | [diff] [blame] | 217 | #define CONFIG_CMD_NAND /* enable NAND support */ |
| 218 | #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ |
Stefan Roese | 406e95a | 2009-06-09 16:57:47 +0200 | [diff] [blame] | 219 | #define CONFIG_NAND_MPC5121_NFC |
| 220 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 221 | |
| 222 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 |
Stefan Roese | 406e95a | 2009-06-09 16:57:47 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ |
| 224 | |
| 225 | /* |
| 226 | * Configuration parameters for MPC5121 NAND driver |
| 227 | */ |
| 228 | #define CONFIG_FSL_NFC_WIDTH 1 |
| 229 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 |
| 230 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 |
| 231 | #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE |
| 232 | |
| 233 | /* |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 234 | * CPLD registers area is really only 32 bytes in size, but the smallest possible LP |
| 235 | * window is 64KB |
| 236 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_CPLD_BASE 0x82000000 |
| 238 | #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ |
Anatolij Gustschin | ca625ee | 2013-02-08 00:03:44 +0000 | [diff] [blame] | 239 | #define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE |
| 240 | #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 241 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 242 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
| 243 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 244 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 245 | #define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ |
| 246 | #define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ |
| 247 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 248 | |
| 249 | /* Use SRAM for initial stack */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 250 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 251 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 252 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 253 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 254 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 255 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 256 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ |
Stefan Roese | 406e95a | 2009-06-09 16:57:47 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 258 | #ifdef CONFIG_FSL_DIU_FB |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 260 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 261 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 262 | #endif |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 263 | |
| 264 | /* |
| 265 | * Serial Port |
| 266 | */ |
| 267 | #define CONFIG_CONS_INDEX 1 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 268 | |
| 269 | /* |
| 270 | * Serial console configuration |
| 271 | */ |
| 272 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ |
Marek Vasut | e79aa90 | 2012-09-16 16:07:24 +0200 | [diff] [blame] | 273 | #define CONFIG_SYS_PSC3 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 274 | #if CONFIG_PSC_CONSOLE != 3 |
| 275 | #error CONFIG_PSC_CONSOLE must be 3 |
| 276 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 277 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 278 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 279 | |
| 280 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE |
| 281 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR |
| 282 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE |
| 283 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR |
| 284 | |
| 285 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 286 | |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 287 | /* |
Anatolij Gustschin | c936642 | 2013-02-08 00:03:45 +0000 | [diff] [blame] | 288 | * Clocks in use |
| 289 | */ |
| 290 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ |
| 291 | CLOCK_SCCR1_DDR_EN | \ |
| 292 | CLOCK_SCCR1_FEC_EN | \ |
| 293 | CLOCK_SCCR1_LPC_EN | \ |
| 294 | CLOCK_SCCR1_NFC_EN | \ |
| 295 | CLOCK_SCCR1_PATA_EN | \ |
| 296 | CLOCK_SCCR1_PCI_EN | \ |
| 297 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ |
| 298 | CLOCK_SCCR1_PSCFIFO_EN | \ |
| 299 | CLOCK_SCCR1_TPR_EN) |
| 300 | |
| 301 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ |
| 302 | CLOCK_SCCR2_I2C_EN | \ |
| 303 | CLOCK_SCCR2_MEM_EN | \ |
| 304 | CLOCK_SCCR2_SPDIF_EN | \ |
| 305 | CLOCK_SCCR2_USB1_EN | \ |
| 306 | CLOCK_SCCR2_USB2_EN) |
| 307 | |
| 308 | /* |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 309 | * PCI |
| 310 | */ |
| 311 | #ifdef CONFIG_PCI |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 312 | #define CONFIG_PCI_INDIRECT_BRIDGE |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 313 | |
| 314 | /* |
| 315 | * General PCI |
| 316 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 317 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 |
| 318 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE |
| 319 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ |
| 320 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE) |
| 321 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE |
| 322 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ |
| 323 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 |
| 324 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 |
| 325 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 326 | |
John Rigby | d1228c9 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 327 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 328 | |
| 329 | #endif |
| 330 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 331 | /* I2C */ |
| 332 | #define CONFIG_HARD_I2C /* I2C with hardware support */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 333 | #define CONFIG_I2C_MULTI_BUS |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 334 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
| 335 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 336 | #if 0 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 337 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 338 | #endif |
| 339 | |
| 340 | /* |
Martha Marx | 5d3e23f | 2009-01-26 10:45:07 -0700 | [diff] [blame] | 341 | * IIM - IC Identification Module |
| 342 | */ |
Benoît Thébaudeau | 8ac3711 | 2013-04-23 10:17:42 +0000 | [diff] [blame] | 343 | #undef CONFIG_FSL_IIM |
Martha Marx | 5d3e23f | 2009-01-26 10:45:07 -0700 | [diff] [blame] | 344 | |
| 345 | /* |
Grzegorz Bernacki | 8713c4b | 2007-10-09 13:58:24 +0200 | [diff] [blame] | 346 | * EEPROM configuration |
| 347 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 348 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ |
| 349 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ |
| 350 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ |
| 351 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ |
Grzegorz Bernacki | 8713c4b | 2007-10-09 13:58:24 +0200 | [diff] [blame] | 352 | |
| 353 | /* |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 354 | * Ethernet configuration |
| 355 | */ |
| 356 | #define CONFIG_MPC512x_FEC 1 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 357 | #define CONFIG_PHY_ADDR 0x1 |
| 358 | #define CONFIG_MII 1 /* MII PHY management */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 359 | #define CONFIG_FEC_AN_TIMEOUT 1 |
John Rigby | d096f62 | 2008-08-05 17:38:57 -0600 | [diff] [blame] | 360 | #define CONFIG_HAS_ETH0 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 361 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 362 | /* |
| 363 | * Configure on-board RTC |
| 364 | */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 365 | #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 366 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 367 | |
| 368 | /* |
Damien Dusha | 7c3be66 | 2010-10-14 15:27:06 +0200 | [diff] [blame] | 369 | * USB Support |
| 370 | */ |
Damien Dusha | 7c3be66 | 2010-10-14 15:27:06 +0200 | [diff] [blame] | 371 | |
| 372 | #if defined(CONFIG_CMD_USB) |
| 373 | #define CONFIG_USB_EHCI /* Enable EHCI Support */ |
| 374 | #define CONFIG_USB_EHCI_FSL /* On a FSL platform */ |
| 375 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */ |
| 376 | #define CONFIG_EHCI_DESC_BIG_ENDIAN |
| 377 | #define CONFIG_EHCI_IS_TDI |
Damien Dusha | 7c3be66 | 2010-10-14 15:27:06 +0200 | [diff] [blame] | 378 | #endif |
| 379 | |
| 380 | /* |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 381 | * Environment |
| 382 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 383 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 384 | /* This has to be a multiple of the Flash sector size */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 385 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 386 | #define CONFIG_ENV_SIZE 0x2000 |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 387 | #ifdef CONFIG_BKUP_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 388 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 389 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 390 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 391 | #endif |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 392 | |
| 393 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 394 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 395 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 396 | |
| 397 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 398 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 399 | |
Wolfgang Denk | 21d523c | 2009-06-14 20:58:53 +0200 | [diff] [blame] | 400 | #define CONFIG_CMD_DATE |
Wolfgang Denk | 21d523c | 2009-06-14 20:58:53 +0200 | [diff] [blame] | 401 | #define CONFIG_CMD_EEPROM |
Wolfgang Denk | 21d523c | 2009-06-14 20:58:53 +0200 | [diff] [blame] | 402 | #define CONFIG_CMD_IDE |
| 403 | #define CONFIG_CMD_JFFS2 |
Wolfgang Denk | 83b1fac | 2007-08-12 14:47:54 +0200 | [diff] [blame] | 404 | #define CONFIG_CMD_REGINFO |
Wolfgang Denk | 21d523c | 2009-06-14 20:58:53 +0200 | [diff] [blame] | 405 | |
Martha Marx | 5d3e23f | 2009-01-26 10:45:07 -0700 | [diff] [blame] | 406 | #undef CONFIG_CMD_FUSE |
Wolfgang Denk | 83b1fac | 2007-08-12 14:47:54 +0200 | [diff] [blame] | 407 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 408 | #if defined(CONFIG_PCI) |
Wolfgang Denk | 83b1fac | 2007-08-12 14:47:54 +0200 | [diff] [blame] | 409 | #define CONFIG_CMD_PCI |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 410 | #endif |
| 411 | |
Wolfgang Denk | 21d523c | 2009-06-14 20:58:53 +0200 | [diff] [blame] | 412 | /* |
| 413 | * Dynamic MTD partition support |
| 414 | */ |
| 415 | #define CONFIG_CMD_MTDPARTS |
| 416 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
| 417 | #define CONFIG_FLASH_CFI_MTD |
| 418 | #define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand" |
| 419 | |
| 420 | /* |
| 421 | * NOR flash layout: |
| 422 | * |
| 423 | * FC000000 - FEABFFFF 42.75 MiB User Data |
| 424 | * FEAC0000 - FFABFFFF 16 MiB Root File System |
| 425 | * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel |
| 426 | * FFEC0000 - FFEFFFFF 256 KiB Device Tree |
| 427 | * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env |
| 428 | * |
| 429 | * NAND flash layout: one big partition |
| 430 | */ |
| 431 | #define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \ |
| 432 | "16m(rootfs)," \ |
| 433 | "4m(kernel)," \ |
| 434 | "256k(dtb)," \ |
| 435 | "1m(u-boot);" \ |
| 436 | "mpc5121.nand:-(data)" |
| 437 | |
Damien Dusha | 7c3be66 | 2010-10-14 15:27:06 +0200 | [diff] [blame] | 438 | #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB) |
Damien Dusha | 7c3be66 | 2010-10-14 15:27:06 +0200 | [diff] [blame] | 439 | #define CONFIG_SUPPORT_VFAT |
| 440 | |
Ralph Kondziella | d074bfe | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 441 | #endif /* defined(CONFIG_CMD_IDE) */ |
| 442 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 443 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 444 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. |
| 445 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 446 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer |
| 447 | * to chapter 36 of the MPC5121e Reference Manual. |
| 448 | */ |
Wolfgang Denk | fc507f5 | 2008-01-15 17:22:28 +0100 | [diff] [blame] | 449 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 450 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 451 | |
| 452 | /* |
| 453 | * Miscellaneous configurable options |
| 454 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 455 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 456 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 457 | |
Wolfgang Denk | 83b1fac | 2007-08-12 14:47:54 +0200 | [diff] [blame] | 458 | #ifdef CONFIG_CMD_KGDB |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 459 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 460 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 461 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 462 | #endif |
| 463 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 464 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
| 465 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 466 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 467 | |
| 468 | /* |
| 469 | * For booting Linux, the board info and command line data |
Ira W. Snyder | c5a22d0 | 2010-09-10 15:42:32 -0700 | [diff] [blame] | 470 | * have to be in the first 256 MB of memory, since this is |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 471 | * the maximum mapped by the Linux kernel during initialization. |
| 472 | */ |
Ira W. Snyder | c5a22d0 | 2010-09-10 15:42:32 -0700 | [diff] [blame] | 473 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 474 | |
| 475 | /* Cache Configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 476 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
| 477 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
Wolfgang Denk | 83b1fac | 2007-08-12 14:47:54 +0200 | [diff] [blame] | 478 | #ifdef CONFIG_CMD_KGDB |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 479 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 480 | #endif |
| 481 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 482 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
Wolfgang Denk | 1997cd9 | 2009-03-26 10:00:57 +0100 | [diff] [blame] | 483 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 484 | #define CONFIG_SYS_HID2 HID2_HBE |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 485 | |
Becky Bruce | 03ea1be | 2008-05-08 19:02:12 -0500 | [diff] [blame] | 486 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 487 | |
Wolfgang Denk | 83b1fac | 2007-08-12 14:47:54 +0200 | [diff] [blame] | 488 | #ifdef CONFIG_CMD_KGDB |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 489 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 490 | #endif |
| 491 | |
| 492 | /* |
| 493 | * Environment Configuration |
| 494 | */ |
Wolfgang Denk | fc507f5 | 2008-01-15 17:22:28 +0100 | [diff] [blame] | 495 | #define CONFIG_TIMESTAMP |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 496 | |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 497 | #define CONFIG_HOSTNAME mpc5121ads |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 498 | #define CONFIG_BOOTFILE "mpc5121ads/uImage" |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 499 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 500 | |
Wolfgang Denk | 39d03f3 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 501 | #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 502 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 503 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 504 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 505 | #define CONFIG_PREBOOT "echo;" \ |
Wolfgang Denk | c4c342e | 2008-03-03 12:36:49 +0100 | [diff] [blame] | 506 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 507 | "echo" |
| 508 | |
| 509 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Wolfgang Denk | 39d03f3 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 510 | "u-boot_addr_r=200000\0" \ |
Wolfgang Denk | 60da471 | 2008-08-26 15:01:28 +0200 | [diff] [blame] | 511 | "kernel_addr_r=600000\0" \ |
| 512 | "fdt_addr_r=880000\0" \ |
| 513 | "ramdisk_addr_r=900000\0" \ |
Wolfgang Denk | 39d03f3 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 514 | "u-boot_addr=FFF00000\0" \ |
Wolfgang Denk | 21d523c | 2009-06-14 20:58:53 +0200 | [diff] [blame] | 515 | "kernel_addr=FFAC0000\0" \ |
Wolfgang Denk | 60da471 | 2008-08-26 15:01:28 +0200 | [diff] [blame] | 516 | "fdt_addr=FFEC0000\0" \ |
Wolfgang Denk | 21d523c | 2009-06-14 20:58:53 +0200 | [diff] [blame] | 517 | "ramdisk_addr=FEAC0000\0" \ |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 518 | "ramdiskfile=mpc5121ads/uRamdisk\0" \ |
| 519 | "u-boot=mpc5121ads/u-boot.bin\0" \ |
| 520 | "bootfile=mpc5121ads/uImage\0" \ |
| 521 | "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \ |
Wolfgang Denk | 60da471 | 2008-08-26 15:01:28 +0200 | [diff] [blame] | 522 | "rootpath=/opt/eldk/ppc_6xx\n" \ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 523 | "netdev=eth0\0" \ |
Wolfgang Denk | 39d03f3 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 524 | "consdev=ttyPSC0\0" \ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 525 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 526 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 527 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 528 | "addip=setenv bootargs ${bootargs} " \ |
| 529 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 530 | ":${hostname}:${netdev}:off panic=1\0" \ |
Wolfgang Denk | 39d03f3 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 531 | "addtty=setenv bootargs ${bootargs} " \ |
| 532 | "console=${consdev},${baudrate}\0" \ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 533 | "flash_nfs=run nfsargs addip addtty;" \ |
Detlev Zundel | 027fa49 | 2008-04-18 14:50:01 +0200 | [diff] [blame] | 534 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 535 | "flash_self=run ramargs addip addtty;" \ |
Wolfgang Denk | 39d03f3 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 536 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
| 537 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ |
| 538 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
| 539 | "run nfsargs addip addtty;" \ |
| 540 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ |
| 541 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ |
| 542 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ |
Detlev Zundel | 027fa49 | 2008-04-18 14:50:01 +0200 | [diff] [blame] | 543 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
Wolfgang Denk | 39d03f3 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 544 | "run ramargs addip addtty;" \ |
Wolfgang Denk | c4c342e | 2008-03-03 12:36:49 +0100 | [diff] [blame] | 545 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ |
Detlev Zundel | 027fa49 | 2008-04-18 14:50:01 +0200 | [diff] [blame] | 546 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ |
Wolfgang Denk | 39d03f3 | 2008-01-13 23:37:50 +0100 | [diff] [blame] | 547 | "update=protect off ${u-boot_addr} +${filesize};" \ |
| 548 | "era ${u-boot_addr} +${filesize};" \ |
| 549 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ |
| 550 | "upd=run load update\0" \ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 551 | "" |
| 552 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 553 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 554 | |
John Rigby | d096f62 | 2008-08-05 17:38:57 -0600 | [diff] [blame] | 555 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
Grzegorz Bernacki | af554d8 | 2008-01-08 17:16:15 +0100 | [diff] [blame] | 556 | |
| 557 | #define OF_CPU "PowerPC,5121@0" |
John Rigby | d096f62 | 2008-08-05 17:38:57 -0600 | [diff] [blame] | 558 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" |
Grzegorz Bernacki | af554d8 | 2008-01-08 17:16:15 +0100 | [diff] [blame] | 559 | #define OF_TBCLK (bd->bi_busfreq / 4) |
John Rigby | fc807c5 | 2008-01-30 13:36:57 -0700 | [diff] [blame] | 560 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" |
Grzegorz Bernacki | af554d8 | 2008-01-08 17:16:15 +0100 | [diff] [blame] | 561 | |
Ralph Kondziella | d074bfe | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 562 | /*----------------------------------------------------------------------- |
| 563 | * IDE/ATA stuff |
| 564 | *----------------------------------------------------------------------- |
| 565 | */ |
| 566 | |
| 567 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
| 568 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 569 | #undef CONFIG_IDE_LED /* LED for IDE not supported */ |
| 570 | |
| 571 | #define CONFIG_IDE_RESET /* reset for IDE supported */ |
| 572 | #define CONFIG_IDE_PREINIT |
| 573 | |
| 574 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 575 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ |
| 576 | |
| 577 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 578 | #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() |
Ralph Kondziella | d074bfe | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 579 | |
| 580 | /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ |
| 581 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) |
| 582 | |
| 583 | /* Offset for normal register accesses */ |
| 584 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
| 585 | |
| 586 | /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ |
| 587 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) |
| 588 | |
| 589 | /* Interval between registers */ |
| 590 | #define CONFIG_SYS_ATA_STRIDE 4 |
| 591 | |
Wolfgang Denk | f342f86 | 2009-05-16 10:47:45 +0200 | [diff] [blame] | 592 | #define ATA_BASE_ADDR get_pata_base() |
Ralph Kondziella | d074bfe | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 593 | |
| 594 | /* |
| 595 | * Control register bit definitions |
| 596 | */ |
| 597 | #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 |
| 598 | #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 |
| 599 | #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 |
| 600 | #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 |
| 601 | #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 |
| 602 | #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 |
| 603 | #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 |
| 604 | #define FSL_ATA_CTRL_IORDY_EN 0x01000000 |
| 605 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 606 | #endif /* __CONFIG_H */ |