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TsiChung Liewf6afe722007-06-18 13:50:13 -05001/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00005 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liewf6afe722007-06-18 13:50:13 -05009 */
10
Wolfgang Denk0191e472010-10-26 14:34:52 +020011#include <asm-offsets.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050012#include <config.h>
13#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -060014#include <asm/cache.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050015
TsiChung Liewf6afe722007-06-18 13:50:13 -050016#define _START _start
17#define _FAULT _fault
18
TsiChung Liewf6afe722007-06-18 13:50:13 -050019#define SAVE_ALL \
20 move.w #0x2700,%sr; /* disable intrs */ \
21 subl #60,%sp; /* space for 15 regs */ \
22 moveml %d0-%d7/%a0-%a6,%sp@;
23
24#define RESTORE_ALL \
25 moveml %sp@,%d0-%d7/%a0-%a6; \
26 addl #60,%sp; /* space for 15 regs */ \
27 rte;
28
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010029#if !defined(CONFIG_MONITOR_IS_IN_RAM)
Angelo Dureghello65d59912016-05-22 00:14:29 +020030
TsiChung Liewf6afe722007-06-18 13:50:13 -050031.text
Angelo Dureghello65d59912016-05-22 00:14:29 +020032
TsiChung Liewf6afe722007-06-18 13:50:13 -050033/*
Angelo Dureghello65d59912016-05-22 00:14:29 +020034 * Vector table. This is used for initial platform startup.
35 * These vectors are to catch any un-intended traps.
TsiChung Liewf6afe722007-06-18 13:50:13 -050036 */
37_vectors:
Angelo Dureghello65d59912016-05-22 00:14:29 +020038INITSP: .long 0x00000000 /* Initial SP */
39INITPC: .long _START /* Initial PC */
TsiChung Liewf6afe722007-06-18 13:50:13 -050040
Angelo Dureghello65d59912016-05-22 00:14:29 +020041vector02_0F:
42.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
43.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liewf6afe722007-06-18 13:50:13 -050044
TsiChungLiew8592cda2007-07-05 23:06:55 -050045/* Reserved */
TsiChung Liewf6afe722007-06-18 13:50:13 -050046vector10_17:
47.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
48
Angelo Dureghello65d59912016-05-22 00:14:29 +020049vector18_1F:
50.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liewf6afe722007-06-18 13:50:13 -050051
52/* TRAP #0 - #15 */
53vector20_2F:
54.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
55.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
56
57/* Reserved */
58vector30_3F:
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61
62vector64_127:
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71
72vector128_191:
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81
82vector192_255:
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010091#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
TsiChung Liewf6afe722007-06-18 13:50:13 -050092
Angelo Dureghello65d59912016-05-22 00:14:29 +020093.text
TsiChung Liewf6afe722007-06-18 13:50:13 -050094
Angelo Dureghello65d59912016-05-22 00:14:29 +020095.globl _start
TsiChung Liewf6afe722007-06-18 13:50:13 -050096_start:
97 nop
98 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +020099 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500100
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100101#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChungLiew8592cda2007-07-05 23:06:55 -0500102 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200103 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500104 movec %d0, %VBR
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100105#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -0500106
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew942383d2007-10-25 17:12:36 -0500108 movec %d0, %RAMBAR1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500109
110 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600111 move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500112 movec %d0, %CACR /* Invalidate cache */
113 move.l #0, %d0
114 movec %d0, %ACR0
115 movec %d0, %ACR1
116
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000117#ifdef CONFIG_MCF5301x
118 move.l #(0xFC0a0010), %a0
119 move.w (%a0), %d0
120 and.l %d0, 0xEFFF
121
122 move.w %d0, (%a0)
123#endif
124
TsiChung Liewf6afe722007-06-18 13:50:13 -0500125 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200126 move.l #0, %d0
127 move.l #(ICACHE_STATUS), %a1 /* icache */
128 move.l #(DCACHE_STATUS), %a2 /* icache */
129 move.l %d0, (%a1)
130 move.l %d0, (%a2)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500131
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200132 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200133 move.l #__got_start, %a5
TsiChung Liewf6afe722007-06-18 13:50:13 -0500134
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200135 /* setup stack initially on top of internal static ram */
136 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
137
138 /*
139 * if configured, malloc_f arena will be reserved first,
140 * then (and always) gd struct space will be reserved
141 */
142 move.l %sp, -(%sp)
143 move.l #board_init_f_alloc_reserve, %a1
144 jsr (%a1)
145
146 /* update stack and frame-pointers */
147 move.l %d0, %sp
148 move.l %sp, %fp
149
150 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200151 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200152 move.l #board_init_f_init_reserve, %a1
153 jsr (%a1)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500154
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200155 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200156 move.l #cpu_init_f, %a1
157 jsr (%a1)
158
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200159 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200160 clr.l %sp@-
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200161 move.l #board_init_f, %a1
162 jsr (%a1)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500163
164 /* board_init_f() does not return */
165
Angelo Dureghello65d59912016-05-22 00:14:29 +0200166/******************************************************************************/
TsiChung Liewf6afe722007-06-18 13:50:13 -0500167
168/*
169 * void relocate_code (addr_sp, gd, addr_moni)
170 *
171 * This "function" does not return, instead it continues in RAM
172 * after relocating the monitor code.
173 *
174 * r3 = dest
175 * r4 = src
176 * r5 = length in bytes
177 * r6 = cachelinesize
178 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200179.globl relocate_code
TsiChung Liewf6afe722007-06-18 13:50:13 -0500180relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200181 link.w %a6,#0
182 move.l 8(%a6), %sp /* set new stack pointer */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500183
Angelo Dureghello65d59912016-05-22 00:14:29 +0200184 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
185 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500186
Angelo Dureghello65d59912016-05-22 00:14:29 +0200187 move.l #CONFIG_SYS_MONITOR_BASE, %a1
188 move.l #__init_end, %a2
189 move.l %a0, %a3
TsiChung Liewf6afe722007-06-18 13:50:13 -0500190
191 /* copy the code to RAM */
1921:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200193 move.l (%a1)+, (%a3)+
194 cmp.l %a1,%a2
195 bgt.s 1b
TsiChung Liewf6afe722007-06-18 13:50:13 -0500196
197/*
198 * We are done. Do not return, instead branch to second part of board
199 * initialization, now running from RAM.
200 */
201 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500203 jmp (%a1)
204
205in_ram:
206
207clear_bss:
208 /*
209 * Now clear BSS segment
210 */
211 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500213 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChung Liewf6afe722007-06-18 13:50:13 -05002156:
216 clr.l (%a1)+
217 cmp.l %a1,%d1
218 bgt.s 6b
219
220 /*
221 * fix got table in RAM
222 */
223 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200225 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500226
227 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChung Liewf6afe722007-06-18 13:50:13 -0500229
2307:
231 move.l (%a1),%d1
232 sub.l #_start,%d1
233 add.l %a0,%d1
234 move.l %d1,(%a1)+
235 cmp.l %a2, %a1
236 bne 7b
237
238 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200239 move.l %a0, %a1
240 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500241
242 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200243 move.l %a0,-(%sp) /* dest_addr */
244 move.l %d0,-(%sp) /* gd */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500245 jsr (%a1)
246
Angelo Dureghello65d59912016-05-22 00:14:29 +0200247/******************************************************************************/
248
TsiChung Liewf6afe722007-06-18 13:50:13 -0500249/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200250.globl _fault
TsiChung Liewf6afe722007-06-18 13:50:13 -0500251_fault:
Marek Vasut876813b2012-10-03 13:28:43 +0000252 bra _fault
TsiChung Liewf6afe722007-06-18 13:50:13 -0500253
Angelo Dureghello65d59912016-05-22 00:14:29 +0200254.globl _exc_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500255_exc_handler:
256 SAVE_ALL
257 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200258 bsr exc_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500259 addql #4,%sp
260 RESTORE_ALL
261
Angelo Dureghello65d59912016-05-22 00:14:29 +0200262.globl _int_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500263_int_handler:
264 SAVE_ALL
265 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200266 bsr int_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500267 addql #4,%sp
268 RESTORE_ALL
269
Angelo Dureghello65d59912016-05-22 00:14:29 +0200270/******************************************************************************/
271
272.globl version_string
TsiChung Liewf6afe722007-06-18 13:50:13 -0500273version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200274.ascii U_BOOT_VERSION_STRING, "\0"
275.align 4