TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
| 3 | * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <config.h> |
| 25 | #include "version.h" |
| 26 | |
| 27 | #ifndef CONFIG_IDENT_STRING |
| 28 | #define CONFIG_IDENT_STRING "" |
| 29 | #endif |
| 30 | |
| 31 | #define _START _start |
| 32 | #define _FAULT _fault |
| 33 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 34 | #define SAVE_ALL \ |
| 35 | move.w #0x2700,%sr; /* disable intrs */ \ |
| 36 | subl #60,%sp; /* space for 15 regs */ \ |
| 37 | moveml %d0-%d7/%a0-%a6,%sp@; |
| 38 | |
| 39 | #define RESTORE_ALL \ |
| 40 | moveml %sp@,%d0-%d7/%a0-%a6; \ |
| 41 | addl #60,%sp; /* space for 15 regs */ \ |
| 42 | rte; |
| 43 | |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 44 | .text |
| 45 | /* |
| 46 | * Vector table. This is used for initial platform startup. |
| 47 | * These vectors are to catch any un-intended traps. |
| 48 | */ |
| 49 | _vectors: |
| 50 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 51 | INITSP: .long 0x00000000 /* Initial SP */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 52 | INITPC: .long _START /* Initial PC */ |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 53 | vector02: .long _FAULT /* Access Error */ |
| 54 | vector03: .long _FAULT /* Address Error */ |
| 55 | vector04: .long _FAULT /* Illegal Instruction */ |
| 56 | vector05: .long _FAULT /* Reserved */ |
| 57 | vector06: .long _FAULT /* Reserved */ |
| 58 | vector07: .long _FAULT /* Reserved */ |
| 59 | vector08: .long _FAULT /* Privilege Violation */ |
| 60 | vector09: .long _FAULT /* Trace */ |
| 61 | vector0A: .long _FAULT /* Unimplemented A-Line */ |
| 62 | vector0B: .long _FAULT /* Unimplemented F-Line */ |
| 63 | vector0C: .long _FAULT /* Debug Interrupt */ |
| 64 | vector0D: .long _FAULT /* Reserved */ |
| 65 | vector0E: .long _FAULT /* Format Error */ |
| 66 | vector0F: .long _FAULT /* Unitialized Int. */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 67 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 68 | /* Reserved */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 69 | vector10_17: |
| 70 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 71 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 72 | vector18: .long _FAULT /* Spurious Interrupt */ |
| 73 | vector19: .long _FAULT /* Autovector Level 1 */ |
| 74 | vector1A: .long _FAULT /* Autovector Level 2 */ |
| 75 | vector1B: .long _FAULT /* Autovector Level 3 */ |
| 76 | vector1C: .long _FAULT /* Autovector Level 4 */ |
| 77 | vector1D: .long _FAULT /* Autovector Level 5 */ |
| 78 | vector1E: .long _FAULT /* Autovector Level 6 */ |
| 79 | vector1F: .long _FAULT /* Autovector Level 7 */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 80 | |
| 81 | /* TRAP #0 - #15 */ |
| 82 | vector20_2F: |
| 83 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 84 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 85 | |
| 86 | /* Reserved */ |
| 87 | vector30_3F: |
| 88 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 89 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 90 | |
| 91 | vector64_127: |
| 92 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 93 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 94 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 95 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 96 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 97 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 98 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 99 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 100 | |
| 101 | vector128_191: |
| 102 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 103 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 104 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 105 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 106 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 107 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 108 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 109 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 110 | |
| 111 | vector192_255: |
| 112 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 113 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 114 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 115 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 116 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 117 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 118 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 119 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 120 | |
| 121 | .text |
| 122 | |
| 123 | .globl _start |
| 124 | _start: |
| 125 | nop |
| 126 | nop |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 127 | move.w #0x2700,%sr /* Mask off Interrupt */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 128 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 129 | /* Set vector base register at the beginning of the Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 130 | move.l #CONFIG_SYS_FLASH_BASE, %d0 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 131 | movec %d0, %VBR |
| 132 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 133 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 |
TsiChungLiew | 942383d | 2007-10-25 17:12:36 -0500 | [diff] [blame] | 134 | movec %d0, %RAMBAR1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 135 | |
| 136 | /* invalidate and disable cache */ |
| 137 | move.l #0x01000000, %d0 /* Invalidate cache cmd */ |
| 138 | movec %d0, %CACR /* Invalidate cache */ |
| 139 | move.l #0, %d0 |
| 140 | movec %d0, %ACR0 |
| 141 | movec %d0, %ACR1 |
| 142 | |
| 143 | /* initialize general use internal ram */ |
| 144 | move.l #0, %d0 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 145 | move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 |
| 146 | move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 147 | move.l %d0, (%a1) |
| 148 | move.l %d0, (%a2) |
| 149 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 150 | /* set stackpointer to end of internal ram to get some stackspace for the |
| 151 | first c-code */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 152 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 153 | clr.l %sp@- |
| 154 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 155 | move.l #__got_start, %a5 /* put relocation table address to a5 */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 156 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 157 | bsr cpu_init_f /* run low-level CPU init code (from flash) */ |
| 158 | bsr board_init_f /* run low-level board init code (from flash) */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 159 | |
| 160 | /* board_init_f() does not return */ |
| 161 | |
| 162 | /*------------------------------------------------------------------------------*/ |
| 163 | |
| 164 | /* |
| 165 | * void relocate_code (addr_sp, gd, addr_moni) |
| 166 | * |
| 167 | * This "function" does not return, instead it continues in RAM |
| 168 | * after relocating the monitor code. |
| 169 | * |
| 170 | * r3 = dest |
| 171 | * r4 = src |
| 172 | * r5 = length in bytes |
| 173 | * r6 = cachelinesize |
| 174 | */ |
| 175 | .globl relocate_code |
| 176 | relocate_code: |
| 177 | link.w %a6,#0 |
| 178 | move.l 8(%a6), %sp /* set new stack pointer */ |
| 179 | |
| 180 | move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ |
| 181 | move.l 16(%a6), %a0 /* Save copy of Destination Address */ |
| 182 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 183 | move.l #CONFIG_SYS_MONITOR_BASE, %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 184 | move.l #__init_end, %a2 |
| 185 | move.l %a0, %a3 |
| 186 | |
| 187 | /* copy the code to RAM */ |
| 188 | 1: |
| 189 | move.l (%a1)+, (%a3)+ |
| 190 | cmp.l %a1,%a2 |
| 191 | bgt.s 1b |
| 192 | |
| 193 | /* |
| 194 | * We are done. Do not return, instead branch to second part of board |
| 195 | * initialization, now running from RAM. |
| 196 | */ |
| 197 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 198 | add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 199 | jmp (%a1) |
| 200 | |
| 201 | in_ram: |
| 202 | |
| 203 | clear_bss: |
| 204 | /* |
| 205 | * Now clear BSS segment |
| 206 | */ |
| 207 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 208 | add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 209 | move.l %a0, %d1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 210 | add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 211 | 6: |
| 212 | clr.l (%a1)+ |
| 213 | cmp.l %a1,%d1 |
| 214 | bgt.s 6b |
| 215 | |
| 216 | /* |
| 217 | * fix got table in RAM |
| 218 | */ |
| 219 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 220 | add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 221 | move.l %a1,%a5 /* * fix got pointer register a5 */ |
| 222 | |
| 223 | move.l %a0, %a2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 224 | add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 225 | |
| 226 | 7: |
| 227 | move.l (%a1),%d1 |
| 228 | sub.l #_start,%d1 |
| 229 | add.l %a0,%d1 |
| 230 | move.l %d1,(%a1)+ |
| 231 | cmp.l %a2, %a1 |
| 232 | bne 7b |
| 233 | |
| 234 | /* calculate relative jump to board_init_r in ram */ |
| 235 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 236 | add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 237 | |
| 238 | /* set parameters for board_init_r */ |
| 239 | move.l %a0,-(%sp) /* dest_addr */ |
| 240 | move.l %d0,-(%sp) /* gd */ |
| 241 | jsr (%a1) |
| 242 | |
| 243 | /*------------------------------------------------------------------------------*/ |
| 244 | /* exception code */ |
| 245 | .globl _fault |
| 246 | _fault: |
| 247 | jmp _fault |
| 248 | .globl _exc_handler |
| 249 | |
| 250 | _exc_handler: |
| 251 | SAVE_ALL |
| 252 | movel %sp,%sp@- |
| 253 | bsr exc_handler |
| 254 | addql #4,%sp |
| 255 | RESTORE_ALL |
| 256 | |
| 257 | .globl _int_handler |
| 258 | _int_handler: |
| 259 | SAVE_ALL |
| 260 | movel %sp,%sp@- |
| 261 | bsr int_handler |
| 262 | addql #4,%sp |
| 263 | RESTORE_ALL |
| 264 | |
| 265 | /*------------------------------------------------------------------------------*/ |
| 266 | /* cache functions */ |
| 267 | .globl icache_enable |
| 268 | icache_enable: |
| 269 | move.l #0x01000000, %d0 /* Invalidate cache cmd */ |
| 270 | movec %d0, %CACR /* Invalidate cache */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 271 | move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 272 | movec %d0, %ACR0 /* Enable cache */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 273 | |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 274 | move.l #0x80000200, %d0 /* Setup cache mask */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 275 | movec %d0, %CACR /* Enable cache */ |
TsiChungLiew | 8592cda | 2007-07-05 23:06:55 -0500 | [diff] [blame] | 276 | nop |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 277 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 278 | move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 279 | moveq #1, %d0 |
| 280 | move.l %d0, (%a1) |
| 281 | rts |
| 282 | |
| 283 | .globl icache_disable |
| 284 | icache_disable: |
TsiChung | 6373c0c | 2007-07-10 15:45:43 -0500 | [diff] [blame] | 285 | move.l #0x01000000, %d0 /* Setup cache mask */ |
| 286 | movec %d0, %CACR /* Disable cache */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 287 | clr.l %d0 /* Setup cache mask */ |
TsiChung | 6373c0c | 2007-07-10 15:45:43 -0500 | [diff] [blame] | 288 | movec %d0, %ACR0 |
| 289 | movec %d0, %ACR1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 290 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 291 | move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 292 | moveq #0, %d0 |
| 293 | move.l %d0, (%a1) |
| 294 | rts |
| 295 | |
| 296 | .globl icache_status |
| 297 | icache_status: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 298 | move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 299 | move.l (%a1), %d0 |
| 300 | rts |
| 301 | |
| 302 | .globl icache_invalid |
| 303 | icache_invalid: |
TsiChung | 6373c0c | 2007-07-10 15:45:43 -0500 | [diff] [blame] | 304 | move.l #0x81000200, %d0 /* Setup cache mask */ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 305 | movec %d0, %CACR /* Enable cache */ |
| 306 | rts |
| 307 | |
| 308 | .globl dcache_enable |
| 309 | dcache_enable: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 310 | move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 311 | moveq #1, %d0 |
| 312 | move.l %d0, (%a1) |
| 313 | rts |
| 314 | |
| 315 | /* No dcache, just a dummy function */ |
| 316 | .globl dcache_disable |
| 317 | dcache_disable: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 318 | move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 319 | moveq #0, %d0 |
| 320 | move.l %d0, (%a1) |
| 321 | rts |
| 322 | |
| 323 | .globl dcache_status |
| 324 | dcache_status: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame^] | 325 | move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1 |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 326 | move.l (%a1), %d0 |
| 327 | rts |
| 328 | |
| 329 | /*------------------------------------------------------------------------------*/ |
| 330 | |
| 331 | .globl version_string |
| 332 | version_string: |
| 333 | .ascii U_BOOT_VERSION |
| 334 | .ascii " (", __DATE__, " - ", __TIME__, ")" |
| 335 | .ascii CONFIG_IDENT_STRING, "\0" |
TsiChung Liew | 9d636e9 | 2008-03-28 08:47:45 -0500 | [diff] [blame] | 336 | .align 4 |