blob: 302fca52451e15dd2a317048b0d048b6567593db [file] [log] [blame]
TsiChung Liewf6afe722007-06-18 13:50:13 -05001/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
TsiChung Liewe7e4fc82008-10-22 11:38:21 +00005 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liewf6afe722007-06-18 13:50:13 -05009 */
10
Wolfgang Denk0191e472010-10-26 14:34:52 +020011#include <asm-offsets.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050012#include <config.h>
13#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -060014#include <asm/cache.h>
TsiChung Liewf6afe722007-06-18 13:50:13 -050015
16#ifndef CONFIG_IDENT_STRING
17#define CONFIG_IDENT_STRING ""
18#endif
19
20#define _START _start
21#define _FAULT _fault
22
TsiChung Liewf6afe722007-06-18 13:50:13 -050023#define SAVE_ALL \
24 move.w #0x2700,%sr; /* disable intrs */ \
25 subl #60,%sp; /* space for 15 regs */ \
26 moveml %d0-%d7/%a0-%a6,%sp@;
27
28#define RESTORE_ALL \
29 moveml %sp@,%d0-%d7/%a0-%a6; \
30 addl #60,%sp; /* space for 15 regs */ \
31 rte;
32
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010033#if !defined(CONFIG_MONITOR_IS_IN_RAM)
Angelo Dureghello65d59912016-05-22 00:14:29 +020034
TsiChung Liewf6afe722007-06-18 13:50:13 -050035.text
Angelo Dureghello65d59912016-05-22 00:14:29 +020036
TsiChung Liewf6afe722007-06-18 13:50:13 -050037/*
Angelo Dureghello65d59912016-05-22 00:14:29 +020038 * Vector table. This is used for initial platform startup.
39 * These vectors are to catch any un-intended traps.
TsiChung Liewf6afe722007-06-18 13:50:13 -050040 */
41_vectors:
Angelo Dureghello65d59912016-05-22 00:14:29 +020042INITSP: .long 0x00000000 /* Initial SP */
43INITPC: .long _START /* Initial PC */
TsiChung Liewf6afe722007-06-18 13:50:13 -050044
Angelo Dureghello65d59912016-05-22 00:14:29 +020045vector02_0F:
46.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
47.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liewf6afe722007-06-18 13:50:13 -050048
TsiChungLiew8592cda2007-07-05 23:06:55 -050049/* Reserved */
TsiChung Liewf6afe722007-06-18 13:50:13 -050050vector10_17:
51.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
52
Angelo Dureghello65d59912016-05-22 00:14:29 +020053vector18_1F:
54.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liewf6afe722007-06-18 13:50:13 -050055
56/* TRAP #0 - #15 */
57vector20_2F:
58.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60
61/* Reserved */
62vector30_3F:
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65
66vector64_127:
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75
76vector128_191:
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85
86vector192_255:
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +010095#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
TsiChung Liewf6afe722007-06-18 13:50:13 -050096
Angelo Dureghello65d59912016-05-22 00:14:29 +020097.text
TsiChung Liewf6afe722007-06-18 13:50:13 -050098
Angelo Dureghello65d59912016-05-22 00:14:29 +020099.globl _start
TsiChung Liewf6afe722007-06-18 13:50:13 -0500100_start:
101 nop
102 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200103 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500104
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100105#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChungLiew8592cda2007-07-05 23:06:55 -0500106 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChung Liewf6afe722007-06-18 13:50:13 -0500108 movec %d0, %VBR
Wolfgang Wegnerea32ab22010-03-02 10:59:20 +0100109#endif
TsiChung Liewf6afe722007-06-18 13:50:13 -0500110
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew942383d2007-10-25 17:12:36 -0500112 movec %d0, %RAMBAR1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500113
114 /* invalidate and disable cache */
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600115 move.l #CF_CACR_CINVA, %d0 /* Invalidate cache cmd */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500116 movec %d0, %CACR /* Invalidate cache */
117 move.l #0, %d0
118 movec %d0, %ACR0
119 movec %d0, %ACR1
120
TsiChung Liewe7e4fc82008-10-22 11:38:21 +0000121#ifdef CONFIG_MCF5301x
122 move.l #(0xFC0a0010), %a0
123 move.w (%a0), %d0
124 and.l %d0, 0xEFFF
125
126 move.w %d0, (%a0)
127#endif
128
TsiChung Liewf6afe722007-06-18 13:50:13 -0500129 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200130 move.l #0, %d0
131 move.l #(ICACHE_STATUS), %a1 /* icache */
132 move.l #(DCACHE_STATUS), %a2 /* icache */
133 move.l %d0, (%a1)
134 move.l %d0, (%a2)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500135
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200136 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200137 move.l #__got_start, %a5
TsiChung Liewf6afe722007-06-18 13:50:13 -0500138
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200139 /* setup stack initially on top of internal static ram */
140 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
141
142 /*
143 * if configured, malloc_f arena will be reserved first,
144 * then (and always) gd struct space will be reserved
145 */
146 move.l %sp, -(%sp)
147 move.l #board_init_f_alloc_reserve, %a1
148 jsr (%a1)
149
150 /* update stack and frame-pointers */
151 move.l %d0, %sp
152 move.l %sp, %fp
153
154 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200155 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200156 move.l #board_init_f_init_reserve, %a1
157 jsr (%a1)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500158
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200159 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200160 move.l #cpu_init_f, %a1
161 jsr (%a1)
162
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200163 /* run low-level board init code (from flash) */
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200164 clr.l %sp@-
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200165 move.l #board_init_f, %a1
166 jsr (%a1)
TsiChung Liewf6afe722007-06-18 13:50:13 -0500167
168 /* board_init_f() does not return */
169
Angelo Dureghello65d59912016-05-22 00:14:29 +0200170/******************************************************************************/
TsiChung Liewf6afe722007-06-18 13:50:13 -0500171
172/*
173 * void relocate_code (addr_sp, gd, addr_moni)
174 *
175 * This "function" does not return, instead it continues in RAM
176 * after relocating the monitor code.
177 *
178 * r3 = dest
179 * r4 = src
180 * r5 = length in bytes
181 * r6 = cachelinesize
182 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200183.globl relocate_code
TsiChung Liewf6afe722007-06-18 13:50:13 -0500184relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200185 link.w %a6,#0
186 move.l 8(%a6), %sp /* set new stack pointer */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500187
Angelo Dureghello65d59912016-05-22 00:14:29 +0200188 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
189 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500190
Angelo Dureghello65d59912016-05-22 00:14:29 +0200191 move.l #CONFIG_SYS_MONITOR_BASE, %a1
192 move.l #__init_end, %a2
193 move.l %a0, %a3
TsiChung Liewf6afe722007-06-18 13:50:13 -0500194
195 /* copy the code to RAM */
1961:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200197 move.l (%a1)+, (%a3)+
198 cmp.l %a1,%a2
199 bgt.s 1b
TsiChung Liewf6afe722007-06-18 13:50:13 -0500200
201/*
202 * We are done. Do not return, instead branch to second part of board
203 * initialization, now running from RAM.
204 */
205 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500207 jmp (%a1)
208
209in_ram:
210
211clear_bss:
212 /*
213 * Now clear BSS segment
214 */
215 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500217 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChung Liewf6afe722007-06-18 13:50:13 -05002196:
220 clr.l (%a1)+
221 cmp.l %a1,%d1
222 bgt.s 6b
223
224 /*
225 * fix got table in RAM
226 */
227 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
Angelo Dureghello65d59912016-05-22 00:14:29 +0200229 move.l %a1,%a5 /* fix got pointer register a5 */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500230
231 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChung Liewf6afe722007-06-18 13:50:13 -0500233
2347:
235 move.l (%a1),%d1
236 sub.l #_start,%d1
237 add.l %a0,%d1
238 move.l %d1,(%a1)+
239 cmp.l %a2, %a1
240 bne 7b
241
242 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200243 move.l %a0, %a1
244 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liewf6afe722007-06-18 13:50:13 -0500245
246 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200247 move.l %a0,-(%sp) /* dest_addr */
248 move.l %d0,-(%sp) /* gd */
TsiChung Liewf6afe722007-06-18 13:50:13 -0500249 jsr (%a1)
250
Angelo Dureghello65d59912016-05-22 00:14:29 +0200251/******************************************************************************/
252
TsiChung Liewf6afe722007-06-18 13:50:13 -0500253/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200254.globl _fault
TsiChung Liewf6afe722007-06-18 13:50:13 -0500255_fault:
Marek Vasut876813b2012-10-03 13:28:43 +0000256 bra _fault
TsiChung Liewf6afe722007-06-18 13:50:13 -0500257
Angelo Dureghello65d59912016-05-22 00:14:29 +0200258.globl _exc_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500259_exc_handler:
260 SAVE_ALL
261 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200262 bsr exc_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500263 addql #4,%sp
264 RESTORE_ALL
265
Angelo Dureghello65d59912016-05-22 00:14:29 +0200266.globl _int_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500267_int_handler:
268 SAVE_ALL
269 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200270 bsr int_handler
TsiChung Liewf6afe722007-06-18 13:50:13 -0500271 addql #4,%sp
272 RESTORE_ALL
273
Angelo Dureghello65d59912016-05-22 00:14:29 +0200274/******************************************************************************/
275
276.globl version_string
TsiChung Liewf6afe722007-06-18 13:50:13 -0500277version_string:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200278.ascii U_BOOT_VERSION_STRING, "\0"
279.align 4