Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 2 | /* |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 3 | * Copyright 2014-2015 Freescale Semiconductor |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 7 | #include <fsl_immap.h> |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 8 | #include <fsl_ifc.h> |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 9 | #include <asm/arch/fsl_serdes.h> |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 10 | #include <asm/arch/soc.h> |
Scott Wood | ae1df32 | 2015-03-20 19:28:13 -0700 | [diff] [blame] | 11 | #include <asm/io.h> |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 13 | #include <asm/arch-fsl-layerscape/config.h> |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 14 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
Hou Zhiqiang | 5ac9a5c | 2016-08-02 19:03:23 +0800 | [diff] [blame] | 15 | #include <fsl_csu.h> |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 16 | #endif |
Prabhakar Kushwaha | d169ebe | 2016-06-03 18:41:31 +0530 | [diff] [blame] | 17 | #ifdef CONFIG_SYS_FSL_DDR |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 18 | #include <fsl_ddr_sdram.h> |
| 19 | #include <fsl_ddr.h> |
Prabhakar Kushwaha | d169ebe | 2016-06-03 18:41:31 +0530 | [diff] [blame] | 20 | #endif |
Aneesh Bansal | 39d5b3b | 2016-01-22 16:37:26 +0530 | [diff] [blame] | 21 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 22 | #include <fsl_validate.h> |
| 23 | #endif |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 24 | #include <fsl_immap.h> |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 25 | |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 26 | bool soc_has_dp_ddr(void) |
| 27 | { |
| 28 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 29 | u32 svr = gur_in32(&gur->svr); |
| 30 | |
Priyanka Jain | 4a6f173 | 2016-11-17 12:29:55 +0530 | [diff] [blame] | 31 | /* LS2085A, LS2088A, LS2048A has DP_DDR */ |
| 32 | if ((SVR_SOC_VER(svr) == SVR_LS2085A) || |
| 33 | (SVR_SOC_VER(svr) == SVR_LS2088A) || |
| 34 | (SVR_SOC_VER(svr) == SVR_LS2048A)) |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 35 | return true; |
| 36 | |
| 37 | return false; |
| 38 | } |
| 39 | |
| 40 | bool soc_has_aiop(void) |
| 41 | { |
| 42 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 43 | u32 svr = gur_in32(&gur->svr); |
| 44 | |
| 45 | /* LS2085A has AIOP */ |
Prabhakar Kushwaha | ac7f242 | 2016-06-24 13:48:13 +0530 | [diff] [blame] | 46 | if (SVR_SOC_VER(svr) == SVR_LS2085A) |
York Sun | cbe8e1c | 2016-04-04 11:41:26 -0700 | [diff] [blame] | 47 | return true; |
| 48 | |
| 49 | return false; |
| 50 | } |
| 51 | |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 52 | static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset) |
| 53 | { |
| 54 | scfg_clrsetbits32(scfg + offset / 4, |
| 55 | 0xF << 6, |
| 56 | SCFG_USB_TXVREFTUNE << 6); |
| 57 | } |
| 58 | |
| 59 | static void erratum_a009008(void) |
| 60 | { |
| 61 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 |
| 62 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 63 | |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 64 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 65 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 66 | set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 67 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 68 | set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); |
| 69 | set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 70 | #endif |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 71 | #elif defined(CONFIG_ARCH_LS2080A) |
| 72 | set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); |
| 73 | #endif |
| 74 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ |
| 75 | } |
| 76 | |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 77 | static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset) |
| 78 | { |
| 79 | scfg_clrbits32(scfg + offset / 4, |
| 80 | SCFG_USB_SQRXTUNE_MASK << 23); |
| 81 | } |
| 82 | |
| 83 | static void erratum_a009798(void) |
| 84 | { |
| 85 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 |
| 86 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
| 87 | |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 88 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 89 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 90 | set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 91 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 92 | set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); |
| 93 | set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 94 | #endif |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 95 | #elif defined(CONFIG_ARCH_LS2080A) |
| 96 | set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR); |
| 97 | #endif |
| 98 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ |
| 99 | } |
| 100 | |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 101 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 102 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 103 | static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) |
| 104 | { |
| 105 | scfg_clrsetbits32(scfg + offset / 4, |
| 106 | 0x7F << 9, |
| 107 | SCFG_USB_PCSTXSWINGFULL << 9); |
| 108 | } |
| 109 | #endif |
| 110 | |
| 111 | static void erratum_a008997(void) |
| 112 | { |
| 113 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 114 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 115 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 116 | u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; |
| 117 | |
| 118 | set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 119 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 120 | set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); |
| 121 | set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); |
| 122 | #endif |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 123 | #endif |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 124 | #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ |
| 125 | } |
| 126 | |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 127 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 128 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 129 | |
| 130 | #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ |
| 131 | out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ |
| 132 | out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ |
| 133 | out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ |
| 134 | out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) |
| 135 | |
Ran Wang | ef27707 | 2017-09-22 15:21:34 +0800 | [diff] [blame] | 136 | #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 137 | |
| 138 | #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ |
| 139 | out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ |
| 140 | out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \ |
| 141 | out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ |
| 142 | out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) |
| 143 | |
| 144 | #endif |
| 145 | |
| 146 | static void erratum_a009007(void) |
| 147 | { |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 148 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ |
| 149 | defined(CONFIG_ARCH_LS1012A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 150 | void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; |
| 151 | |
| 152 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 153 | #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 154 | usb_phy = (void __iomem *)SCFG_USB_PHY2; |
| 155 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); |
| 156 | |
| 157 | usb_phy = (void __iomem *)SCFG_USB_PHY3; |
| 158 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 159 | #endif |
Ran Wang | ef27707 | 2017-09-22 15:21:34 +0800 | [diff] [blame] | 160 | #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 161 | void __iomem *dcsr = (void __iomem *)DCSR_BASE; |
| 162 | |
| 163 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); |
| 164 | PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); |
| 165 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ |
| 166 | } |
| 167 | |
Shengzhou Liu | a3117ee | 2016-11-11 18:11:05 +0800 | [diff] [blame] | 168 | #if defined(CONFIG_FSL_LSCH3) |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 169 | /* |
| 170 | * This erratum requires setting a value to eddrtqcr1 to |
| 171 | * optimal the DDR performance. |
| 172 | */ |
| 173 | static void erratum_a008336(void) |
| 174 | { |
Shengzhou Liu | a3117ee | 2016-11-11 18:11:05 +0800 | [diff] [blame] | 175 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 176 | u32 *eddrtqcr1; |
| 177 | |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 178 | #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR |
| 179 | eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; |
Shengzhou Liu | 7beb0c4 | 2016-08-26 18:30:38 +0800 | [diff] [blame] | 180 | if (fsl_ddr_get_version(0) == 0x50200) |
| 181 | out_le32(eddrtqcr1, 0x63b30002); |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 182 | #endif |
| 183 | #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR |
| 184 | eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; |
Shengzhou Liu | 7beb0c4 | 2016-08-26 18:30:38 +0800 | [diff] [blame] | 185 | if (fsl_ddr_get_version(0) == 0x50200) |
| 186 | out_le32(eddrtqcr1, 0x63b30002); |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 187 | #endif |
| 188 | #endif |
| 189 | } |
| 190 | |
| 191 | /* |
| 192 | * This erratum requires a register write before being Memory |
| 193 | * controller 3 being enabled. |
| 194 | */ |
| 195 | static void erratum_a008514(void) |
| 196 | { |
Shengzhou Liu | a3117ee | 2016-11-11 18:11:05 +0800 | [diff] [blame] | 197 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 198 | u32 *eddrtqcr1; |
| 199 | |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 200 | #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR |
| 201 | eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; |
| 202 | out_le32(eddrtqcr1, 0x63b20002); |
| 203 | #endif |
| 204 | #endif |
| 205 | } |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 206 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 |
| 207 | #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" |
| 208 | |
| 209 | static unsigned long get_internval_val_mhz(void) |
| 210 | { |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 211 | char *interval = env_get(PLATFORM_CYCLE_ENV_VAR); |
Prabhakar Kushwaha | 22cfe96 | 2015-11-05 12:00:14 +0530 | [diff] [blame] | 212 | /* |
| 213 | * interval is the number of platform cycles(MHz) between |
| 214 | * wake up events generated by EPU. |
| 215 | */ |
| 216 | ulong interval_mhz = get_bus_freq(0) / (1000 * 1000); |
| 217 | |
| 218 | if (interval) |
| 219 | interval_mhz = simple_strtoul(interval, NULL, 10); |
| 220 | |
| 221 | return interval_mhz; |
| 222 | } |
| 223 | |
| 224 | void erratum_a009635(void) |
| 225 | { |
| 226 | u32 val; |
| 227 | unsigned long interval_mhz = get_internval_val_mhz(); |
| 228 | |
| 229 | if (!interval_mhz) |
| 230 | return; |
| 231 | |
| 232 | val = in_le32(DCSR_CGACRE5); |
| 233 | writel(val | 0x00000200, DCSR_CGACRE5); |
| 234 | |
| 235 | val = in_le32(EPU_EPCMPR5); |
| 236 | writel(interval_mhz, EPU_EPCMPR5); |
| 237 | val = in_le32(EPU_EPCCR5); |
| 238 | writel(val | 0x82820000, EPU_EPCCR5); |
| 239 | val = in_le32(EPU_EPSMCR5); |
| 240 | writel(val | 0x002f0000, EPU_EPSMCR5); |
| 241 | val = in_le32(EPU_EPECR5); |
| 242 | writel(val | 0x20000000, EPU_EPECR5); |
| 243 | val = in_le32(EPU_EPGCR); |
| 244 | writel(val | 0x80000000, EPU_EPGCR); |
| 245 | } |
| 246 | #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */ |
| 247 | |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 248 | static void erratum_rcw_src(void) |
| 249 | { |
Santan Kumar | 9913648 | 2017-05-05 15:42:28 +0530 | [diff] [blame] | 250 | #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 251 | u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; |
| 252 | u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; |
| 253 | u32 val; |
| 254 | |
| 255 | val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); |
| 256 | val &= ~DCFG_PORSR1_RCW_SRC; |
| 257 | val |= DCFG_PORSR1_RCW_SRC_NOR; |
| 258 | out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); |
| 259 | #endif |
| 260 | } |
| 261 | |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 262 | #define I2C_DEBUG_REG 0x6 |
| 263 | #define I2C_GLITCH_EN 0x8 |
| 264 | /* |
| 265 | * This erratum requires setting glitch_en bit to enable |
| 266 | * digital glitch filter to improve clock stability. |
| 267 | */ |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 268 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 269 | static void erratum_a009203(void) |
| 270 | { |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 271 | #ifdef CONFIG_SYS_I2C |
Sriram Dash | afa125b | 2017-09-04 15:45:02 +0530 | [diff] [blame] | 272 | u8 __iomem *ptr; |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 273 | #ifdef I2C1_BASE_ADDR |
| 274 | ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); |
| 275 | |
| 276 | writeb(I2C_GLITCH_EN, ptr); |
| 277 | #endif |
| 278 | #ifdef I2C2_BASE_ADDR |
| 279 | ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); |
| 280 | |
| 281 | writeb(I2C_GLITCH_EN, ptr); |
| 282 | #endif |
| 283 | #ifdef I2C3_BASE_ADDR |
| 284 | ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); |
| 285 | |
| 286 | writeb(I2C_GLITCH_EN, ptr); |
| 287 | #endif |
| 288 | #ifdef I2C4_BASE_ADDR |
| 289 | ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); |
| 290 | |
| 291 | writeb(I2C_GLITCH_EN, ptr); |
| 292 | #endif |
| 293 | #endif |
| 294 | } |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 295 | #endif |
Shengzhou Liu | a3117ee | 2016-11-11 18:11:05 +0800 | [diff] [blame] | 296 | |
Saksham Jain | 5d8ffe1 | 2016-03-23 16:24:40 +0530 | [diff] [blame] | 297 | void bypass_smmu(void) |
| 298 | { |
| 299 | u32 val; |
| 300 | val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); |
| 301 | out_le32(SMMU_SCR0, val); |
| 302 | val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); |
| 303 | out_le32(SMMU_NSCR0, val); |
| 304 | } |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 305 | void fsl_lsch3_early_init_f(void) |
| 306 | { |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 307 | erratum_rcw_src(); |
Sriram Dash | 36a4a34 | 2017-09-04 15:44:05 +0530 | [diff] [blame] | 308 | #ifdef CONFIG_FSL_IFC |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 309 | init_early_memctl_regs(); /* tighten IFC timing */ |
Sriram Dash | 36a4a34 | 2017-09-04 15:44:05 +0530 | [diff] [blame] | 310 | #endif |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 311 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 |
York Sun | 0404a39 | 2015-03-23 10:41:35 -0700 | [diff] [blame] | 312 | erratum_a009203(); |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 313 | #endif |
Yao Yuan | fae8805 | 2015-12-05 14:59:14 +0800 | [diff] [blame] | 314 | erratum_a008514(); |
| 315 | erratum_a008336(); |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 316 | erratum_a009008(); |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 317 | erratum_a009798(); |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 318 | erratum_a008997(); |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 319 | erratum_a009007(); |
Saksham Jain | 5d8ffe1 | 2016-03-23 16:24:40 +0530 | [diff] [blame] | 320 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 321 | /* In case of Secure Boot, the IBR configures the SMMU |
| 322 | * to allow only Secure transactions. |
| 323 | * SMMU must be reset in bypass mode. |
| 324 | * Set the ClientPD bit and Clear the USFCFG Bit |
| 325 | */ |
| 326 | if (fsl_check_boot_mode_secure() == 1) |
| 327 | bypass_smmu(); |
| 328 | #endif |
Scott Wood | f64c98c | 2015-03-20 19:28:12 -0700 | [diff] [blame] | 329 | } |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 330 | |
Rajesh Bhagat | 814e077 | 2018-01-17 16:13:00 +0530 | [diff] [blame] | 331 | /* Get VDD in the unit mV from voltage ID */ |
| 332 | int get_core_volt_from_fuse(void) |
| 333 | { |
| 334 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 335 | int vdd; |
| 336 | u32 fusesr; |
| 337 | u8 vid; |
| 338 | |
| 339 | /* get the voltage ID from fuse status register */ |
| 340 | fusesr = in_le32(&gur->dcfg_fusesr); |
| 341 | debug("%s: fusesr = 0x%x\n", __func__, fusesr); |
| 342 | vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & |
| 343 | FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; |
| 344 | if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { |
| 345 | vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & |
| 346 | FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; |
| 347 | } |
| 348 | debug("%s: VID = 0x%x\n", __func__, vid); |
| 349 | switch (vid) { |
| 350 | case 0x00: /* VID isn't supported */ |
| 351 | vdd = -EINVAL; |
| 352 | debug("%s: The VID feature is not supported\n", __func__); |
| 353 | break; |
| 354 | case 0x08: /* 0.9V silicon */ |
| 355 | vdd = 900; |
| 356 | break; |
| 357 | case 0x10: /* 1.0V silicon */ |
| 358 | vdd = 1000; |
| 359 | break; |
| 360 | default: /* Other core voltage */ |
| 361 | vdd = -EINVAL; |
| 362 | debug("%s: The VID(%x) isn't supported\n", __func__, vid); |
| 363 | break; |
| 364 | } |
| 365 | debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); |
| 366 | |
| 367 | return vdd; |
| 368 | } |
| 369 | |
Prabhakar Kushwaha | 1966d01 | 2016-06-03 18:41:27 +0530 | [diff] [blame] | 370 | #elif defined(CONFIG_FSL_LSCH2) |
Tang Yuantian | 57894be | 2015-12-09 15:32:18 +0800 | [diff] [blame] | 371 | |
Mingkai Hu | 8beb075 | 2015-12-07 16:58:54 +0800 | [diff] [blame] | 372 | static void erratum_a009929(void) |
| 373 | { |
| 374 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009929 |
| 375 | struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 376 | u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR; |
| 377 | u32 rstrqmr1 = gur_in32(&gur->rstrqmr1); |
| 378 | |
| 379 | rstrqmr1 |= 0x00000400; |
| 380 | gur_out32(&gur->rstrqmr1, rstrqmr1); |
| 381 | writel(0x01000000, dcsr_cop_ccp); |
| 382 | #endif |
| 383 | } |
| 384 | |
Mingkai Hu | 172081c | 2016-02-02 11:28:03 +0800 | [diff] [blame] | 385 | /* |
| 386 | * This erratum requires setting a value to eddrtqcr1 to optimal |
| 387 | * the DDR performance. The eddrtqcr1 register is in SCFG space |
| 388 | * of LS1043A and the offset is 0x157_020c. |
| 389 | */ |
| 390 | #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ |
| 391 | && defined(CONFIG_SYS_FSL_ERRATUM_A008514) |
| 392 | #error A009660 and A008514 can not be both enabled. |
| 393 | #endif |
| 394 | |
| 395 | static void erratum_a009660(void) |
| 396 | { |
| 397 | #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 |
| 398 | u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; |
| 399 | out_be32(eddrtqcr1, 0x63b20042); |
| 400 | #endif |
| 401 | } |
| 402 | |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 403 | static void erratum_a008850_early(void) |
| 404 | { |
| 405 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 |
| 406 | /* part 1 of 2 */ |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 407 | struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + |
| 408 | CONFIG_SYS_CCI400_OFFSET); |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 409 | struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
| 410 | |
York Sun | e6b871e | 2017-05-15 08:51:59 -0700 | [diff] [blame] | 411 | /* Skip if running at lower exception level */ |
| 412 | if (current_el() < 3) |
| 413 | return; |
| 414 | |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 415 | /* disables propagation of barrier transactions to DDRC from CCI400 */ |
| 416 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); |
| 417 | |
| 418 | /* disable the re-ordering in DDRC */ |
| 419 | ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); |
| 420 | #endif |
| 421 | } |
| 422 | |
| 423 | void erratum_a008850_post(void) |
| 424 | { |
| 425 | #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 |
| 426 | /* part 2 of 2 */ |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 427 | struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + |
| 428 | CONFIG_SYS_CCI400_OFFSET); |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 429 | struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
| 430 | u32 tmp; |
| 431 | |
York Sun | e6b871e | 2017-05-15 08:51:59 -0700 | [diff] [blame] | 432 | /* Skip if running at lower exception level */ |
| 433 | if (current_el() < 3) |
| 434 | return; |
| 435 | |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 436 | /* enable propagation of barrier transactions to DDRC from CCI400 */ |
| 437 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); |
| 438 | |
| 439 | /* enable the re-ordering in DDRC */ |
| 440 | tmp = ddr_in32(&ddr->eor); |
| 441 | tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); |
| 442 | ddr_out32(&ddr->eor, tmp); |
| 443 | #endif |
| 444 | } |
Hou Zhiqiang | 4b23ca8 | 2016-08-02 19:03:27 +0800 | [diff] [blame] | 445 | |
| 446 | #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 |
| 447 | void erratum_a010315(void) |
| 448 | { |
| 449 | int i; |
| 450 | |
| 451 | for (i = PCIE1; i <= PCIE4; i++) |
| 452 | if (!is_serdes_configured(i)) { |
| 453 | debug("PCIe%d: disabled all R/W permission!\n", i); |
| 454 | set_pcie_ns_access(i, 0); |
| 455 | } |
| 456 | } |
| 457 | #endif |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 458 | |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 459 | static void erratum_a010539(void) |
| 460 | { |
| 461 | #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) |
| 462 | struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 463 | u32 porsr1; |
| 464 | |
| 465 | porsr1 = in_be32(&gur->porsr1); |
| 466 | porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; |
| 467 | out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), |
| 468 | porsr1); |
Hou Zhiqiang | 653793a | 2018-04-25 14:25:42 +0800 | [diff] [blame] | 469 | out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 470 | #endif |
| 471 | } |
| 472 | |
Hou Zhiqiang | 4ad5999 | 2016-12-09 16:09:00 +0800 | [diff] [blame] | 473 | /* Get VDD in the unit mV from voltage ID */ |
| 474 | int get_core_volt_from_fuse(void) |
| 475 | { |
| 476 | struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
| 477 | int vdd; |
| 478 | u32 fusesr; |
| 479 | u8 vid; |
| 480 | |
| 481 | fusesr = in_be32(&gur->dcfg_fusesr); |
| 482 | debug("%s: fusesr = 0x%x\n", __func__, fusesr); |
| 483 | vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & |
| 484 | FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK; |
| 485 | if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { |
| 486 | vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & |
| 487 | FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; |
| 488 | } |
| 489 | debug("%s: VID = 0x%x\n", __func__, vid); |
| 490 | switch (vid) { |
| 491 | case 0x00: /* VID isn't supported */ |
| 492 | vdd = -EINVAL; |
| 493 | debug("%s: The VID feature is not supported\n", __func__); |
| 494 | break; |
| 495 | case 0x08: /* 0.9V silicon */ |
| 496 | vdd = 900; |
| 497 | break; |
| 498 | case 0x10: /* 1.0V silicon */ |
| 499 | vdd = 1000; |
| 500 | break; |
| 501 | default: /* Other core voltage */ |
| 502 | vdd = -EINVAL; |
| 503 | printf("%s: The VID(%x) isn't supported\n", __func__, vid); |
| 504 | break; |
| 505 | } |
| 506 | debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); |
| 507 | |
| 508 | return vdd; |
| 509 | } |
| 510 | |
| 511 | __weak int board_switch_core_volt(u32 vdd) |
| 512 | { |
| 513 | return 0; |
| 514 | } |
| 515 | |
| 516 | static int setup_core_volt(u32 vdd) |
| 517 | { |
| 518 | return board_setup_core_volt(vdd); |
| 519 | } |
| 520 | |
| 521 | #ifdef CONFIG_SYS_FSL_DDR |
| 522 | static void ddr_enable_0v9_volt(bool en) |
| 523 | { |
| 524 | struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
| 525 | u32 tmp; |
| 526 | |
| 527 | tmp = ddr_in32(&ddr->ddr_cdr1); |
| 528 | |
| 529 | if (en) |
| 530 | tmp |= DDR_CDR1_V0PT9_EN; |
| 531 | else |
| 532 | tmp &= ~DDR_CDR1_V0PT9_EN; |
| 533 | |
| 534 | ddr_out32(&ddr->ddr_cdr1, tmp); |
| 535 | } |
| 536 | #endif |
| 537 | |
| 538 | int setup_chip_volt(void) |
| 539 | { |
| 540 | int vdd; |
| 541 | |
| 542 | vdd = get_core_volt_from_fuse(); |
| 543 | /* Nothing to do for silicons doesn't support VID */ |
| 544 | if (vdd < 0) |
| 545 | return vdd; |
| 546 | |
| 547 | if (setup_core_volt(vdd)) |
| 548 | printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd); |
| 549 | #ifdef CONFIG_SYS_HAS_SERDES |
| 550 | if (setup_serdes_volt(vdd)) |
| 551 | printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd); |
| 552 | #endif |
| 553 | |
| 554 | #ifdef CONFIG_SYS_FSL_DDR |
| 555 | if (vdd == 900) |
| 556 | ddr_enable_0v9_volt(true); |
| 557 | #endif |
| 558 | |
| 559 | return 0; |
| 560 | } |
| 561 | |
Calvin Johnson | 6d6ef01 | 2018-03-08 15:30:33 +0530 | [diff] [blame] | 562 | #ifdef CONFIG_FSL_PFE |
| 563 | void init_pfe_scfg_dcfg_regs(void) |
| 564 | { |
| 565 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
| 566 | u32 ecccr2; |
| 567 | |
| 568 | out_be32(&scfg->pfeasbcr, |
| 569 | in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0); |
| 570 | out_be32(&scfg->pfebsbcr, |
| 571 | in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0); |
| 572 | |
| 573 | /* CCI-400 QoS settings for PFE */ |
| 574 | out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS |
| 575 | | SCFG_WR_QOS1_PFE2_QOS)); |
| 576 | out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS |
| 577 | | SCFG_RD_QOS1_PFE2_QOS)); |
| 578 | |
| 579 | ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); |
| 580 | out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, |
| 581 | ecccr2 | (unsigned int)DISABLE_PFE_ECC); |
| 582 | } |
| 583 | #endif |
| 584 | |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 585 | void fsl_lsch2_early_init_f(void) |
| 586 | { |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 587 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + |
| 588 | CONFIG_SYS_CCI400_OFFSET); |
Aneesh Bansal | 13d984d | 2015-12-08 13:54:27 +0530 | [diff] [blame] | 589 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 590 | |
Hou Zhiqiang | 5ac9a5c | 2016-08-02 19:03:23 +0800 | [diff] [blame] | 591 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
| 592 | enable_layerscape_ns_access(); |
| 593 | #endif |
| 594 | |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 595 | #ifdef CONFIG_FSL_IFC |
| 596 | init_early_memctl_regs(); /* tighten IFC timing */ |
| 597 | #endif |
| 598 | |
Qianyu Gong | 5ab2d0a | 2016-03-16 18:01:52 +0800 | [diff] [blame] | 599 | #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) |
Gong Qianyu | 760df89 | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 600 | out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); |
| 601 | #endif |
Aneesh Bansal | 13d984d | 2015-12-08 13:54:27 +0530 | [diff] [blame] | 602 | /* Make SEC reads and writes snoopable */ |
| 603 | setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | |
Tang Yuantian | 2945ae0 | 2016-08-08 15:07:20 +0800 | [diff] [blame] | 604 | SCFG_SNPCNFGCR_SECWRSNP | |
| 605 | SCFG_SNPCNFGCR_SATARDSNP | |
| 606 | SCFG_SNPCNFGCR_SATAWRSNP); |
Aneesh Bansal | 13d984d | 2015-12-08 13:54:27 +0530 | [diff] [blame] | 607 | |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 608 | /* |
| 609 | * Enable snoop requests and DVM message requests for |
| 610 | * Slave insterface S4 (A53 core cluster) |
| 611 | */ |
York Sun | e6b871e | 2017-05-15 08:51:59 -0700 | [diff] [blame] | 612 | if (current_el() == 3) { |
| 613 | out_le32(&cci->slave[4].snoop_ctrl, |
| 614 | CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); |
| 615 | } |
Mingkai Hu | 8beb075 | 2015-12-07 16:58:54 +0800 | [diff] [blame] | 616 | |
| 617 | /* Erratum */ |
Shengzhou Liu | ddf060b | 2016-04-07 16:22:21 +0800 | [diff] [blame] | 618 | erratum_a008850_early(); /* part 1 of 2 */ |
Mingkai Hu | 8beb075 | 2015-12-07 16:58:54 +0800 | [diff] [blame] | 619 | erratum_a009929(); |
Mingkai Hu | 172081c | 2016-02-02 11:28:03 +0800 | [diff] [blame] | 620 | erratum_a009660(); |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 621 | erratum_a010539(); |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 622 | erratum_a009008(); |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 623 | erratum_a009798(); |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 624 | erratum_a008997(); |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 625 | erratum_a009007(); |
Mingkai Hu | e4e93ea | 2015-10-26 19:47:51 +0800 | [diff] [blame] | 626 | } |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 627 | #endif |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 628 | |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 629 | #ifdef CONFIG_QSPI_AHB_INIT |
| 630 | /* Enable 4bytes address support and fast read */ |
| 631 | int qspi_ahb_init(void) |
| 632 | { |
| 633 | u32 *qspi_lut, lut_key, *qspi_key; |
| 634 | |
| 635 | qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300; |
| 636 | qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310; |
| 637 | |
| 638 | lut_key = in_be32(qspi_key); |
| 639 | |
| 640 | if (lut_key == 0x5af05af0) { |
| 641 | /* That means the register is BE */ |
| 642 | out_be32(qspi_key, 0x5af05af0); |
| 643 | /* Unlock the lut table */ |
| 644 | out_be32(qspi_key + 1, 0x00000002); |
| 645 | out_be32(qspi_lut, 0x0820040c); |
| 646 | out_be32(qspi_lut + 1, 0x1c080c08); |
| 647 | out_be32(qspi_lut + 2, 0x00002400); |
| 648 | /* Lock the lut table */ |
| 649 | out_be32(qspi_key, 0x5af05af0); |
| 650 | out_be32(qspi_key + 1, 0x00000001); |
| 651 | } else { |
| 652 | /* That means the register is LE */ |
| 653 | out_le32(qspi_key, 0x5af05af0); |
| 654 | /* Unlock the lut table */ |
| 655 | out_le32(qspi_key + 1, 0x00000002); |
| 656 | out_le32(qspi_lut, 0x0820040c); |
| 657 | out_le32(qspi_lut + 1, 0x1c080c08); |
| 658 | out_le32(qspi_lut + 2, 0x00002400); |
| 659 | /* Lock the lut table */ |
| 660 | out_le32(qspi_key, 0x5af05af0); |
| 661 | out_le32(qspi_key + 1, 0x00000001); |
| 662 | } |
| 663 | |
| 664 | return 0; |
| 665 | } |
| 666 | #endif |
| 667 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 668 | #ifdef CONFIG_BOARD_LATE_INIT |
| 669 | int board_late_init(void) |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 670 | { |
Aneesh Bansal | 39d5b3b | 2016-01-22 16:37:26 +0530 | [diff] [blame] | 671 | #ifdef CONFIG_CHAIN_OF_TRUST |
| 672 | fsl_setenv_chain_of_trust(); |
| 673 | #endif |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 674 | #ifdef CONFIG_QSPI_AHB_INIT |
| 675 | qspi_ahb_init(); |
| 676 | #endif |
Tang Yuantian | 57894be | 2015-12-09 15:32:18 +0800 | [diff] [blame] | 677 | |
Mingkai Hu | 0e58b51 | 2015-10-26 19:47:50 +0800 | [diff] [blame] | 678 | return 0; |
Scott Wood | 8e728cd | 2015-03-24 13:25:02 -0700 | [diff] [blame] | 679 | } |
| 680 | #endif |