Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> |
| 4 | * |
| 5 | * (C) Copyright 2007-2011 |
| 6 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
| 7 | * Tom Cubie <tangliang@allwinnertech.com> |
| 8 | * |
| 9 | * Some init for sunxi platform. |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 13 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 14 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 15 | #include <log.h> |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 16 | #include <mmc.h> |
Hans de Goede | 3352b22 | 2014-06-13 22:55:49 +0200 | [diff] [blame] | 17 | #include <i2c.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 18 | #include <serial.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 19 | #include <spl.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 20 | #include <asm/cache.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 21 | #include <asm/gpio.h> |
| 22 | #include <asm/io.h> |
| 23 | #include <asm/arch/clock.h> |
| 24 | #include <asm/arch/gpio.h> |
Bernhard Nortmann | ead498a | 2015-09-17 18:52:52 +0200 | [diff] [blame] | 25 | #include <asm/arch/spl.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 26 | #include <asm/arch/sys_proto.h> |
| 27 | #include <asm/arch/timer.h> |
Chen-Yu Tsai | fcc7b70 | 2015-08-25 10:49:19 +0800 | [diff] [blame] | 28 | #include <asm/arch/tzpc.h> |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 29 | #include <asm/arch/mmc.h> |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 30 | |
Ian Campbell | d41e2f67 | 2014-07-06 20:03:20 +0100 | [diff] [blame] | 31 | #include <linux/compiler.h> |
| 32 | |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 33 | struct fel_stash { |
| 34 | uint32_t sp; |
| 35 | uint32_t lr; |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 36 | uint32_t cpsr; |
| 37 | uint32_t sctlr; |
| 38 | uint32_t vbar; |
| 39 | uint32_t cr; |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 40 | }; |
| 41 | |
Marek Behún | 4bebdd3 | 2021-05-20 13:23:52 +0200 | [diff] [blame] | 42 | struct fel_stash fel_stash __section(".data"); |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 43 | |
Andre Przywara | 3a63c23 | 2017-02-16 01:20:24 +0000 | [diff] [blame] | 44 | #ifdef CONFIG_ARM64 |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 45 | #include <asm/armv8/mmu.h> |
| 46 | |
| 47 | static struct mm_region sunxi_mem_map[] = { |
| 48 | { |
| 49 | /* SRAM, MMIO regions */ |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 50 | .virt = 0x0UL, |
| 51 | .phys = 0x0UL, |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 52 | .size = 0x40000000UL, |
| 53 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 54 | PTE_BLOCK_NON_SHARE |
| 55 | }, { |
| 56 | /* RAM */ |
York Sun | c7104e5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 57 | .virt = 0x40000000UL, |
| 58 | .phys = 0x40000000UL, |
Icenowy Zheng | 9bc6bec | 2018-10-25 17:23:05 +0800 | [diff] [blame] | 59 | .size = 0xC0000000UL, |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 60 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 61 | PTE_BLOCK_INNER_SHARE |
| 62 | }, { |
| 63 | /* List terminator */ |
| 64 | 0, |
| 65 | } |
| 66 | }; |
| 67 | struct mm_region *mem_map = sunxi_mem_map; |
| 68 | #endif |
| 69 | |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 70 | static int gpio_init(void) |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 71 | { |
Icenowy Zheng | 112c886 | 2019-04-24 13:44:12 +0800 | [diff] [blame] | 72 | __maybe_unused uint val; |
Chen-Yu Tsai | d4ea92b | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 73 | #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 74 | #if defined(CONFIG_MACH_SUN4I) || \ |
| 75 | defined(CONFIG_MACH_SUN7I) || \ |
| 76 | defined(CONFIG_MACH_SUN8I_R40) |
Chen-Yu Tsai | d4ea92b | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 77 | /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ |
| 78 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); |
| 79 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); |
| 80 | #endif |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 81 | #if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40) |
Chen-Yu Tsai | da2f333 | 2015-06-23 19:57:23 +0800 | [diff] [blame] | 82 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); |
| 83 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 84 | #else |
Chen-Yu Tsai | da2f333 | 2015-06-23 19:57:23 +0800 | [diff] [blame] | 85 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); |
| 86 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 87 | #endif |
Chen-Yu Tsai | d4ea92b | 2014-10-22 16:47:42 +0800 | [diff] [blame] | 88 | sunxi_gpio_set_pull(SUNXI_GPF(4), 1); |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 89 | #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \ |
| 90 | defined(CONFIG_MACH_SUN7I) || \ |
| 91 | defined(CONFIG_MACH_SUN8I_R40)) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 92 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); |
| 93 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 94 | sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 95 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 96 | sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0); |
| 97 | sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 98 | sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 99 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 100 | sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); |
| 101 | sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); |
Maxime Ripard | f139f1e | 2014-10-03 20:16:28 +0800 | [diff] [blame] | 102 | sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); |
Chen-Yu Tsai | 28b7192 | 2015-06-23 19:57:25 +0800 | [diff] [blame] | 103 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) |
| 104 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); |
| 105 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); |
| 106 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); |
Andre Przywara | 5fb9743 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 107 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5) |
Jens Kuske | f977072 | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 108 | sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); |
| 109 | sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); |
| 110 | sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP); |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 111 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I) |
| 112 | sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0); |
| 113 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0); |
| 114 | sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); |
Icenowy Zheng | a78bb07 | 2018-07-21 16:20:28 +0800 | [diff] [blame] | 115 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6) |
| 116 | sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0); |
| 117 | sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0); |
| 118 | sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); |
Jernej Skrabec | 30efb9d | 2021-01-11 21:11:41 +0100 | [diff] [blame] | 119 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616) |
| 120 | sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0); |
| 121 | sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0); |
| 122 | sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP); |
vishnupatekar | 133bfbe | 2015-11-29 01:07:20 +0800 | [diff] [blame] | 123 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T) |
| 124 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); |
| 125 | sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); |
| 126 | sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); |
Icenowy Zheng | 52e6188 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 127 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) |
| 128 | sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); |
| 129 | sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); |
| 130 | sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); |
Hans de Goede | 7bfe2bb | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 131 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) |
| 132 | sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); |
| 133 | sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); |
| 134 | sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 135 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 136 | sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1); |
| 137 | sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1); |
Chen-Yu Tsai | 4e526e2 | 2014-10-03 20:16:21 +0800 | [diff] [blame] | 138 | sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); |
Laurent Itti | 20dfe00 | 2015-05-05 17:02:00 -0700 | [diff] [blame] | 139 | #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) |
| 140 | sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2); |
| 141 | sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2); |
| 142 | sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); |
Ian Campbell | 8f32aaa | 2014-10-24 21:20:47 +0100 | [diff] [blame] | 143 | #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) |
Paul Kocialkowski | ae358a4 | 2015-03-22 18:12:22 +0100 | [diff] [blame] | 144 | sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART); |
| 145 | sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART); |
Chen-Yu Tsai | 6ee6388 | 2014-10-22 16:47:47 +0800 | [diff] [blame] | 146 | sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); |
Tobias Schramm | 6892a56 | 2021-02-15 00:19:58 +0100 | [diff] [blame] | 147 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \ |
| 148 | !defined(CONFIG_MACH_SUN8I_R40) |
| 149 | sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1); |
| 150 | sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1); |
| 151 | sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP); |
Hans de Goede | 8c1c782 | 2014-06-09 11:36:58 +0200 | [diff] [blame] | 152 | #else |
| 153 | #error Unsupported console port number. Please fix pin mux settings in board.c |
| 154 | #endif |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 155 | |
Jernej Skrabec | da8ae61 | 2021-01-11 21:11:34 +0100 | [diff] [blame] | 156 | #ifdef CONFIG_SUN50I_GEN_H6 |
Icenowy Zheng | 112c886 | 2019-04-24 13:44:12 +0800 | [diff] [blame] | 157 | /* Update PIO power bias configuration by copy hardware detected value */ |
| 158 | val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); |
| 159 | writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); |
| 160 | val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); |
| 161 | writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); |
| 162 | #endif |
| 163 | |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 164 | return 0; |
| 165 | } |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 166 | |
Andre Przywara | a563adc | 2017-01-02 11:48:45 +0000 | [diff] [blame] | 167 | #if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD) |
Simon Glass | ee30679 | 2016-09-24 18:20:13 -0600 | [diff] [blame] | 168 | static int spl_board_load_image(struct spl_image_info *spl_image, |
| 169 | struct spl_boot_device *bootdev) |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 170 | { |
| 171 | debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); |
| 172 | return_to_fel(fel_stash.sp, fel_stash.lr); |
Nikita Kiryanov | 33eefe4 | 2015-11-08 17:11:49 +0200 | [diff] [blame] | 173 | |
| 174 | return 0; |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 175 | } |
Simon Glass | 4fc1f25 | 2016-11-30 15:30:50 -0700 | [diff] [blame] | 176 | SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image); |
Simon Glass | a499648 | 2016-09-24 18:20:12 -0600 | [diff] [blame] | 177 | #endif |
Simon Glass | 5debe1f | 2015-02-07 10:47:30 -0700 | [diff] [blame] | 178 | |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 179 | void s_init(void) |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 180 | { |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 181 | /* |
| 182 | * Undocumented magic taken from boot0, without this DRAM |
| 183 | * access gets messed up (seems cache related). |
| 184 | * The boot0 sources describe this as: "config ema for cache sram" |
| 185 | */ |
| 186 | #if defined CONFIG_MACH_SUN6I |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 187 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); |
Hans de Goede | c62f8da | 2016-03-24 22:37:08 +0100 | [diff] [blame] | 188 | #elif defined CONFIG_MACH_SUN8I |
| 189 | __maybe_unused uint version; |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 190 | |
| 191 | /* Unlock sram version info reg, read it, relock */ |
| 192 | setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); |
Hans de Goede | c62f8da | 2016-03-24 22:37:08 +0100 | [diff] [blame] | 193 | version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16; |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 194 | clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); |
| 195 | |
Hans de Goede | c62f8da | 2016-03-24 22:37:08 +0100 | [diff] [blame] | 196 | /* |
| 197 | * Ideally this would be a switch case, but we do not know exactly |
| 198 | * which versions there are and which version needs which settings, |
| 199 | * so reproduce the per SoC code from the BSP. |
| 200 | */ |
| 201 | #if defined CONFIG_MACH_SUN8I_A23 |
| 202 | if (version == 0x1650) |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 203 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); |
| 204 | else /* 0x1661 ? */ |
| 205 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); |
Hans de Goede | c62f8da | 2016-03-24 22:37:08 +0100 | [diff] [blame] | 206 | #elif defined CONFIG_MACH_SUN8I_A33 |
| 207 | if (version != 0x1667) |
| 208 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); |
| 209 | #endif |
| 210 | /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */ |
| 211 | /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */ |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 212 | #endif |
Hans de Goede | b88d0ab | 2016-03-04 10:57:34 +0100 | [diff] [blame] | 213 | |
Andre Przywara | 4330eb9 | 2017-02-16 01:20:21 +0000 | [diff] [blame] | 214 | #if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64) |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 215 | /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ |
| 216 | asm volatile( |
| 217 | "mrc p15, 0, r0, c1, c0, 1\n" |
| 218 | "orr r0, r0, #1 << 6\n" |
Andre Przywara | cd975a4 | 2017-02-16 01:20:18 +0000 | [diff] [blame] | 219 | "mcr p15, 0, r0, c1, c0, 1\n" |
| 220 | ::: "r0"); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 221 | #endif |
Chen-Yu Tsai | 0932b63 | 2016-01-06 15:13:06 +0800 | [diff] [blame] | 222 | #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 |
| 223 | /* Enable non-secure access to some peripherals */ |
Chen-Yu Tsai | fcc7b70 | 2015-08-25 10:49:19 +0800 | [diff] [blame] | 224 | tzpc_init(); |
| 225 | #endif |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 226 | |
| 227 | clock_init(); |
| 228 | timer_init(); |
| 229 | gpio_init(); |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 230 | #if !CONFIG_IS_ENABLED(DM_I2C) |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 231 | i2c_init_board(); |
Jernej Skrabec | 9220d50 | 2017-04-27 00:03:36 +0200 | [diff] [blame] | 232 | #endif |
Hans de Goede | 42cbbe3 | 2016-03-17 13:53:03 +0100 | [diff] [blame] | 233 | eth_init_board(); |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 234 | } |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 235 | |
Andre Przywara | a0a5b21 | 2020-01-10 01:47:31 +0000 | [diff] [blame] | 236 | #define SUNXI_INVALID_BOOT_SOURCE -1 |
| 237 | |
| 238 | static int sunxi_get_boot_source(void) |
| 239 | { |
| 240 | if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ |
| 241 | return SUNXI_INVALID_BOOT_SOURCE; |
| 242 | |
| 243 | return readb(SPL_ADDR + 0x28); |
| 244 | } |
| 245 | |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 246 | /* The sunxi internal brom will try to loader external bootloader |
| 247 | * from mmc0, nand flash, mmc2. |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 248 | */ |
Maxime Ripard | 1941be8 | 2017-08-23 10:06:30 +0200 | [diff] [blame] | 249 | uint32_t sunxi_get_boot_device(void) |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 250 | { |
Andre Przywara | a0a5b21 | 2020-01-10 01:47:31 +0000 | [diff] [blame] | 251 | int boot_source = sunxi_get_boot_source(); |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 252 | |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 253 | /* |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 254 | * When booting from the SD card or NAND memory, the "eGON.BT0" |
| 255 | * signature is expected to be found in memory at the address 0x0004 |
| 256 | * (see the "mksunxiboot" tool, which generates this header). |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 257 | * |
| 258 | * When booting in the FEL mode over USB, this signature is patched in |
| 259 | * memory and replaced with something else by the 'fel' tool. This other |
| 260 | * signature is selected in such a way, that it can't be present in a |
| 261 | * valid bootable SD card image (because the BROM would refuse to |
| 262 | * execute the SPL in this case). |
| 263 | * |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 264 | * This checks for the signature and if it is not found returns to |
| 265 | * the FEL code in the BROM to wait and receive the main u-boot |
| 266 | * binary over USB. If it is found, it determines where SPL was |
| 267 | * read from. |
Siarhei Siamashka | 7ef91f0 | 2015-02-16 10:23:59 +0200 | [diff] [blame] | 268 | */ |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 269 | switch (boot_source) { |
Andre Przywara | a0a5b21 | 2020-01-10 01:47:31 +0000 | [diff] [blame] | 270 | case SUNXI_INVALID_BOOT_SOURCE: |
| 271 | return BOOT_DEVICE_BOARD; |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 272 | case SUNXI_BOOTED_FROM_MMC0: |
Andre Przywara | 946e9db | 2018-12-16 02:04:58 +0000 | [diff] [blame] | 273 | case SUNXI_BOOTED_FROM_MMC0_HIGH: |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 274 | return BOOT_DEVICE_MMC1; |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 275 | case SUNXI_BOOTED_FROM_NAND: |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 276 | return BOOT_DEVICE_NAND; |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 277 | case SUNXI_BOOTED_FROM_MMC2: |
Andre Przywara | 946e9db | 2018-12-16 02:04:58 +0000 | [diff] [blame] | 278 | case SUNXI_BOOTED_FROM_MMC2_HIGH: |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 279 | return BOOT_DEVICE_MMC2; |
| 280 | case SUNXI_BOOTED_FROM_SPI: |
| 281 | return BOOT_DEVICE_SPI; |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 282 | } |
| 283 | |
Hans de Goede | 6527fa2 | 2016-07-09 15:31:47 +0200 | [diff] [blame] | 284 | panic("Unknown boot source %d\n", boot_source); |
Daniel Kochmański | e8b97e2 | 2015-05-29 16:55:42 +0200 | [diff] [blame] | 285 | return -1; /* Never reached */ |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 286 | } |
| 287 | |
Maxime Ripard | 1941be8 | 2017-08-23 10:06:30 +0200 | [diff] [blame] | 288 | #ifdef CONFIG_SPL_BUILD |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 289 | static u32 sunxi_get_spl_size(void) |
| 290 | { |
| 291 | if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ |
| 292 | return 0; |
| 293 | |
| 294 | return readl(SPL_ADDR + 0x10); |
| 295 | } |
| 296 | |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 297 | /* |
| 298 | * The eGON SPL image can be located at 8KB or at 128KB into an SD card or |
| 299 | * an eMMC device. The boot source has bit 4 set in the latter case. |
| 300 | * By adding 120KB to the normal offset when booting from a "high" location |
| 301 | * we can support both cases. |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 302 | * Also U-Boot proper is located at least 32KB after the SPL, but will |
| 303 | * immediately follow the SPL if that is bigger than that. |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 304 | */ |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 305 | unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, |
| 306 | unsigned long raw_sect) |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 307 | { |
Andre Przywara | d42cbee | 2021-01-11 21:11:39 +0100 | [diff] [blame] | 308 | unsigned long spl_size = sunxi_get_spl_size(); |
| 309 | unsigned long sector; |
| 310 | |
| 311 | sector = max(raw_sect, spl_size / 512); |
Andre Przywara | 9ba18e8 | 2020-01-10 01:47:32 +0000 | [diff] [blame] | 312 | |
| 313 | switch (sunxi_get_boot_source()) { |
| 314 | case SUNXI_BOOTED_FROM_MMC0_HIGH: |
| 315 | case SUNXI_BOOTED_FROM_MMC2_HIGH: |
| 316 | sector += (128 - 8) * 2; |
| 317 | break; |
| 318 | } |
| 319 | |
| 320 | return sector; |
| 321 | } |
| 322 | |
Maxime Ripard | 1941be8 | 2017-08-23 10:06:30 +0200 | [diff] [blame] | 323 | u32 spl_boot_device(void) |
| 324 | { |
| 325 | return sunxi_get_boot_device(); |
| 326 | } |
| 327 | |
Hans de Goede | b42b04d | 2015-01-21 16:24:05 +0100 | [diff] [blame] | 328 | void board_init_f(ulong dummy) |
| 329 | { |
Hans de Goede | 76fa0b2 | 2015-09-13 12:31:24 +0200 | [diff] [blame] | 330 | spl_init(); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 331 | preloader_console_init(); |
| 332 | |
| 333 | #ifdef CONFIG_SPL_I2C_SUPPORT |
| 334 | /* Needed early by sunxi_board_init if PMU is enabled */ |
| 335 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
| 336 | #endif |
| 337 | sunxi_board_init(); |
Simon Glass | 8735682 | 2014-12-23 12:04:52 -0700 | [diff] [blame] | 338 | } |
| 339 | #endif |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 340 | |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 341 | void reset_cpu(void) |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 342 | { |
Chen-Yu Tsai | 84f3bb4 | 2016-11-30 16:27:14 +0800 | [diff] [blame] | 343 | #if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) |
Hans de Goede | 1374e89 | 2014-06-09 11:36:56 +0200 | [diff] [blame] | 344 | static const struct sunxi_wdog *wdog = |
| 345 | &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; |
| 346 | |
| 347 | /* Set the watchdog for its shortest interval (.5s) and wait */ |
| 348 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); |
| 349 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); |
Hans de Goede | fa43a6e | 2014-06-13 22:55:52 +0200 | [diff] [blame] | 350 | |
| 351 | while (1) { |
| 352 | /* sun5i sometimes gets stuck without this */ |
| 353 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); |
| 354 | } |
Jernej Skrabec | da8ae61 | 2021-01-11 21:11:34 +0100 | [diff] [blame] | 355 | #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) |
Clément Péron | 3344544 | 2019-04-17 19:41:05 +0200 | [diff] [blame] | 356 | #if defined(CONFIG_MACH_SUN50I_H6) |
| 357 | /* WDOG is broken for some H6 rev. use the R_WDOG instead */ |
| 358 | static const struct sunxi_wdog *wdog = |
| 359 | (struct sunxi_wdog *)SUNXI_R_WDOG_BASE; |
| 360 | #else |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 361 | static const struct sunxi_wdog *wdog = |
Clément Péron | 3344544 | 2019-04-17 19:41:05 +0200 | [diff] [blame] | 362 | ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; |
| 363 | #endif |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 364 | /* Set the watchdog for its shortest interval (.5s) and wait */ |
| 365 | writel(WDT_CFG_RESET, &wdog->cfg); |
| 366 | writel(WDT_MODE_EN, &wdog->mode); |
| 367 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); |
Hans de Goede | b25d3c9 | 2015-06-14 16:53:15 +0200 | [diff] [blame] | 368 | while (1) { } |
Chen-Yu Tsai | 1275c48 | 2014-10-04 20:37:28 +0800 | [diff] [blame] | 369 | #endif |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 370 | } |
| 371 | |
Trevor Woerner | 43ec7e0 | 2019-05-03 09:41:00 -0400 | [diff] [blame] | 372 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) |
Ian Campbell | 6efe369 | 2014-05-05 11:52:26 +0100 | [diff] [blame] | 373 | void enable_caches(void) |
| 374 | { |
| 375 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 376 | dcache_enable(); |
| 377 | } |
| 378 | #endif |