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git01.mediatek.com / filogic / uboot / 9aaa236c9c5ba20a8c46be78f064cdf6e64e846a / . / include / configs / ti_omap3_common.h
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Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]1/*
2 * ti_omap3_common.h
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * For more details, please see the technical documents listed at
9 * http://www.ti.com/product/omap3530
10 * http://www.ti.com/product/omap3630
11 * http://www.ti.com/product/dm3730
12 */
13
14#ifndef __CONFIG_TI_OMAP3_COMMON_H__
15#define __CONFIG_TI_OMAP3_COMMON_H__
16
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +0100[diff] [blame]17/*
18 * High Level Configuration Options
19 */
20
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]21#include <asm/arch/cpu.h>
Nishanth Menonfa96c962015-03-09 17:12:04 -0500[diff] [blame]22#include <asm/arch/omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]23
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]24/* Clock Defines */
25#define V_OSCK 26000000 /* Clock output from T2 */
26#define V_SCLK (V_OSCK >> 1)
27
28/* NS16550 Configuration */
29#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
Thomas Chou52ac4432015-11-19 21:48:12 +0800[diff] [blame]30#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]31#ifdef CONFIG_SPL_BUILD
32# define CONFIG_SYS_NS16550_SERIAL
33# define CONFIG_SYS_NS16550_REG_SIZE (-4)
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]34#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]35#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
36 115200}
37
38/* Select serial console configuration */
39#define CONFIG_CONS_INDEX 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]40#ifdef CONFIG_SPL_BUILD
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]41#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
42#define CONFIG_SERIAL3 3
Simon Glassbc0f4ea2014-10-22 21:37:15 -0600[diff] [blame]43#endif
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]44
45/* Physical Memory Map */
46#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
47#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
48
49/*
50 * OMAP3 has 12 GP timers, they can be driven by the system clock
51 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
52 * This rate is divided by a local divisor.
53 */
54#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
55
56#define CONFIG_SYS_MONITOR_LEN (256 << 10)
57
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]58/* SPL */
59#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rinid9f808d2014-04-03 07:52:53 -0400[diff] [blame]60#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
61 (64 << 20))
62
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]63#ifdef CONFIG_NAND
Tom Rinie10247f2014-04-03 15:17:15 -0400[diff] [blame]64#define CONFIG_SYS_NAND_BASE 0x30000000
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]65#endif
66
67/* Now bring in the rest of the common code. */
Nishanth Menonad63dd72015-07-22 18:05:41 -0500[diff] [blame]68#include <configs/ti_armv7_omap.h>
Enric Balletbò i Serra458d6032013-12-06 21:30:23 +0100[diff] [blame]69
70#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */