Blame - arch/arm/mach-socfpga/Kconfig - filogic/uboot

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Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Simon Goldschmidt	b1c4269	2019-04-09 21:02:05 +0200	[diff] [blame]	3	config NR_DRAM_BANKS
				4	default 1
				5
				6	config SPL_STACK_R_ADDR
				7	default 0x00800000 if TARGET_SOCFPGA_GEN5
				8
Simon Goldschmidt	4f57b9a	2019-04-09 21:02:06 +0200	[diff] [blame]	9	config SPL_SYS_MALLOC_F_LEN
				10	default 0x800 if TARGET_SOCFPGA_GEN5
				11
Dalon Westergreen	8d770f4	2017-02-10 17:15:34 -0800	[diff] [blame]	12	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
				13	default 0xa2
				14
Simon Goldschmidt	b1c4269	2019-04-09 21:02:05 +0200	[diff] [blame]	15	config SYS_MALLOC_F_LEN
				16	default 0x2000 if TARGET_SOCFPGA_ARRIA10
				17	default 0x2000 if TARGET_SOCFPGA_GEN5
				18
				19	config SYS_TEXT_BASE
				20	default 0x01000040 if TARGET_SOCFPGA_ARRIA10
				21	default 0x01000040 if TARGET_SOCFPGA_GEN5
				22
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	23	config TARGET_SOCFPGA_ARRIA5
				24	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	25	select TARGET_SOCFPGA_GEN5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	26
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	27	config TARGET_SOCFPGA_ARRIA10
				28	bool
Ley Foon Tan	17b9ba6	2019-05-06 09:55:59 +0800	[diff] [blame]	29	select SPL_ALTERA_SDRAM
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	30	select SPL_BOARD_INIT if SPL
Marek Vasut	e1dcd62	2018-07-30 15:56:19 +0200	[diff] [blame]	31	select CLK
				32	select SPL_CLK if SPL
Marek Vasut	69fbb88	2018-08-13 18:32:38 +0200	[diff] [blame]	33	select DM_I2C
Marek Vasut	700b2c6	2018-08-13 18:32:38 +0200	[diff] [blame]	34	select DM_RESET
				35	select SPL_DM_RESET if SPL
Marek Vasut	04c8f4f	2018-08-13 20:06:46 +0200	[diff] [blame]	36	select REGMAP
				37	select SPL_REGMAP if SPL
				38	select SYSCON
				39	select SPL_SYSCON if SPL
				40	select ETH_DESIGNWARE_SOCFPGA
Simon Goldschmidt	b1c4269	2019-04-09 21:02:05 +0200	[diff] [blame]	41	imply FPGA_SOCFPGA
				42	imply USE_TINY_PRINTF
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	43
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	44	config TARGET_SOCFPGA_CYCLONE5
				45	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	46	select TARGET_SOCFPGA_GEN5
				47
				48	config TARGET_SOCFPGA_GEN5
				49	bool
Ley Foon Tan	17b9ba6	2019-05-06 09:55:59 +0800	[diff] [blame]	50	select SPL_ALTERA_SDRAM
Simon Goldschmidt	b1c4269	2019-04-09 21:02:05 +0200	[diff] [blame]	51	imply FPGA_SOCFPGA
				52	imply SPL_STACK_R
				53	imply SPL_SYS_MALLOC_SIMPLE
				54	imply USE_TINY_PRINTF
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	55
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	56	config TARGET_SOCFPGA_STRATIX10
				57	bool
				58	select ARMV8_MULTIENTRY
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	59	select ARMV8_SET_SMPEN
Michal Simek	7e7ba3b	2018-07-23 15:55:15 +0200	[diff] [blame]	60	select ARMV8_SPIN_TABLE
Ang, Chee Hong	da9640e	2018-12-19 18:35:16 -0800	[diff] [blame]	61	select FPGA_STRATIX10
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	62
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	63	choice
				64	prompt "Altera SOCFPGA board select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	65	optional
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	66
Wolfgang Grandegger	7789aab2	2019-05-12 19:25:18 +0200	[diff] [blame]	67	config TARGET_SOCFPGA_ARIES_MCVEVK
				68	bool "Aries MCVEVK (Cyclone V)"
				69	select TARGET_SOCFPGA_CYCLONE5
				70
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	71	config TARGET_SOCFPGA_ARRIA10_SOCDK
				72	bool "Altera SOCFPGA SoCDK (Arria 10)"
				73	select TARGET_SOCFPGA_ARRIA10
				74
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	75	config TARGET_SOCFPGA_ARRIA5_SOCDK
				76	bool "Altera SOCFPGA SoCDK (Arria V)"
				77	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	78
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	79	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				80	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				81	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	82
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	83	config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
				84	bool "Devboards DBM-SoC1 (Cyclone V)"
				85	select TARGET_SOCFPGA_CYCLONE5
				86
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	87	config TARGET_SOCFPGA_EBV_SOCRATES
				88	bool "EBV SoCrates (Cyclone V)"
				89	select TARGET_SOCFPGA_CYCLONE5
				90
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	91	config TARGET_SOCFPGA_IS1
				92	bool "IS1 (Cyclone V)"
				93	select TARGET_SOCFPGA_CYCLONE5
				94
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	95	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				96	bool "samtec VIN\|ING FPGA (Cyclone V)"
Tom Rini	22d567e	2017-01-22 19:43:11 -0500	[diff] [blame]	97	select BOARD_LATE_INIT
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	98	select TARGET_SOCFPGA_CYCLONE5
				99
Marek Vasut	2e717ec	2016-06-08 02:57:05 +0200	[diff] [blame]	100	config TARGET_SOCFPGA_SR1500
				101	bool "SR1500 (Cyclone V)"
				102	select TARGET_SOCFPGA_CYCLONE5
				103
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	104	config TARGET_SOCFPGA_STRATIX10_SOCDK
				105	bool "Intel SOCFPGA SoCDK (Stratix 10)"
				106	select TARGET_SOCFPGA_STRATIX10
				107
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	108	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				109	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				110	select TARGET_SOCFPGA_CYCLONE5
				111
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	112	config TARGET_SOCFPGA_TERASIC_DE10_NANO
				113	bool "Terasic DE10-Nano (Cyclone V)"
				114	select TARGET_SOCFPGA_CYCLONE5
				115
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	116	config TARGET_SOCFPGA_TERASIC_DE1_SOC
				117	bool "Terasic DE1-SoC (Cyclone V)"
				118	select TARGET_SOCFPGA_CYCLONE5
				119
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	120	config TARGET_SOCFPGA_TERASIC_SOCKIT
				121	bool "Terasic SoCkit (Cyclone V)"
				122	select TARGET_SOCFPGA_CYCLONE5
				123
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	124	endchoice
				125
				126	config SYS_BOARD
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	127	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	128	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	129	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	130	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	131	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	132	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	133	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	134	default "is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger	7789aab2	2019-05-12 19:25:18 +0200	[diff] [blame]	135	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	136	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	137	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	138	default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	139	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	140	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	141
				142	config SYS_VENDOR
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	143	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	144	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	145	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	146	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Wolfgang Grandegger	7789aab2	2019-05-12 19:25:18 +0200	[diff] [blame]	147	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	148	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	149	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	150	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	151	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	152	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	153	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	154	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	155
				156	config SYS_SOC
				157	default "socfpga"
				158
				159	config SYS_CONFIG_NAME
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	160	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	161	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	162	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame]	163	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	164	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	165	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	166	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	167	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger	7789aab2	2019-05-12 19:25:18 +0200	[diff] [blame]	168	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	169	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	170	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	171	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan	9c407b5	2018-05-24 00:17:32 +0800	[diff] [blame]	172	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	173	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	174
				175	endif