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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +02002/*
3 * Copyright (C) 2004-2006 Atmel Corporation
4 *
Andreas Bießmannfb378682010-09-03 10:28:05 +02005 * Modified to support C structur SoC access by
6 * Andreas Bießmann <biessmann@corscience.de>
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +02007 */
8#include <common.h>
Wenyou Yang7c56e102017-04-14 15:01:28 +08009#include <clk.h>
Simon Glass7cbab242014-10-29 13:09:00 -060010#include <dm.h>
11#include <errno.h>
Simon Glass9bc15642020-02-03 07:36:16 -070012#include <malloc.h>
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +010013#include <watchdog.h>
Marek Vasutff093ed2012-09-13 16:50:30 +020014#include <serial.h>
Wenyou Yang6b611e62016-10-17 09:49:55 +080015#include <debug_uart.h>
Marek Vasutff093ed2012-09-13 16:50:30 +020016#include <linux/compiler.h>
Simon Glassdbd79542020-05-10 11:40:11 -060017#include <linux/delay.h>
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020018
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020019#include <asm/io.h>
Simon Glass7cbab242014-10-29 13:09:00 -060020#ifdef CONFIG_DM_SERIAL
21#include <asm/arch/atmel_serial.h>
22#endif
Haavard Skinnemoen0a2743f2006-11-19 18:06:53 +010023#include <asm/arch/clk.h>
Reinhard Meyer7f619cb2010-11-03 16:32:56 +010024#include <asm/arch/hardware.h>
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020025
26#include "atmel_usart.h"
27
28DECLARE_GLOBAL_DATA_PTR;
29
Wenyou Yangb045a602017-04-14 15:01:27 +080030#ifndef CONFIG_DM_SERIAL
Simon Glass1e5c2a82014-10-29 13:08:59 -060031static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
32 int baudrate)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020033{
34 unsigned long divisor;
35 unsigned long usart_hz;
36
37 /*
38 * Master Clock
39 * Baud Rate = --------------
40 * 16 * CD
41 */
Simon Glass1e5c2a82014-10-29 13:08:59 -060042 usart_hz = get_usart_clk_rate(id);
43 divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
Andreas Bießmannfb378682010-09-03 10:28:05 +020044 writel(USART3_BF(CD, divisor), &usart->brgr);
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020045}
46
Simon Glass1e5c2a82014-10-29 13:08:59 -060047static void atmel_serial_init_internal(atmel_usart3_t *usart)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020048{
Xu, Hong9db57992011-08-02 01:05:04 +000049 /*
50 * Just in case: drain transmitter register
51 * 1000us is enough for baudrate >= 9600
52 */
53 if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
54 __udelay(1000);
55
Andreas Bießmannfb378682010-09-03 10:28:05 +020056 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
Simon Glass1e5c2a82014-10-29 13:08:59 -060057}
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020058
Simon Glass1e5c2a82014-10-29 13:08:59 -060059static void atmel_serial_activate(atmel_usart3_t *usart)
60{
Andreas Bießmannfb378682010-09-03 10:28:05 +020061 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
Haavard Skinnemoen0a2743f2006-11-19 18:06:53 +010062 | USART3_BF(USCLKS, USART3_USCLKS_MCK)
63 | USART3_BF(CHRL, USART3_CHRL_8)
64 | USART3_BF(PAR, USART3_PAR_NONE)
Andreas Bießmannfb378682010-09-03 10:28:05 +020065 | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
66 &usart->mr);
Xu, Hong9db57992011-08-02 01:05:04 +000067 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
68 /* 100us is enough for the new settings to be settled */
69 __udelay(100);
Simon Glass1e5c2a82014-10-29 13:08:59 -060070}
71
72static void atmel_serial_setbrg(void)
73{
74 atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
75 CONFIG_USART_ID, gd->baudrate);
76}
77
78static int atmel_serial_init(void)
79{
80 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
81
82 atmel_serial_init_internal(usart);
83 serial_setbrg();
84 atmel_serial_activate(usart);
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020085
86 return 0;
87}
88
Marek Vasutff093ed2012-09-13 16:50:30 +020089static void atmel_serial_putc(char c)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020090{
Reinhard Meyer7f619cb2010-11-03 16:32:56 +010091 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
Andreas Bießmannfb378682010-09-03 10:28:05 +020092
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020093 if (c == '\n')
94 serial_putc('\r');
95
Andreas Bießmannfb378682010-09-03 10:28:05 +020096 while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
97 writel(c, &usart->thr);
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +020098}
99
Marek Vasutff093ed2012-09-13 16:50:30 +0200100static int atmel_serial_getc(void)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +0200101{
Reinhard Meyer7f619cb2010-11-03 16:32:56 +0100102 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
Andreas Bießmannfb378682010-09-03 10:28:05 +0200103
104 while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +0100105 WATCHDOG_RESET();
Andreas Bießmannfb378682010-09-03 10:28:05 +0200106 return readl(&usart->rhr);
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +0200107}
108
Marek Vasutff093ed2012-09-13 16:50:30 +0200109static int atmel_serial_tstc(void)
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +0200110{
Reinhard Meyer7f619cb2010-11-03 16:32:56 +0100111 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
Andreas Bießmannfb378682010-09-03 10:28:05 +0200112 return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
Wolfgang Denk5e1d9ec2006-10-24 14:31:24 +0200113}
Marek Vasutff093ed2012-09-13 16:50:30 +0200114
Marek Vasutff093ed2012-09-13 16:50:30 +0200115static struct serial_device atmel_serial_drv = {
116 .name = "atmel_serial",
117 .start = atmel_serial_init,
118 .stop = NULL,
119 .setbrg = atmel_serial_setbrg,
120 .putc = atmel_serial_putc,
Marek Vasutd9c64492012-10-06 14:07:02 +0000121 .puts = default_serial_puts,
Marek Vasutff093ed2012-09-13 16:50:30 +0200122 .getc = atmel_serial_getc,
123 .tstc = atmel_serial_tstc,
124};
125
126void atmel_serial_initialize(void)
127{
128 serial_register(&atmel_serial_drv);
129}
130
131__weak struct serial_device *default_serial_console(void)
132{
133 return &atmel_serial_drv;
134}
Simon Glass7cbab242014-10-29 13:09:00 -0600135#endif
136
137#ifdef CONFIG_DM_SERIAL
Wenyou Yang7c56e102017-04-14 15:01:28 +0800138enum serial_clk_type {
139 CLK_TYPE_NORMAL = 0,
140 CLK_TYPE_DBGU,
141};
Simon Glass7cbab242014-10-29 13:09:00 -0600142
143struct atmel_serial_priv {
144 atmel_usart3_t *usart;
Wenyou Yang7c56e102017-04-14 15:01:28 +0800145 ulong usart_clk_rate;
Simon Glass7cbab242014-10-29 13:09:00 -0600146};
147
Wenyou Yangb045a602017-04-14 15:01:27 +0800148static void _atmel_serial_set_brg(atmel_usart3_t *usart,
149 ulong usart_clk_rate, int baudrate)
150{
151 unsigned long divisor;
152
153 divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
154 writel(USART3_BF(CD, divisor), &usart->brgr);
155}
156
157void _atmel_serial_init(atmel_usart3_t *usart,
158 ulong usart_clk_rate, int baudrate)
159{
160 writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);
161
162 writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
163 USART3_BF(USCLKS, USART3_USCLKS_MCK) |
164 USART3_BF(CHRL, USART3_CHRL_8) |
165 USART3_BF(PAR, USART3_PAR_NONE) |
166 USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
167
168 _atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
169
170 writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
171 writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
172}
173
Simon Glass7cbab242014-10-29 13:09:00 -0600174int atmel_serial_setbrg(struct udevice *dev, int baudrate)
175{
176 struct atmel_serial_priv *priv = dev_get_priv(dev);
177
Wenyou Yang7c56e102017-04-14 15:01:28 +0800178 _atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
Simon Glass7cbab242014-10-29 13:09:00 -0600179
180 return 0;
181}
182
183static int atmel_serial_getc(struct udevice *dev)
184{
185 struct atmel_serial_priv *priv = dev_get_priv(dev);
186
187 if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
188 return -EAGAIN;
189
190 return readl(&priv->usart->rhr);
191}
192
193static int atmel_serial_putc(struct udevice *dev, const char ch)
194{
195 struct atmel_serial_priv *priv = dev_get_priv(dev);
196
197 if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
198 return -EAGAIN;
199
200 writel(ch, &priv->usart->thr);
201
202 return 0;
203}
204
205static int atmel_serial_pending(struct udevice *dev, bool input)
206{
207 struct atmel_serial_priv *priv = dev_get_priv(dev);
208 uint32_t csr = readl(&priv->usart->csr);
209
210 if (input)
211 return csr & USART3_BIT(RXRDY) ? 1 : 0;
212 else
213 return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
214}
215
216static const struct dm_serial_ops atmel_serial_ops = {
217 .putc = atmel_serial_putc,
218 .pending = atmel_serial_pending,
219 .getc = atmel_serial_getc,
220 .setbrg = atmel_serial_setbrg,
221};
222
Stefan Roeseb1f3da82019-04-03 15:24:19 +0200223#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
Wenyou Yang7c56e102017-04-14 15:01:28 +0800224static int atmel_serial_enable_clk(struct udevice *dev)
225{
226 struct atmel_serial_priv *priv = dev_get_priv(dev);
Stefan Roeseb1f3da82019-04-03 15:24:19 +0200227
228 /* Use fixed clock value in SPL */
229 priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
230
231 return 0;
232}
233#else
234static int atmel_serial_enable_clk(struct udevice *dev)
235{
236 struct atmel_serial_priv *priv = dev_get_priv(dev);
Wenyou Yang7c56e102017-04-14 15:01:28 +0800237 struct clk clk;
238 ulong clk_rate;
239 int ret;
240
241 ret = clk_get_by_index(dev, 0, &clk);
242 if (ret)
243 return -EINVAL;
244
245 if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
246 ret = clk_enable(&clk);
247 if (ret)
248 return ret;
249 }
250
251 clk_rate = clk_get_rate(&clk);
252 if (!clk_rate)
253 return -EINVAL;
254
255 priv->usart_clk_rate = clk_rate;
256
257 clk_free(&clk);
258
259 return 0;
260}
Stefan Roeseb1f3da82019-04-03 15:24:19 +0200261#endif
Wenyou Yang7c56e102017-04-14 15:01:28 +0800262
Simon Glass7cbab242014-10-29 13:09:00 -0600263static int atmel_serial_probe(struct udevice *dev)
264{
265 struct atmel_serial_platdata *plat = dev->platdata;
266 struct atmel_serial_priv *priv = dev_get_priv(dev);
Wenyou Yang7c56e102017-04-14 15:01:28 +0800267 int ret;
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800268#if CONFIG_IS_ENABLED(OF_CONTROL)
269 fdt_addr_t addr_base;
Simon Glass7cbab242014-10-29 13:09:00 -0600270
Simon Glassba1dea42017-05-17 17:18:05 -0600271 addr_base = devfdt_get_addr(dev);
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800272 if (addr_base == FDT_ADDR_T_NONE)
273 return -ENODEV;
274
275 plat->base_addr = (uint32_t)addr_base;
276#endif
Simon Glass7cbab242014-10-29 13:09:00 -0600277 priv->usart = (atmel_usart3_t *)plat->base_addr;
Wenyou Yangb045a602017-04-14 15:01:27 +0800278
Wenyou Yang7c56e102017-04-14 15:01:28 +0800279 ret = atmel_serial_enable_clk(dev);
280 if (ret)
281 return ret;
282
283 _atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
Simon Glass7cbab242014-10-29 13:09:00 -0600284
285 return 0;
286}
287
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800288#if CONFIG_IS_ENABLED(OF_CONTROL)
289static const struct udevice_id atmel_serial_ids[] = {
Wenyou Yang7c56e102017-04-14 15:01:28 +0800290 {
291 .compatible = "atmel,at91sam9260-dbgu",
292 .data = CLK_TYPE_DBGU,
293 },
294 {
295 .compatible = "atmel,at91sam9260-usart",
296 .data = CLK_TYPE_NORMAL,
297 },
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800298 { }
299};
300#endif
301
Simon Glass7cbab242014-10-29 13:09:00 -0600302U_BOOT_DRIVER(serial_atmel) = {
303 .name = "serial_atmel",
304 .id = UCLASS_SERIAL,
Wenyou Yangb0e59ee2016-06-01 08:36:56 +0800305#if CONFIG_IS_ENABLED(OF_CONTROL)
306 .of_match = atmel_serial_ids,
307 .platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
308#endif
Simon Glass7cbab242014-10-29 13:09:00 -0600309 .probe = atmel_serial_probe,
310 .ops = &atmel_serial_ops,
Bin Mengbdb33d82018-10-24 06:36:36 -0700311#if !CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glass7cbab242014-10-29 13:09:00 -0600312 .flags = DM_FLAG_PRE_RELOC,
Bin Mengbdb33d82018-10-24 06:36:36 -0700313#endif
Simon Glass7cbab242014-10-29 13:09:00 -0600314 .priv_auto_alloc_size = sizeof(struct atmel_serial_priv),
315};
316#endif
Wenyou Yang6b611e62016-10-17 09:49:55 +0800317
318#ifdef CONFIG_DEBUG_UART_ATMEL
319static inline void _debug_uart_init(void)
320{
321 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
322
Wenyou Yangb045a602017-04-14 15:01:27 +0800323 _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
Wenyou Yang6b611e62016-10-17 09:49:55 +0800324}
325
326static inline void _debug_uart_putc(int ch)
327{
328 atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
329
330 while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
331 ;
332
333 writel(ch, &usart->thr);
334}
335
336DEBUG_UART_FUNCS
337#endif