Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 1 | /* |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 3 | * Andy Fleming |
| 4 | * |
| 5 | * Based vaguely on the pxa mmc code: |
| 6 | * (C) Copyright 2003 |
| 7 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
| 8 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 9 | * SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <config.h> |
| 13 | #include <common.h> |
| 14 | #include <command.h> |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 15 | #include <hwconfig.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 16 | #include <mmc.h> |
| 17 | #include <part.h> |
| 18 | #include <malloc.h> |
| 19 | #include <mmc.h> |
| 20 | #include <fsl_esdhc.h> |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 21 | #include <fdt_support.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 22 | #include <asm/io.h> |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 23 | #include <dm.h> |
| 24 | #include <asm-generic/gpio.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 25 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
Ye.Li | 3d46c31 | 2014-11-04 15:35:49 +0800 | [diff] [blame] | 28 | #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ |
| 29 | IRQSTATEN_CINT | \ |
| 30 | IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ |
| 31 | IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \ |
| 32 | IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \ |
| 33 | IRQSTATEN_DINT) |
| 34 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 35 | struct fsl_esdhc { |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 36 | uint dsaddr; /* SDMA system address register */ |
| 37 | uint blkattr; /* Block attributes register */ |
| 38 | uint cmdarg; /* Command argument register */ |
| 39 | uint xfertyp; /* Transfer type register */ |
| 40 | uint cmdrsp0; /* Command response 0 register */ |
| 41 | uint cmdrsp1; /* Command response 1 register */ |
| 42 | uint cmdrsp2; /* Command response 2 register */ |
| 43 | uint cmdrsp3; /* Command response 3 register */ |
| 44 | uint datport; /* Buffer data port register */ |
| 45 | uint prsstat; /* Present state register */ |
| 46 | uint proctl; /* Protocol control register */ |
| 47 | uint sysctl; /* System Control Register */ |
| 48 | uint irqstat; /* Interrupt status register */ |
| 49 | uint irqstaten; /* Interrupt status enable register */ |
| 50 | uint irqsigen; /* Interrupt signal enable register */ |
| 51 | uint autoc12err; /* Auto CMD error status register */ |
| 52 | uint hostcapblt; /* Host controller capabilities register */ |
| 53 | uint wml; /* Watermark level register */ |
| 54 | uint mixctrl; /* For USDHC */ |
| 55 | char reserved1[4]; /* reserved */ |
| 56 | uint fevt; /* Force event register */ |
| 57 | uint admaes; /* ADMA error status register */ |
| 58 | uint adsaddr; /* ADMA system address register */ |
Peng Fan | a6eadd5 | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 59 | char reserved2[4]; |
| 60 | uint dllctrl; |
| 61 | uint dllstat; |
| 62 | uint clktunectrlstatus; |
| 63 | char reserved3[84]; |
| 64 | uint vendorspec; |
| 65 | uint mmcboot; |
| 66 | uint vendorspec2; |
| 67 | char reserved4[48]; |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 68 | uint hostver; /* Host controller version register */ |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 69 | char reserved5[4]; /* reserved */ |
Peng Fan | a6eadd5 | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 70 | uint dmaerraddr; /* DMA error address register */ |
Otavio Salvador | fad3e06 | 2015-02-17 10:42:43 -0200 | [diff] [blame] | 71 | char reserved6[4]; /* reserved */ |
Peng Fan | a6eadd5 | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 72 | uint dmaerrattr; /* DMA error attribute register */ |
| 73 | char reserved7[4]; /* reserved */ |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 74 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
Peng Fan | a6eadd5 | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 75 | char reserved8[8]; /* reserved */ |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 76 | uint tcr; /* Tuning control register */ |
Peng Fan | a6eadd5 | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 77 | char reserved9[28]; /* reserved */ |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 78 | uint sddirctl; /* SD direction control register */ |
Peng Fan | a6eadd5 | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 79 | char reserved10[712];/* reserved */ |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 80 | uint scr; /* eSDHC control register */ |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 81 | }; |
| 82 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 83 | /** |
| 84 | * struct fsl_esdhc_priv |
| 85 | * |
| 86 | * @esdhc_regs: registers of the sdhc controller |
| 87 | * @sdhc_clk: Current clk of the sdhc controller |
| 88 | * @bus_width: bus width, 1bit, 4bit or 8bit |
| 89 | * @cfg: mmc config |
| 90 | * @mmc: mmc |
| 91 | * Following is used when Driver Model is enabled for MMC |
| 92 | * @dev: pointer for the device |
| 93 | * @non_removable: 0: removable; 1: non-removable |
Peng Fan | 01eb1c4 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 94 | * @wp_enable: 1: enable checking wp; 0: no check |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 95 | * @cd_gpio: gpio for card detection |
Peng Fan | 01eb1c4 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 96 | * @wp_gpio: gpio for write protection |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 97 | */ |
| 98 | struct fsl_esdhc_priv { |
| 99 | struct fsl_esdhc *esdhc_regs; |
| 100 | unsigned int sdhc_clk; |
| 101 | unsigned int bus_width; |
| 102 | struct mmc_config cfg; |
| 103 | struct mmc *mmc; |
| 104 | struct udevice *dev; |
| 105 | int non_removable; |
Peng Fan | 01eb1c4 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 106 | int wp_enable; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 107 | struct gpio_desc cd_gpio; |
Peng Fan | 01eb1c4 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 108 | struct gpio_desc wp_gpio; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 109 | }; |
| 110 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 111 | /* Return the XFERTYP flags for a given command and data packet */ |
Kim Phillips | f9e0b60 | 2012-10-29 13:34:44 +0000 | [diff] [blame] | 112 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 113 | { |
| 114 | uint xfertyp = 0; |
| 115 | |
| 116 | if (data) { |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 117 | xfertyp |= XFERTYP_DPSEL; |
| 118 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 119 | xfertyp |= XFERTYP_DMAEN; |
| 120 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 121 | if (data->blocks > 1) { |
| 122 | xfertyp |= XFERTYP_MSBSEL; |
| 123 | xfertyp |= XFERTYP_BCEN; |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 124 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 125 | xfertyp |= XFERTYP_AC12EN; |
| 126 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | if (data->flags & MMC_DATA_READ) |
| 130 | xfertyp |= XFERTYP_DTDSEL; |
| 131 | } |
| 132 | |
| 133 | if (cmd->resp_type & MMC_RSP_CRC) |
| 134 | xfertyp |= XFERTYP_CCCEN; |
| 135 | if (cmd->resp_type & MMC_RSP_OPCODE) |
| 136 | xfertyp |= XFERTYP_CICEN; |
| 137 | if (cmd->resp_type & MMC_RSP_136) |
| 138 | xfertyp |= XFERTYP_RSPTYP_136; |
| 139 | else if (cmd->resp_type & MMC_RSP_BUSY) |
| 140 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; |
| 141 | else if (cmd->resp_type & MMC_RSP_PRESENT) |
| 142 | xfertyp |= XFERTYP_RSPTYP_48; |
| 143 | |
Jason Liu | bef0ff0 | 2011-03-22 01:32:31 +0000 | [diff] [blame] | 144 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 145 | xfertyp |= XFERTYP_CMDTYP_ABORT; |
Yangbo Lu | b73a3d6 | 2016-01-21 17:33:19 +0800 | [diff] [blame] | 146 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 147 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
| 148 | } |
| 149 | |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 150 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 151 | /* |
| 152 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. |
| 153 | */ |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 154 | static void |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 155 | esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) |
| 156 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 157 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 158 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 159 | uint blocks; |
| 160 | char *buffer; |
| 161 | uint databuf; |
| 162 | uint size; |
| 163 | uint irqstat; |
| 164 | uint timeout; |
| 165 | |
| 166 | if (data->flags & MMC_DATA_READ) { |
| 167 | blocks = data->blocks; |
| 168 | buffer = data->dest; |
| 169 | while (blocks) { |
| 170 | timeout = PIO_TIMEOUT; |
| 171 | size = data->blocksize; |
| 172 | irqstat = esdhc_read32(®s->irqstat); |
| 173 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) |
| 174 | && --timeout); |
| 175 | if (timeout <= 0) { |
| 176 | printf("\nData Read Failed in PIO Mode."); |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 177 | return; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 178 | } |
| 179 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 180 | udelay(100); /* Wait before last byte transfer complete */ |
| 181 | irqstat = esdhc_read32(®s->irqstat); |
| 182 | databuf = in_le32(®s->datport); |
| 183 | *((uint *)buffer) = databuf; |
| 184 | buffer += 4; |
| 185 | size -= 4; |
| 186 | } |
| 187 | blocks--; |
| 188 | } |
| 189 | } else { |
| 190 | blocks = data->blocks; |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 191 | buffer = (char *)data->src; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 192 | while (blocks) { |
| 193 | timeout = PIO_TIMEOUT; |
| 194 | size = data->blocksize; |
| 195 | irqstat = esdhc_read32(®s->irqstat); |
| 196 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) |
| 197 | && --timeout); |
| 198 | if (timeout <= 0) { |
| 199 | printf("\nData Write Failed in PIO Mode."); |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 200 | return; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 201 | } |
| 202 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 203 | udelay(100); /* Wait before last byte transfer complete */ |
| 204 | databuf = *((uint *)buffer); |
| 205 | buffer += 4; |
| 206 | size -= 4; |
| 207 | irqstat = esdhc_read32(®s->irqstat); |
| 208 | out_le32(®s->datport, databuf); |
| 209 | } |
| 210 | blocks--; |
| 211 | } |
| 212 | } |
| 213 | } |
| 214 | #endif |
| 215 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 216 | static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) |
| 217 | { |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 218 | int timeout; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 219 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 220 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 221 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 222 | dma_addr_t addr; |
| 223 | #endif |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 224 | uint wml_value; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 225 | |
| 226 | wml_value = data->blocksize/4; |
| 227 | |
| 228 | if (data->flags & MMC_DATA_READ) { |
Priyanka Jain | 0244963 | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 229 | if (wml_value > WML_RD_WML_MAX) |
| 230 | wml_value = WML_RD_WML_MAX_VAL; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 231 | |
Roy Zang | e5853af | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 232 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 233 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 234 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 235 | addr = virt_to_phys((void *)(data->dest)); |
| 236 | if (upper_32_bits(addr)) |
| 237 | printf("Error found for upper 32 bits\n"); |
| 238 | else |
| 239 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); |
| 240 | #else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 241 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 242 | #endif |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 243 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 244 | } else { |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 245 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 246 | flush_dcache_range((ulong)data->src, |
| 247 | (ulong)data->src+data->blocks |
| 248 | *data->blocksize); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 249 | #endif |
Priyanka Jain | 0244963 | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 250 | if (wml_value > WML_WR_WML_MAX) |
| 251 | wml_value = WML_WR_WML_MAX_VAL; |
Peng Fan | 01eb1c4 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 252 | if (priv->wp_enable) { |
| 253 | if ((esdhc_read32(®s->prsstat) & |
| 254 | PRSSTAT_WPSPL) == 0) { |
| 255 | printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); |
| 256 | return TIMEOUT; |
| 257 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 258 | } |
Roy Zang | e5853af | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 259 | |
| 260 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, |
| 261 | wml_value << 16); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 262 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 263 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 264 | addr = virt_to_phys((void *)(data->src)); |
| 265 | if (upper_32_bits(addr)) |
| 266 | printf("Error found for upper 32 bits\n"); |
| 267 | else |
| 268 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); |
| 269 | #else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 270 | esdhc_write32(®s->dsaddr, (u32)data->src); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 271 | #endif |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 272 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 273 | } |
| 274 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 275 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 276 | |
| 277 | /* Calculate the timeout period for data transactions */ |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 278 | /* |
| 279 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles |
| 280 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec |
| 281 | * So, Number of SD Clock cycles for 0.25sec should be minimum |
| 282 | * (SD Clock/sec * 0.25 sec) SD Clock cycles |
Andrew Gabbasov | d5b4866 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 283 | * = (mmc->clock * 1/4) SD Clock cycles |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 284 | * As 1) >= 2) |
Andrew Gabbasov | d5b4866 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 285 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 286 | * Taking log2 both the sides |
Andrew Gabbasov | d5b4866 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 287 | * => timeout + 13 >= log2(mmc->clock/4) |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 288 | * Rounding up to next power of 2 |
Andrew Gabbasov | d5b4866 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 289 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
| 290 | * => timeout + 13 = fls(mmc->clock/4) |
Yangbo Lu | 9d7f321 | 2015-12-30 14:19:30 +0800 | [diff] [blame] | 291 | * |
| 292 | * However, the MMC spec "It is strongly recommended for hosts to |
| 293 | * implement more than 500ms timeout value even if the card |
| 294 | * indicates the 250ms maximum busy length." Even the previous |
| 295 | * value of 300ms is known to be insufficient for some cards. |
| 296 | * So, we use |
| 297 | * => timeout + 13 = fls(mmc->clock/2) |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 298 | */ |
Yangbo Lu | 9d7f321 | 2015-12-30 14:19:30 +0800 | [diff] [blame] | 299 | timeout = fls(mmc->clock/2); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 300 | timeout -= 13; |
| 301 | |
| 302 | if (timeout > 14) |
| 303 | timeout = 14; |
| 304 | |
| 305 | if (timeout < 0) |
| 306 | timeout = 0; |
| 307 | |
Kumar Gala | 9a878d5 | 2011-01-29 15:36:10 -0600 | [diff] [blame] | 308 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 309 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) |
| 310 | timeout++; |
| 311 | #endif |
| 312 | |
Haijun.Zhang | edeb83a | 2014-03-18 17:04:23 +0800 | [diff] [blame] | 313 | #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
| 314 | timeout = 0xE; |
| 315 | #endif |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 316 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 321 | static void check_and_invalidate_dcache_range |
| 322 | (struct mmc_cmd *cmd, |
| 323 | struct mmc_data *data) { |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 324 | unsigned start = 0; |
Yangbo Lu | e7702c6 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 325 | unsigned end = 0; |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 326 | unsigned size = roundup(ARCH_DMA_MINALIGN, |
| 327 | data->blocks*data->blocksize); |
Eddy Petrișor | 5178dc1 | 2016-06-05 03:43:00 +0300 | [diff] [blame] | 328 | #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 329 | dma_addr_t addr; |
| 330 | |
| 331 | addr = virt_to_phys((void *)(data->dest)); |
| 332 | if (upper_32_bits(addr)) |
| 333 | printf("Error found for upper 32 bits\n"); |
| 334 | else |
| 335 | start = lower_32_bits(addr); |
Yangbo Lu | e7702c6 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 336 | #else |
| 337 | start = (unsigned)data->dest; |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 338 | #endif |
Yangbo Lu | e7702c6 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 339 | end = start + size; |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 340 | invalidate_dcache_range(start, end); |
| 341 | } |
Tom Rini | 239dd25 | 2014-05-23 09:19:05 -0400 | [diff] [blame] | 342 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 343 | /* |
| 344 | * Sends a command out on the bus. Takes the mmc pointer, |
| 345 | * a command pointer, and an optional data pointer. |
| 346 | */ |
| 347 | static int |
| 348 | esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
| 349 | { |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 350 | int err = 0; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 351 | uint xfertyp; |
| 352 | uint irqstat; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 353 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 354 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 355 | |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 356 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 357 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 358 | return 0; |
| 359 | #endif |
| 360 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 361 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 362 | |
| 363 | sync(); |
| 364 | |
| 365 | /* Wait for the bus to be idle */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 366 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
| 367 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) |
| 368 | ; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 369 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 370 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
| 371 | ; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 372 | |
| 373 | /* Wait at least 8 SD clock cycles before the next command */ |
| 374 | /* |
| 375 | * Note: This is way more than 8 cycles, but 1ms seems to |
| 376 | * resolve timing issues with some cards |
| 377 | */ |
| 378 | udelay(1000); |
| 379 | |
| 380 | /* Set up for a data transfer if we have one */ |
| 381 | if (data) { |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 382 | err = esdhc_setup_data(mmc, data); |
| 383 | if(err) |
| 384 | return err; |
Peng Fan | 9cb5e99 | 2015-06-25 10:32:26 +0800 | [diff] [blame] | 385 | |
| 386 | if (data->flags & MMC_DATA_READ) |
| 387 | check_and_invalidate_dcache_range(cmd, data); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | /* Figure out the transfer arguments */ |
| 391 | xfertyp = esdhc_xfertyp(cmd, data); |
| 392 | |
Andrew Gabbasov | 4816b7a | 2013-06-11 10:34:22 -0500 | [diff] [blame] | 393 | /* Mask all irqs */ |
| 394 | esdhc_write32(®s->irqsigen, 0); |
| 395 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 396 | /* Send the command */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 397 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
Jason Liu | 9919d64 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 398 | #if defined(CONFIG_FSL_USDHC) |
| 399 | esdhc_write32(®s->mixctrl, |
Volodymyr Riazantsev | d251e11 | 2015-01-20 10:16:44 -0500 | [diff] [blame] | 400 | (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) |
| 401 | | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); |
Jason Liu | 9919d64 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 402 | esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); |
| 403 | #else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 404 | esdhc_write32(®s->xfertyp, xfertyp); |
Jason Liu | 9919d64 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 405 | #endif |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 406 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 407 | /* Wait for the command to complete */ |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 408 | while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 409 | ; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 410 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 411 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 412 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 413 | if (irqstat & CMD_ERR) { |
| 414 | err = COMM_ERR; |
| 415 | goto out; |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 416 | } |
| 417 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 418 | if (irqstat & IRQSTAT_CTOE) { |
| 419 | err = TIMEOUT; |
| 420 | goto out; |
| 421 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 422 | |
Otavio Salvador | fad3e06 | 2015-02-17 10:42:43 -0200 | [diff] [blame] | 423 | /* Switch voltage to 1.8V if CMD11 succeeded */ |
| 424 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { |
| 425 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); |
| 426 | |
| 427 | printf("Run CMD11 1.8V switch\n"); |
| 428 | /* Sleep for 5 ms - max time for card to switch to 1.8V */ |
| 429 | udelay(5000); |
| 430 | } |
| 431 | |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 432 | /* Workaround for ESDHC errata ENGcm03648 */ |
| 433 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { |
Yangbo Lu | 3ffa851 | 2015-04-15 10:13:12 +0800 | [diff] [blame] | 434 | int timeout = 6000; |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 435 | |
Yangbo Lu | 3ffa851 | 2015-04-15 10:13:12 +0800 | [diff] [blame] | 436 | /* Poll on DATA0 line for cmd with busy signal for 600 ms */ |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 437 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
| 438 | PRSSTAT_DAT0)) { |
| 439 | udelay(100); |
| 440 | timeout--; |
| 441 | } |
| 442 | |
| 443 | if (timeout <= 0) { |
| 444 | printf("Timeout waiting for DAT0 to go high!\n"); |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 445 | err = TIMEOUT; |
| 446 | goto out; |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 447 | } |
| 448 | } |
| 449 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 450 | /* Copy the response to the response buffer */ |
| 451 | if (cmd->resp_type & MMC_RSP_136) { |
| 452 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; |
| 453 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 454 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
| 455 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); |
| 456 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); |
| 457 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); |
Rabin Vincent | b6eed94 | 2009-04-05 13:30:56 +0530 | [diff] [blame] | 458 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
| 459 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); |
| 460 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); |
| 461 | cmd->response[3] = (cmdrsp0 << 8); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 462 | } else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 463 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 464 | |
| 465 | /* Wait until all of the blocks are transferred */ |
| 466 | if (data) { |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 467 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 468 | esdhc_pio_read_write(mmc, data); |
| 469 | #else |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 470 | do { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 471 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 472 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 473 | if (irqstat & IRQSTAT_DTOE) { |
| 474 | err = TIMEOUT; |
| 475 | goto out; |
| 476 | } |
Frans Meulenbroeks | 010ba98 | 2010-07-31 04:45:18 +0000 | [diff] [blame] | 477 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 478 | if (irqstat & DATA_ERR) { |
| 479 | err = COMM_ERR; |
| 480 | goto out; |
| 481 | } |
Andrew Gabbasov | 4a92962 | 2013-04-07 23:06:08 +0000 | [diff] [blame] | 482 | } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 483 | |
Peng Fan | 9cb5e99 | 2015-06-25 10:32:26 +0800 | [diff] [blame] | 484 | /* |
| 485 | * Need invalidate the dcache here again to avoid any |
| 486 | * cache-fill during the DMA operations such as the |
| 487 | * speculative pre-fetching etc. |
| 488 | */ |
Eric Nelson | 70e6869 | 2013-04-03 12:31:56 +0000 | [diff] [blame] | 489 | if (data->flags & MMC_DATA_READ) |
| 490 | check_and_invalidate_dcache_range(cmd, data); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 491 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 492 | } |
| 493 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 494 | out: |
| 495 | /* Reset CMD and DATA portions on error */ |
| 496 | if (err) { |
| 497 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | |
| 498 | SYSCTL_RSTC); |
| 499 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) |
| 500 | ; |
| 501 | |
| 502 | if (data) { |
| 503 | esdhc_write32(®s->sysctl, |
| 504 | esdhc_read32(®s->sysctl) | |
| 505 | SYSCTL_RSTD); |
| 506 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) |
| 507 | ; |
| 508 | } |
Otavio Salvador | fad3e06 | 2015-02-17 10:42:43 -0200 | [diff] [blame] | 509 | |
| 510 | /* If this was CMD11, then notify that power cycle is needed */ |
| 511 | if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) |
| 512 | printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n"); |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 513 | } |
| 514 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 515 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 516 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 517 | return err; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 518 | } |
| 519 | |
Kim Phillips | f9e0b60 | 2012-10-29 13:34:44 +0000 | [diff] [blame] | 520 | static void set_sysctl(struct mmc *mmc, uint clock) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 521 | { |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 522 | int div, pre_div; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 523 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 524 | struct fsl_esdhc *regs = priv->esdhc_regs; |
| 525 | int sdhc_clk = priv->sdhc_clk; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 526 | uint clk; |
| 527 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 528 | if (clock < mmc->cfg->f_min) |
| 529 | clock = mmc->cfg->f_min; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 530 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 531 | if (sdhc_clk / 16 > clock) { |
| 532 | for (pre_div = 2; pre_div < 256; pre_div *= 2) |
| 533 | if ((sdhc_clk / pre_div) <= (clock * 16)) |
| 534 | break; |
| 535 | } else |
| 536 | pre_div = 2; |
| 537 | |
| 538 | for (div = 1; div <= 16; div++) |
| 539 | if ((sdhc_clk / (div * pre_div)) <= clock) |
| 540 | break; |
| 541 | |
Volodymyr Riazantsev | d251e11 | 2015-01-20 10:16:44 -0500 | [diff] [blame] | 542 | pre_div >>= mmc->ddr_mode ? 2 : 1; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 543 | div -= 1; |
| 544 | |
| 545 | clk = (pre_div << 8) | (div << 4); |
| 546 | |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 547 | #ifdef CONFIG_FSL_USDHC |
Ye Li | 5a24f29 | 2016-06-15 10:53:01 +0800 | [diff] [blame] | 548 | esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 549 | #else |
Kumar Gala | 09876a3 | 2010-03-18 15:51:05 -0500 | [diff] [blame] | 550 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 551 | #endif |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 552 | |
| 553 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 554 | |
| 555 | udelay(10000); |
| 556 | |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 557 | #ifdef CONFIG_FSL_USDHC |
Ye Li | 5a24f29 | 2016-06-15 10:53:01 +0800 | [diff] [blame] | 558 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 559 | #else |
| 560 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); |
| 561 | #endif |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 562 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 563 | } |
| 564 | |
Yangbo Lu | 163beec | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 565 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
| 566 | static void esdhc_clock_control(struct mmc *mmc, bool enable) |
| 567 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 568 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 569 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Yangbo Lu | 163beec | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 570 | u32 value; |
| 571 | u32 time_out; |
| 572 | |
| 573 | value = esdhc_read32(®s->sysctl); |
| 574 | |
| 575 | if (enable) |
| 576 | value |= SYSCTL_CKEN; |
| 577 | else |
| 578 | value &= ~SYSCTL_CKEN; |
| 579 | |
| 580 | esdhc_write32(®s->sysctl, value); |
| 581 | |
| 582 | time_out = 20; |
| 583 | value = PRSSTAT_SDSTB; |
| 584 | while (!(esdhc_read32(®s->prsstat) & value)) { |
| 585 | if (time_out == 0) { |
| 586 | printf("fsl_esdhc: Internal clock never stabilised.\n"); |
| 587 | break; |
| 588 | } |
| 589 | time_out--; |
| 590 | mdelay(1); |
| 591 | } |
| 592 | } |
| 593 | #endif |
| 594 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 595 | static void esdhc_set_ios(struct mmc *mmc) |
| 596 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 597 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 598 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 599 | |
Yangbo Lu | 163beec | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 600 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
| 601 | /* Select to use peripheral clock */ |
| 602 | esdhc_clock_control(mmc, false); |
| 603 | esdhc_setbits32(®s->scr, ESDHCCTL_PCS); |
| 604 | esdhc_clock_control(mmc, true); |
| 605 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 606 | /* Set the clock speed */ |
| 607 | set_sysctl(mmc, mmc->clock); |
| 608 | |
| 609 | /* Set the bus width */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 610 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 611 | |
| 612 | if (mmc->bus_width == 4) |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 613 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 614 | else if (mmc->bus_width == 8) |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 615 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
| 616 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 617 | } |
| 618 | |
| 619 | static int esdhc_init(struct mmc *mmc) |
| 620 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 621 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 622 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 623 | int timeout = 1000; |
| 624 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 625 | /* Reset the entire host controller */ |
Dirk Behme | dbe6725 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 626 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 627 | |
| 628 | /* Wait until the controller is available */ |
| 629 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) |
| 630 | udelay(1000); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 631 | |
Peng Fan | a6eadd5 | 2016-06-15 10:53:00 +0800 | [diff] [blame] | 632 | #if defined(CONFIG_FSL_USDHC) |
| 633 | /* RSTA doesn't reset MMC_BOOT register, so manually reset it */ |
| 634 | esdhc_write32(®s->mmcboot, 0x0); |
| 635 | /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */ |
| 636 | esdhc_write32(®s->mixctrl, 0x0); |
| 637 | esdhc_write32(®s->clktunectrlstatus, 0x0); |
| 638 | |
| 639 | /* Put VEND_SPEC to default value */ |
| 640 | esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); |
| 641 | |
| 642 | /* Disable DLL_CTRL delay line */ |
| 643 | esdhc_write32(®s->dllctrl, 0x0); |
| 644 | #endif |
| 645 | |
Benoît Thébaudeau | c08d11c | 2012-08-13 07:28:16 +0000 | [diff] [blame] | 646 | #ifndef ARCH_MXC |
P.V.Suresh | 7b1868b | 2010-12-04 10:37:23 +0530 | [diff] [blame] | 647 | /* Enable cache snooping */ |
Benoît Thébaudeau | c08d11c | 2012-08-13 07:28:16 +0000 | [diff] [blame] | 648 | esdhc_write32(®s->scr, 0x00000040); |
| 649 | #endif |
P.V.Suresh | 7b1868b | 2010-12-04 10:37:23 +0530 | [diff] [blame] | 650 | |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 651 | #ifndef CONFIG_FSL_USDHC |
Dirk Behme | dbe6725 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 652 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
Ye Li | 5a24f29 | 2016-06-15 10:53:01 +0800 | [diff] [blame] | 653 | #else |
| 654 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 655 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 656 | |
| 657 | /* Set the initial clock speed */ |
Jerry Huang | 0caea1a | 2010-11-25 17:06:07 +0000 | [diff] [blame] | 658 | mmc_set_clock(mmc, 400000); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 659 | |
| 660 | /* Disable the BRR and BWR bits in IRQSTAT */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 661 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 662 | |
| 663 | /* Put the PROCTL reg back to the default */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 664 | esdhc_write32(®s->proctl, PROCTL_INIT); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 665 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 666 | /* Set timout to the maximum value */ |
| 667 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 668 | |
Otavio Salvador | 12b2a87 | 2015-02-17 10:42:44 -0200 | [diff] [blame] | 669 | #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT |
| 670 | esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); |
| 671 | #endif |
| 672 | |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 673 | return 0; |
| 674 | } |
| 675 | |
| 676 | static int esdhc_getcd(struct mmc *mmc) |
| 677 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 678 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 679 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 680 | int timeout = 1000; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 681 | |
Haijun.Zhang | 05f5854 | 2014-01-10 13:52:17 +0800 | [diff] [blame] | 682 | #ifdef CONFIG_ESDHC_DETECT_QUIRK |
| 683 | if (CONFIG_ESDHC_DETECT_QUIRK) |
| 684 | return 1; |
| 685 | #endif |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 686 | |
| 687 | #ifdef CONFIG_DM_MMC |
| 688 | if (priv->non_removable) |
| 689 | return 1; |
| 690 | |
| 691 | if (dm_gpio_is_valid(&priv->cd_gpio)) |
| 692 | return dm_gpio_get_value(&priv->cd_gpio); |
| 693 | #endif |
| 694 | |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 695 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) |
| 696 | udelay(1000); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 697 | |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 698 | return timeout > 0; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 699 | } |
| 700 | |
Jerry Huang | b7ef756 | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 701 | static void esdhc_reset(struct fsl_esdhc *regs) |
| 702 | { |
| 703 | unsigned long timeout = 100; /* wait max 100 ms */ |
| 704 | |
| 705 | /* reset the controller */ |
Dirk Behme | dbe6725 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 706 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
Jerry Huang | b7ef756 | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 707 | |
| 708 | /* hardware clears the bit when it is done */ |
| 709 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) |
| 710 | udelay(1000); |
| 711 | if (!timeout) |
| 712 | printf("MMC/SD: Reset never completed.\n"); |
| 713 | } |
| 714 | |
Pantelis Antoniou | c9e7591 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 715 | static const struct mmc_ops esdhc_ops = { |
| 716 | .send_cmd = esdhc_send_cmd, |
| 717 | .set_ios = esdhc_set_ios, |
| 718 | .init = esdhc_init, |
| 719 | .getcd = esdhc_getcd, |
| 720 | }; |
| 721 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 722 | static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, |
| 723 | struct fsl_esdhc_priv *priv) |
| 724 | { |
| 725 | if (!cfg || !priv) |
| 726 | return -EINVAL; |
| 727 | |
| 728 | priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); |
| 729 | priv->bus_width = cfg->max_bus_width; |
| 730 | priv->sdhc_clk = cfg->sdhc_clk; |
Peng Fan | 01eb1c4 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 731 | priv->wp_enable = cfg->wp_enable; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 732 | |
| 733 | return 0; |
| 734 | }; |
| 735 | |
| 736 | static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 737 | { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 738 | struct fsl_esdhc *regs; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 739 | struct mmc *mmc; |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 740 | u32 caps, voltage_caps; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 741 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 742 | if (!priv) |
| 743 | return -EINVAL; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 744 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 745 | regs = priv->esdhc_regs; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 746 | |
Jerry Huang | b7ef756 | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 747 | /* First reset the eSDHC controller */ |
| 748 | esdhc_reset(regs); |
| 749 | |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 750 | #ifndef CONFIG_FSL_USDHC |
Jerry Huang | 4e3bfa0 | 2012-05-17 23:57:02 +0000 | [diff] [blame] | 751 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
| 752 | | SYSCTL_IPGEN | SYSCTL_CKEN); |
Ye Li | 5a24f29 | 2016-06-15 10:53:01 +0800 | [diff] [blame] | 753 | #else |
| 754 | esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | |
| 755 | VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 756 | #endif |
Jerry Huang | 4e3bfa0 | 2012-05-17 23:57:02 +0000 | [diff] [blame] | 757 | |
Ye.Li | 3d46c31 | 2014-11-04 15:35:49 +0800 | [diff] [blame] | 758 | writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 759 | memset(&priv->cfg, 0, sizeof(priv->cfg)); |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 760 | |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 761 | voltage_caps = 0; |
Wang Huan | c929213 | 2014-09-05 13:52:40 +0800 | [diff] [blame] | 762 | caps = esdhc_read32(®s->hostcapblt); |
Roy Zang | 3935661 | 2011-01-07 00:06:47 -0600 | [diff] [blame] | 763 | |
| 764 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 |
| 765 | caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | |
| 766 | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); |
| 767 | #endif |
Haijun.Zhang | 8a065e9 | 2013-10-31 09:38:19 +0800 | [diff] [blame] | 768 | |
| 769 | /* T4240 host controller capabilities register should have VS33 bit */ |
| 770 | #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
| 771 | caps = caps | ESDHC_HOSTCAPBLT_VS33; |
| 772 | #endif |
| 773 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 774 | if (caps & ESDHC_HOSTCAPBLT_VS18) |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 775 | voltage_caps |= MMC_VDD_165_195; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 776 | if (caps & ESDHC_HOSTCAPBLT_VS30) |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 777 | voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 778 | if (caps & ESDHC_HOSTCAPBLT_VS33) |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 779 | voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; |
| 780 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 781 | priv->cfg.name = "FSL_SDHC"; |
| 782 | priv->cfg.ops = &esdhc_ops; |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 783 | #ifdef CONFIG_SYS_SD_VOLTAGE |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 784 | priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 785 | #else |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 786 | priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 787 | #endif |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 788 | if ((priv->cfg.voltages & voltage_caps) == 0) { |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 789 | printf("voltage not supported by controller\n"); |
| 790 | return -1; |
| 791 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 792 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 793 | if (priv->bus_width == 8) |
| 794 | priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
| 795 | else if (priv->bus_width == 4) |
| 796 | priv->cfg.host_caps = MMC_MODE_4BIT; |
| 797 | |
| 798 | priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
Volodymyr Riazantsev | d251e11 | 2015-01-20 10:16:44 -0500 | [diff] [blame] | 799 | #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 800 | priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; |
Volodymyr Riazantsev | d251e11 | 2015-01-20 10:16:44 -0500 | [diff] [blame] | 801 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 802 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 803 | if (priv->bus_width > 0) { |
| 804 | if (priv->bus_width < 8) |
| 805 | priv->cfg.host_caps &= ~MMC_MODE_8BIT; |
| 806 | if (priv->bus_width < 4) |
| 807 | priv->cfg.host_caps &= ~MMC_MODE_4BIT; |
Abbas Raza | e6bf977 | 2013-03-25 09:13:34 +0000 | [diff] [blame] | 808 | } |
| 809 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 810 | if (caps & ESDHC_HOSTCAPBLT_HSS) |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 811 | priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 812 | |
Haijun.Zhang | f0fe8ad | 2014-01-10 13:52:18 +0800 | [diff] [blame] | 813 | #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK |
| 814 | if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 815 | priv->cfg.host_caps &= ~MMC_MODE_8BIT; |
Haijun.Zhang | f0fe8ad | 2014-01-10 13:52:18 +0800 | [diff] [blame] | 816 | #endif |
| 817 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 818 | priv->cfg.f_min = 400000; |
| 819 | priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 820 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 821 | priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 822 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 823 | mmc = mmc_create(&priv->cfg, priv); |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 824 | if (mmc == NULL) |
| 825 | return -1; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 826 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 827 | priv->mmc = mmc; |
| 828 | |
| 829 | return 0; |
| 830 | } |
| 831 | |
| 832 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) |
| 833 | { |
| 834 | struct fsl_esdhc_priv *priv; |
| 835 | int ret; |
| 836 | |
| 837 | if (!cfg) |
| 838 | return -EINVAL; |
| 839 | |
| 840 | priv = calloc(sizeof(struct fsl_esdhc_priv), 1); |
| 841 | if (!priv) |
| 842 | return -ENOMEM; |
| 843 | |
| 844 | ret = fsl_esdhc_cfg_to_priv(cfg, priv); |
| 845 | if (ret) { |
| 846 | debug("%s xlate failure\n", __func__); |
| 847 | free(priv); |
| 848 | return ret; |
| 849 | } |
| 850 | |
| 851 | ret = fsl_esdhc_init(priv); |
| 852 | if (ret) { |
| 853 | debug("%s init failure\n", __func__); |
| 854 | free(priv); |
| 855 | return ret; |
| 856 | } |
| 857 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 858 | return 0; |
| 859 | } |
| 860 | |
| 861 | int fsl_esdhc_mmc_init(bd_t *bis) |
| 862 | { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 863 | struct fsl_esdhc_cfg *cfg; |
| 864 | |
Fabio Estevam | 6592a99 | 2012-12-27 08:51:08 +0000 | [diff] [blame] | 865 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 866 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
Simon Glass | 9e247d1 | 2012-12-13 20:49:05 +0000 | [diff] [blame] | 867 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 868 | return fsl_esdhc_initialize(bis, cfg); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 869 | } |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 870 | |
Yangbo Lu | b124f8a | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 871 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
| 872 | void mmc_adapter_card_type_ident(void) |
| 873 | { |
| 874 | u8 card_id; |
| 875 | u8 value; |
| 876 | |
| 877 | card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; |
| 878 | gd->arch.sdhc_adapter = card_id; |
| 879 | |
| 880 | switch (card_id) { |
| 881 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: |
Yangbo Lu | 81eacd6 | 2015-09-17 10:27:12 +0800 | [diff] [blame] | 882 | value = QIXIS_READ(brdcfg[5]); |
| 883 | value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); |
| 884 | QIXIS_WRITE(brdcfg[5], value); |
Yangbo Lu | b124f8a | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 885 | break; |
| 886 | case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: |
Yangbo Lu | c6799ce | 2015-09-17 10:27:48 +0800 | [diff] [blame] | 887 | value = QIXIS_READ(pwr_ctl[1]); |
| 888 | value |= QIXIS_EVDD_BY_SDHC_VS; |
| 889 | QIXIS_WRITE(pwr_ctl[1], value); |
Yangbo Lu | b124f8a | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 890 | break; |
| 891 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: |
| 892 | value = QIXIS_READ(brdcfg[5]); |
| 893 | value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); |
| 894 | QIXIS_WRITE(brdcfg[5], value); |
| 895 | break; |
| 896 | case QIXIS_ESDHC_ADAPTER_TYPE_RSV: |
| 897 | break; |
| 898 | case QIXIS_ESDHC_ADAPTER_TYPE_MMC: |
| 899 | break; |
| 900 | case QIXIS_ESDHC_ADAPTER_TYPE_SD: |
| 901 | break; |
| 902 | case QIXIS_ESDHC_NO_ADAPTER: |
| 903 | break; |
| 904 | default: |
| 905 | break; |
| 906 | } |
| 907 | } |
| 908 | #endif |
| 909 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 910 | #ifdef CONFIG_OF_LIBFDT |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 911 | void fdt_fixup_esdhc(void *blob, bd_t *bd) |
| 912 | { |
| 913 | const char *compat = "fsl,esdhc"; |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 914 | |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 915 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 916 | if (!hwconfig("esdhc")) { |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 917 | do_fixup_by_compat(blob, compat, "status", "disabled", |
| 918 | 8 + 1, 1); |
| 919 | return; |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 920 | } |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 921 | #endif |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 922 | |
Yangbo Lu | 163beec | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 923 | #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK |
| 924 | do_fixup_by_compat_u32(blob, compat, "peripheral-frequency", |
| 925 | gd->arch.sdhc_clk, 1); |
| 926 | #else |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 927 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
Simon Glass | 9e247d1 | 2012-12-13 20:49:05 +0000 | [diff] [blame] | 928 | gd->arch.sdhc_clk, 1); |
Yangbo Lu | 163beec | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 929 | #endif |
Yangbo Lu | b124f8a | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 930 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
| 931 | do_fixup_by_compat_u32(blob, compat, "adapter-type", |
| 932 | (u32)(gd->arch.sdhc_adapter), 1); |
| 933 | #endif |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 934 | do_fixup_by_compat(blob, compat, "status", "okay", |
| 935 | 4 + 1, 1); |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 936 | } |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 937 | #endif |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 938 | |
| 939 | #ifdef CONFIG_DM_MMC |
| 940 | #include <asm/arch/clock.h> |
| 941 | static int fsl_esdhc_probe(struct udevice *dev) |
| 942 | { |
| 943 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
| 944 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 945 | const void *fdt = gd->fdt_blob; |
| 946 | int node = dev->of_offset; |
| 947 | fdt_addr_t addr; |
| 948 | unsigned int val; |
| 949 | int ret; |
| 950 | |
| 951 | addr = dev_get_addr(dev); |
| 952 | if (addr == FDT_ADDR_T_NONE) |
| 953 | return -EINVAL; |
| 954 | |
| 955 | priv->esdhc_regs = (struct fsl_esdhc *)addr; |
| 956 | priv->dev = dev; |
| 957 | |
| 958 | val = fdtdec_get_int(fdt, node, "bus-width", -1); |
| 959 | if (val == 8) |
| 960 | priv->bus_width = 8; |
| 961 | else if (val == 4) |
| 962 | priv->bus_width = 4; |
| 963 | else |
| 964 | priv->bus_width = 1; |
| 965 | |
| 966 | if (fdt_get_property(fdt, node, "non-removable", NULL)) { |
| 967 | priv->non_removable = 1; |
| 968 | } else { |
| 969 | priv->non_removable = 0; |
| 970 | gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0, |
| 971 | &priv->cd_gpio, GPIOD_IS_IN); |
| 972 | } |
| 973 | |
Peng Fan | 01eb1c4 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 974 | priv->wp_enable = 1; |
| 975 | |
| 976 | ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0, |
| 977 | &priv->wp_gpio, GPIOD_IS_IN); |
| 978 | if (ret) |
| 979 | priv->wp_enable = 0; |
| 980 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 981 | /* |
| 982 | * TODO: |
| 983 | * Because lack of clk driver, if SDHC clk is not enabled, |
| 984 | * need to enable it first before this driver is invoked. |
| 985 | * |
| 986 | * we use MXC_ESDHC_CLK to get clk freq. |
| 987 | * If one would like to make this function work, |
| 988 | * the aliases should be provided in dts as this: |
| 989 | * |
| 990 | * aliases { |
| 991 | * mmc0 = &usdhc1; |
| 992 | * mmc1 = &usdhc2; |
| 993 | * mmc2 = &usdhc3; |
| 994 | * mmc3 = &usdhc4; |
| 995 | * }; |
| 996 | * Then if your board only supports mmc2 and mmc3, but we can |
| 997 | * correctly get the seq as 2 and 3, then let mxc_get_clock |
| 998 | * work as expected. |
| 999 | */ |
| 1000 | priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); |
| 1001 | if (priv->sdhc_clk <= 0) { |
| 1002 | dev_err(dev, "Unable to get clk for %s\n", dev->name); |
| 1003 | return -EINVAL; |
| 1004 | } |
| 1005 | |
| 1006 | ret = fsl_esdhc_init(priv); |
| 1007 | if (ret) { |
| 1008 | dev_err(dev, "fsl_esdhc_init failure\n"); |
| 1009 | return ret; |
| 1010 | } |
| 1011 | |
| 1012 | upriv->mmc = priv->mmc; |
| 1013 | |
| 1014 | return 0; |
| 1015 | } |
| 1016 | |
| 1017 | static const struct udevice_id fsl_esdhc_ids[] = { |
| 1018 | { .compatible = "fsl,imx6ul-usdhc", }, |
| 1019 | { .compatible = "fsl,imx6sx-usdhc", }, |
| 1020 | { .compatible = "fsl,imx6sl-usdhc", }, |
| 1021 | { .compatible = "fsl,imx6q-usdhc", }, |
| 1022 | { .compatible = "fsl,imx7d-usdhc", }, |
| 1023 | { /* sentinel */ } |
| 1024 | }; |
| 1025 | |
| 1026 | U_BOOT_DRIVER(fsl_esdhc) = { |
| 1027 | .name = "fsl-esdhc-mmc", |
| 1028 | .id = UCLASS_MMC, |
| 1029 | .of_match = fsl_esdhc_ids, |
| 1030 | .probe = fsl_esdhc_probe, |
| 1031 | .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), |
| 1032 | }; |
| 1033 | #endif |