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Andy Fleminge52ffb82008-10-30 16:47:16 -05001/*
Jerry Huanged413672011-01-06 23:42:19 -06002 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
Andy Fleminge52ffb82008-10-30 16:47:16 -05003 * Andy Fleming
4 *
5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Andy Fleminge52ffb82008-10-30 16:47:16 -050010 */
11
12#include <config.h>
13#include <common.h>
14#include <command.h>
Anton Vorontsovf751a3c2009-06-10 00:25:29 +040015#include <hwconfig.h>
Andy Fleminge52ffb82008-10-30 16:47:16 -050016#include <mmc.h>
17#include <part.h>
18#include <malloc.h>
19#include <mmc.h>
20#include <fsl_esdhc.h>
Anton Vorontsovf751a3c2009-06-10 00:25:29 +040021#include <fdt_support.h>
Andy Fleminge52ffb82008-10-30 16:47:16 -050022#include <asm/io.h>
Peng Fana4d36f72016-03-25 14:16:56 +080023#include <dm.h>
24#include <asm-generic/gpio.h>
Andy Fleminge52ffb82008-10-30 16:47:16 -050025
Andy Fleminge52ffb82008-10-30 16:47:16 -050026DECLARE_GLOBAL_DATA_PTR;
27
Ye.Li3d46c312014-11-04 15:35:49 +080028#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
29 IRQSTATEN_CINT | \
30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
33 IRQSTATEN_DINT)
34
Andy Fleminge52ffb82008-10-30 16:47:16 -050035struct fsl_esdhc {
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080036 uint dsaddr; /* SDMA system address register */
37 uint blkattr; /* Block attributes register */
38 uint cmdarg; /* Command argument register */
39 uint xfertyp; /* Transfer type register */
40 uint cmdrsp0; /* Command response 0 register */
41 uint cmdrsp1; /* Command response 1 register */
42 uint cmdrsp2; /* Command response 2 register */
43 uint cmdrsp3; /* Command response 3 register */
44 uint datport; /* Buffer data port register */
45 uint prsstat; /* Present state register */
46 uint proctl; /* Protocol control register */
47 uint sysctl; /* System Control Register */
48 uint irqstat; /* Interrupt status register */
49 uint irqstaten; /* Interrupt status enable register */
50 uint irqsigen; /* Interrupt signal enable register */
51 uint autoc12err; /* Auto CMD error status register */
52 uint hostcapblt; /* Host controller capabilities register */
53 uint wml; /* Watermark level register */
54 uint mixctrl; /* For USDHC */
55 char reserved1[4]; /* reserved */
56 uint fevt; /* Force event register */
57 uint admaes; /* ADMA error status register */
58 uint adsaddr; /* ADMA system address register */
Peng Fana6eadd52016-06-15 10:53:00 +080059 char reserved2[4];
60 uint dllctrl;
61 uint dllstat;
62 uint clktunectrlstatus;
63 char reserved3[84];
64 uint vendorspec;
65 uint mmcboot;
66 uint vendorspec2;
67 char reserved4[48];
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080068 uint hostver; /* Host controller version register */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080069 char reserved5[4]; /* reserved */
Peng Fana6eadd52016-06-15 10:53:00 +080070 uint dmaerraddr; /* DMA error address register */
Otavio Salvadorfad3e062015-02-17 10:42:43 -020071 char reserved6[4]; /* reserved */
Peng Fana6eadd52016-06-15 10:53:00 +080072 uint dmaerrattr; /* DMA error attribute register */
73 char reserved7[4]; /* reserved */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080074 uint hostcapblt2; /* Host controller capabilities register 2 */
Peng Fana6eadd52016-06-15 10:53:00 +080075 char reserved8[8]; /* reserved */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080076 uint tcr; /* Tuning control register */
Peng Fana6eadd52016-06-15 10:53:00 +080077 char reserved9[28]; /* reserved */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080078 uint sddirctl; /* SD direction control register */
Peng Fana6eadd52016-06-15 10:53:00 +080079 char reserved10[712];/* reserved */
Haijun.Zhangd49eb9e2013-10-30 11:37:55 +080080 uint scr; /* eSDHC control register */
Andy Fleminge52ffb82008-10-30 16:47:16 -050081};
82
Peng Fana4d36f72016-03-25 14:16:56 +080083/**
84 * struct fsl_esdhc_priv
85 *
86 * @esdhc_regs: registers of the sdhc controller
87 * @sdhc_clk: Current clk of the sdhc controller
88 * @bus_width: bus width, 1bit, 4bit or 8bit
89 * @cfg: mmc config
90 * @mmc: mmc
91 * Following is used when Driver Model is enabled for MMC
92 * @dev: pointer for the device
93 * @non_removable: 0: removable; 1: non-removable
Peng Fan01eb1c42016-06-15 10:53:02 +080094 * @wp_enable: 1: enable checking wp; 0: no check
Peng Fana4d36f72016-03-25 14:16:56 +080095 * @cd_gpio: gpio for card detection
Peng Fan01eb1c42016-06-15 10:53:02 +080096 * @wp_gpio: gpio for write protection
Peng Fana4d36f72016-03-25 14:16:56 +080097 */
98struct fsl_esdhc_priv {
99 struct fsl_esdhc *esdhc_regs;
100 unsigned int sdhc_clk;
101 unsigned int bus_width;
102 struct mmc_config cfg;
103 struct mmc *mmc;
104 struct udevice *dev;
105 int non_removable;
Peng Fan01eb1c42016-06-15 10:53:02 +0800106 int wp_enable;
Peng Fana4d36f72016-03-25 14:16:56 +0800107 struct gpio_desc cd_gpio;
Peng Fan01eb1c42016-06-15 10:53:02 +0800108 struct gpio_desc wp_gpio;
Peng Fana4d36f72016-03-25 14:16:56 +0800109};
110
Andy Fleminge52ffb82008-10-30 16:47:16 -0500111/* Return the XFERTYP flags for a given command and data packet */
Kim Phillipsf9e0b602012-10-29 13:34:44 +0000112static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500113{
114 uint xfertyp = 0;
115
116 if (data) {
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530117 xfertyp |= XFERTYP_DPSEL;
118#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
119 xfertyp |= XFERTYP_DMAEN;
120#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500121 if (data->blocks > 1) {
122 xfertyp |= XFERTYP_MSBSEL;
123 xfertyp |= XFERTYP_BCEN;
Jerry Huanged413672011-01-06 23:42:19 -0600124#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
125 xfertyp |= XFERTYP_AC12EN;
126#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500127 }
128
129 if (data->flags & MMC_DATA_READ)
130 xfertyp |= XFERTYP_DTDSEL;
131 }
132
133 if (cmd->resp_type & MMC_RSP_CRC)
134 xfertyp |= XFERTYP_CCCEN;
135 if (cmd->resp_type & MMC_RSP_OPCODE)
136 xfertyp |= XFERTYP_CICEN;
137 if (cmd->resp_type & MMC_RSP_136)
138 xfertyp |= XFERTYP_RSPTYP_136;
139 else if (cmd->resp_type & MMC_RSP_BUSY)
140 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
141 else if (cmd->resp_type & MMC_RSP_PRESENT)
142 xfertyp |= XFERTYP_RSPTYP_48;
143
Jason Liubef0ff02011-03-22 01:32:31 +0000144 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
145 xfertyp |= XFERTYP_CMDTYP_ABORT;
Yangbo Lub73a3d62016-01-21 17:33:19 +0800146
Andy Fleminge52ffb82008-10-30 16:47:16 -0500147 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
148}
149
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530150#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
151/*
152 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
153 */
Wolfgang Denka40545c2010-05-09 23:52:59 +0200154static void
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530155esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
156{
Peng Fana4d36f72016-03-25 14:16:56 +0800157 struct fsl_esdhc_priv *priv = mmc->priv;
158 struct fsl_esdhc *regs = priv->esdhc_regs;
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530159 uint blocks;
160 char *buffer;
161 uint databuf;
162 uint size;
163 uint irqstat;
164 uint timeout;
165
166 if (data->flags & MMC_DATA_READ) {
167 blocks = data->blocks;
168 buffer = data->dest;
169 while (blocks) {
170 timeout = PIO_TIMEOUT;
171 size = data->blocksize;
172 irqstat = esdhc_read32(&regs->irqstat);
173 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
174 && --timeout);
175 if (timeout <= 0) {
176 printf("\nData Read Failed in PIO Mode.");
Wolfgang Denka40545c2010-05-09 23:52:59 +0200177 return;
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530178 }
179 while (size && (!(irqstat & IRQSTAT_TC))) {
180 udelay(100); /* Wait before last byte transfer complete */
181 irqstat = esdhc_read32(&regs->irqstat);
182 databuf = in_le32(&regs->datport);
183 *((uint *)buffer) = databuf;
184 buffer += 4;
185 size -= 4;
186 }
187 blocks--;
188 }
189 } else {
190 blocks = data->blocks;
Wolfgang Denka40545c2010-05-09 23:52:59 +0200191 buffer = (char *)data->src;
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530192 while (blocks) {
193 timeout = PIO_TIMEOUT;
194 size = data->blocksize;
195 irqstat = esdhc_read32(&regs->irqstat);
196 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
197 && --timeout);
198 if (timeout <= 0) {
199 printf("\nData Write Failed in PIO Mode.");
Wolfgang Denka40545c2010-05-09 23:52:59 +0200200 return;
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530201 }
202 while (size && (!(irqstat & IRQSTAT_TC))) {
203 udelay(100); /* Wait before last byte transfer complete */
204 databuf = *((uint *)buffer);
205 buffer += 4;
206 size -= 4;
207 irqstat = esdhc_read32(&regs->irqstat);
208 out_le32(&regs->datport, databuf);
209 }
210 blocks--;
211 }
212 }
213}
214#endif
215
Andy Fleminge52ffb82008-10-30 16:47:16 -0500216static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
217{
Andy Fleminge52ffb82008-10-30 16:47:16 -0500218 int timeout;
Peng Fana4d36f72016-03-25 14:16:56 +0800219 struct fsl_esdhc_priv *priv = mmc->priv;
220 struct fsl_esdhc *regs = priv->esdhc_regs;
Eddy Petrișor5178dc12016-06-05 03:43:00 +0300221#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
Yangbo Lud0e295d2015-03-20 19:28:31 -0700222 dma_addr_t addr;
223#endif
Wolfgang Denka40545c2010-05-09 23:52:59 +0200224 uint wml_value;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500225
226 wml_value = data->blocksize/4;
227
228 if (data->flags & MMC_DATA_READ) {
Priyanka Jain02449632011-02-09 09:24:10 +0530229 if (wml_value > WML_RD_WML_MAX)
230 wml_value = WML_RD_WML_MAX_VAL;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500231
Roy Zange5853af2010-02-09 18:23:33 +0800232 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
Ye.Li33a56b12014-02-20 18:00:57 +0800233#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Eddy Petrișor5178dc12016-06-05 03:43:00 +0300234#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
Yangbo Lud0e295d2015-03-20 19:28:31 -0700235 addr = virt_to_phys((void *)(data->dest));
236 if (upper_32_bits(addr))
237 printf("Error found for upper 32 bits\n");
238 else
239 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
240#else
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100241 esdhc_write32(&regs->dsaddr, (u32)data->dest);
Ye.Li33a56b12014-02-20 18:00:57 +0800242#endif
Yangbo Lud0e295d2015-03-20 19:28:31 -0700243#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500244 } else {
Ye.Li33a56b12014-02-20 18:00:57 +0800245#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Eric Nelson30e9cad2012-04-25 14:28:48 +0000246 flush_dcache_range((ulong)data->src,
247 (ulong)data->src+data->blocks
248 *data->blocksize);
Ye.Li33a56b12014-02-20 18:00:57 +0800249#endif
Priyanka Jain02449632011-02-09 09:24:10 +0530250 if (wml_value > WML_WR_WML_MAX)
251 wml_value = WML_WR_WML_MAX_VAL;
Peng Fan01eb1c42016-06-15 10:53:02 +0800252 if (priv->wp_enable) {
253 if ((esdhc_read32(&regs->prsstat) &
254 PRSSTAT_WPSPL) == 0) {
255 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
256 return TIMEOUT;
257 }
Andy Fleminge52ffb82008-10-30 16:47:16 -0500258 }
Roy Zange5853af2010-02-09 18:23:33 +0800259
260 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
261 wml_value << 16);
Ye.Li33a56b12014-02-20 18:00:57 +0800262#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Eddy Petrișor5178dc12016-06-05 03:43:00 +0300263#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
Yangbo Lud0e295d2015-03-20 19:28:31 -0700264 addr = virt_to_phys((void *)(data->src));
265 if (upper_32_bits(addr))
266 printf("Error found for upper 32 bits\n");
267 else
268 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
269#else
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100270 esdhc_write32(&regs->dsaddr, (u32)data->src);
Ye.Li33a56b12014-02-20 18:00:57 +0800271#endif
Yangbo Lud0e295d2015-03-20 19:28:31 -0700272#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500273 }
274
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100275 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500276
277 /* Calculate the timeout period for data transactions */
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530278 /*
279 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
280 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
281 * So, Number of SD Clock cycles for 0.25sec should be minimum
282 * (SD Clock/sec * 0.25 sec) SD Clock cycles
Andrew Gabbasovd5b48662014-03-24 02:40:41 -0500283 * = (mmc->clock * 1/4) SD Clock cycles
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530284 * As 1) >= 2)
Andrew Gabbasovd5b48662014-03-24 02:40:41 -0500285 * => (2^(timeout+13)) >= mmc->clock * 1/4
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530286 * Taking log2 both the sides
Andrew Gabbasovd5b48662014-03-24 02:40:41 -0500287 * => timeout + 13 >= log2(mmc->clock/4)
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530288 * Rounding up to next power of 2
Andrew Gabbasovd5b48662014-03-24 02:40:41 -0500289 * => timeout + 13 = log2(mmc->clock/4) + 1
290 * => timeout + 13 = fls(mmc->clock/4)
Yangbo Lu9d7f3212015-12-30 14:19:30 +0800291 *
292 * However, the MMC spec "It is strongly recommended for hosts to
293 * implement more than 500ms timeout value even if the card
294 * indicates the 250ms maximum busy length." Even the previous
295 * value of 300ms is known to be insufficient for some cards.
296 * So, we use
297 * => timeout + 13 = fls(mmc->clock/2)
Priyanka Jainc51b40d2011-03-03 09:18:56 +0530298 */
Yangbo Lu9d7f3212015-12-30 14:19:30 +0800299 timeout = fls(mmc->clock/2);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500300 timeout -= 13;
301
302 if (timeout > 14)
303 timeout = 14;
304
305 if (timeout < 0)
306 timeout = 0;
307
Kumar Gala9a878d52011-01-29 15:36:10 -0600308#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
309 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
310 timeout++;
311#endif
312
Haijun.Zhangedeb83a2014-03-18 17:04:23 +0800313#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
314 timeout = 0xE;
315#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100316 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500317
318 return 0;
319}
320
Eric Nelson30e9cad2012-04-25 14:28:48 +0000321static void check_and_invalidate_dcache_range
322 (struct mmc_cmd *cmd,
323 struct mmc_data *data) {
Yangbo Lud0e295d2015-03-20 19:28:31 -0700324 unsigned start = 0;
Yangbo Lue7702c62016-05-12 19:12:58 +0800325 unsigned end = 0;
Eric Nelson30e9cad2012-04-25 14:28:48 +0000326 unsigned size = roundup(ARCH_DMA_MINALIGN,
327 data->blocks*data->blocksize);
Eddy Petrișor5178dc12016-06-05 03:43:00 +0300328#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
Yangbo Lud0e295d2015-03-20 19:28:31 -0700329 dma_addr_t addr;
330
331 addr = virt_to_phys((void *)(data->dest));
332 if (upper_32_bits(addr))
333 printf("Error found for upper 32 bits\n");
334 else
335 start = lower_32_bits(addr);
Yangbo Lue7702c62016-05-12 19:12:58 +0800336#else
337 start = (unsigned)data->dest;
Yangbo Lud0e295d2015-03-20 19:28:31 -0700338#endif
Yangbo Lue7702c62016-05-12 19:12:58 +0800339 end = start + size;
Eric Nelson30e9cad2012-04-25 14:28:48 +0000340 invalidate_dcache_range(start, end);
341}
Tom Rini239dd252014-05-23 09:19:05 -0400342
Andy Fleminge52ffb82008-10-30 16:47:16 -0500343/*
344 * Sends a command out on the bus. Takes the mmc pointer,
345 * a command pointer, and an optional data pointer.
346 */
347static int
348esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
349{
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500350 int err = 0;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500351 uint xfertyp;
352 uint irqstat;
Peng Fana4d36f72016-03-25 14:16:56 +0800353 struct fsl_esdhc_priv *priv = mmc->priv;
354 struct fsl_esdhc *regs = priv->esdhc_regs;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500355
Jerry Huanged413672011-01-06 23:42:19 -0600356#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
357 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
358 return 0;
359#endif
360
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100361 esdhc_write32(&regs->irqstat, -1);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500362
363 sync();
364
365 /* Wait for the bus to be idle */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100366 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
367 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
368 ;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500369
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100370 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
371 ;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500372
373 /* Wait at least 8 SD clock cycles before the next command */
374 /*
375 * Note: This is way more than 8 cycles, but 1ms seems to
376 * resolve timing issues with some cards
377 */
378 udelay(1000);
379
380 /* Set up for a data transfer if we have one */
381 if (data) {
Andy Fleminge52ffb82008-10-30 16:47:16 -0500382 err = esdhc_setup_data(mmc, data);
383 if(err)
384 return err;
Peng Fan9cb5e992015-06-25 10:32:26 +0800385
386 if (data->flags & MMC_DATA_READ)
387 check_and_invalidate_dcache_range(cmd, data);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500388 }
389
390 /* Figure out the transfer arguments */
391 xfertyp = esdhc_xfertyp(cmd, data);
392
Andrew Gabbasov4816b7a2013-06-11 10:34:22 -0500393 /* Mask all irqs */
394 esdhc_write32(&regs->irqsigen, 0);
395
Andy Fleminge52ffb82008-10-30 16:47:16 -0500396 /* Send the command */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100397 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
Jason Liu9919d642011-11-25 00:18:04 +0000398#if defined(CONFIG_FSL_USDHC)
399 esdhc_write32(&regs->mixctrl,
Volodymyr Riazantsevd251e112015-01-20 10:16:44 -0500400 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
401 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
Jason Liu9919d642011-11-25 00:18:04 +0000402 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
403#else
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100404 esdhc_write32(&regs->xfertyp, xfertyp);
Jason Liu9919d642011-11-25 00:18:04 +0000405#endif
Dirk Behmed8552d62012-03-26 03:13:05 +0000406
Andy Fleminge52ffb82008-10-30 16:47:16 -0500407 /* Wait for the command to complete */
Dirk Behmed8552d62012-03-26 03:13:05 +0000408 while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100409 ;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500410
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100411 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500412
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500413 if (irqstat & CMD_ERR) {
414 err = COMM_ERR;
415 goto out;
Dirk Behmed8552d62012-03-26 03:13:05 +0000416 }
417
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500418 if (irqstat & IRQSTAT_CTOE) {
419 err = TIMEOUT;
420 goto out;
421 }
Andy Fleminge52ffb82008-10-30 16:47:16 -0500422
Otavio Salvadorfad3e062015-02-17 10:42:43 -0200423 /* Switch voltage to 1.8V if CMD11 succeeded */
424 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
425 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
426
427 printf("Run CMD11 1.8V switch\n");
428 /* Sleep for 5 ms - max time for card to switch to 1.8V */
429 udelay(5000);
430 }
431
Dirk Behmed8552d62012-03-26 03:13:05 +0000432 /* Workaround for ESDHC errata ENGcm03648 */
433 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
Yangbo Lu3ffa8512015-04-15 10:13:12 +0800434 int timeout = 6000;
Dirk Behmed8552d62012-03-26 03:13:05 +0000435
Yangbo Lu3ffa8512015-04-15 10:13:12 +0800436 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
Dirk Behmed8552d62012-03-26 03:13:05 +0000437 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
438 PRSSTAT_DAT0)) {
439 udelay(100);
440 timeout--;
441 }
442
443 if (timeout <= 0) {
444 printf("Timeout waiting for DAT0 to go high!\n");
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500445 err = TIMEOUT;
446 goto out;
Dirk Behmed8552d62012-03-26 03:13:05 +0000447 }
448 }
449
Andy Fleminge52ffb82008-10-30 16:47:16 -0500450 /* Copy the response to the response buffer */
451 if (cmd->resp_type & MMC_RSP_136) {
452 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
453
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100454 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
455 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
456 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
457 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
Rabin Vincentb6eed942009-04-05 13:30:56 +0530458 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
459 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
460 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
461 cmd->response[3] = (cmdrsp0 << 8);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500462 } else
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100463 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500464
465 /* Wait until all of the blocks are transferred */
466 if (data) {
Dipen Dudhat5c72f352009-10-05 15:41:58 +0530467#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
468 esdhc_pio_read_write(mmc, data);
469#else
Andy Fleminge52ffb82008-10-30 16:47:16 -0500470 do {
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100471 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500472
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500473 if (irqstat & IRQSTAT_DTOE) {
474 err = TIMEOUT;
475 goto out;
476 }
Frans Meulenbroeks010ba982010-07-31 04:45:18 +0000477
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500478 if (irqstat & DATA_ERR) {
479 err = COMM_ERR;
480 goto out;
481 }
Andrew Gabbasov4a929622013-04-07 23:06:08 +0000482 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
Ye.Li33a56b12014-02-20 18:00:57 +0800483
Peng Fan9cb5e992015-06-25 10:32:26 +0800484 /*
485 * Need invalidate the dcache here again to avoid any
486 * cache-fill during the DMA operations such as the
487 * speculative pre-fetching etc.
488 */
Eric Nelson70e68692013-04-03 12:31:56 +0000489 if (data->flags & MMC_DATA_READ)
490 check_and_invalidate_dcache_range(cmd, data);
Ye.Li33a56b12014-02-20 18:00:57 +0800491#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500492 }
493
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500494out:
495 /* Reset CMD and DATA portions on error */
496 if (err) {
497 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
498 SYSCTL_RSTC);
499 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
500 ;
501
502 if (data) {
503 esdhc_write32(&regs->sysctl,
504 esdhc_read32(&regs->sysctl) |
505 SYSCTL_RSTD);
506 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
507 ;
508 }
Otavio Salvadorfad3e062015-02-17 10:42:43 -0200509
510 /* If this was CMD11, then notify that power cycle is needed */
511 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
512 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500513 }
514
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100515 esdhc_write32(&regs->irqstat, -1);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500516
Andrew Gabbasova04a6e02014-03-24 02:41:06 -0500517 return err;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500518}
519
Kim Phillipsf9e0b602012-10-29 13:34:44 +0000520static void set_sysctl(struct mmc *mmc, uint clock)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500521{
Andy Fleminge52ffb82008-10-30 16:47:16 -0500522 int div, pre_div;
Peng Fana4d36f72016-03-25 14:16:56 +0800523 struct fsl_esdhc_priv *priv = mmc->priv;
524 struct fsl_esdhc *regs = priv->esdhc_regs;
525 int sdhc_clk = priv->sdhc_clk;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500526 uint clk;
527
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200528 if (clock < mmc->cfg->f_min)
529 clock = mmc->cfg->f_min;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100530
Andy Fleminge52ffb82008-10-30 16:47:16 -0500531 if (sdhc_clk / 16 > clock) {
532 for (pre_div = 2; pre_div < 256; pre_div *= 2)
533 if ((sdhc_clk / pre_div) <= (clock * 16))
534 break;
535 } else
536 pre_div = 2;
537
538 for (div = 1; div <= 16; div++)
539 if ((sdhc_clk / (div * pre_div)) <= clock)
540 break;
541
Volodymyr Riazantsevd251e112015-01-20 10:16:44 -0500542 pre_div >>= mmc->ddr_mode ? 2 : 1;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500543 div -= 1;
544
545 clk = (pre_div << 8) | (div << 4);
546
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700547#ifdef CONFIG_FSL_USDHC
Ye Li5a24f292016-06-15 10:53:01 +0800548 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700549#else
Kumar Gala09876a32010-03-18 15:51:05 -0500550 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700551#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100552
553 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500554
555 udelay(10000);
556
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700557#ifdef CONFIG_FSL_USDHC
Ye Li5a24f292016-06-15 10:53:01 +0800558 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700559#else
560 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
561#endif
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100562
Andy Fleminge52ffb82008-10-30 16:47:16 -0500563}
564
Yangbo Lu163beec2015-04-22 13:57:40 +0800565#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
566static void esdhc_clock_control(struct mmc *mmc, bool enable)
567{
Peng Fana4d36f72016-03-25 14:16:56 +0800568 struct fsl_esdhc_priv *priv = mmc->priv;
569 struct fsl_esdhc *regs = priv->esdhc_regs;
Yangbo Lu163beec2015-04-22 13:57:40 +0800570 u32 value;
571 u32 time_out;
572
573 value = esdhc_read32(&regs->sysctl);
574
575 if (enable)
576 value |= SYSCTL_CKEN;
577 else
578 value &= ~SYSCTL_CKEN;
579
580 esdhc_write32(&regs->sysctl, value);
581
582 time_out = 20;
583 value = PRSSTAT_SDSTB;
584 while (!(esdhc_read32(&regs->prsstat) & value)) {
585 if (time_out == 0) {
586 printf("fsl_esdhc: Internal clock never stabilised.\n");
587 break;
588 }
589 time_out--;
590 mdelay(1);
591 }
592}
593#endif
594
Andy Fleminge52ffb82008-10-30 16:47:16 -0500595static void esdhc_set_ios(struct mmc *mmc)
596{
Peng Fana4d36f72016-03-25 14:16:56 +0800597 struct fsl_esdhc_priv *priv = mmc->priv;
598 struct fsl_esdhc *regs = priv->esdhc_regs;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500599
Yangbo Lu163beec2015-04-22 13:57:40 +0800600#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
601 /* Select to use peripheral clock */
602 esdhc_clock_control(mmc, false);
603 esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
604 esdhc_clock_control(mmc, true);
605#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500606 /* Set the clock speed */
607 set_sysctl(mmc, mmc->clock);
608
609 /* Set the bus width */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100610 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500611
612 if (mmc->bus_width == 4)
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100613 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500614 else if (mmc->bus_width == 8)
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100615 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
616
Andy Fleminge52ffb82008-10-30 16:47:16 -0500617}
618
619static int esdhc_init(struct mmc *mmc)
620{
Peng Fana4d36f72016-03-25 14:16:56 +0800621 struct fsl_esdhc_priv *priv = mmc->priv;
622 struct fsl_esdhc *regs = priv->esdhc_regs;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500623 int timeout = 1000;
624
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100625 /* Reset the entire host controller */
Dirk Behmedbe67252013-07-15 15:44:29 +0200626 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100627
628 /* Wait until the controller is available */
629 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
630 udelay(1000);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500631
Peng Fana6eadd52016-06-15 10:53:00 +0800632#if defined(CONFIG_FSL_USDHC)
633 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
634 esdhc_write32(&regs->mmcboot, 0x0);
635 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
636 esdhc_write32(&regs->mixctrl, 0x0);
637 esdhc_write32(&regs->clktunectrlstatus, 0x0);
638
639 /* Put VEND_SPEC to default value */
640 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
641
642 /* Disable DLL_CTRL delay line */
643 esdhc_write32(&regs->dllctrl, 0x0);
644#endif
645
Benoît Thébaudeauc08d11c2012-08-13 07:28:16 +0000646#ifndef ARCH_MXC
P.V.Suresh7b1868b2010-12-04 10:37:23 +0530647 /* Enable cache snooping */
Benoît Thébaudeauc08d11c2012-08-13 07:28:16 +0000648 esdhc_write32(&regs->scr, 0x00000040);
649#endif
P.V.Suresh7b1868b2010-12-04 10:37:23 +0530650
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700651#ifndef CONFIG_FSL_USDHC
Dirk Behmedbe67252013-07-15 15:44:29 +0200652 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
Ye Li5a24f292016-06-15 10:53:01 +0800653#else
654 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700655#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500656
657 /* Set the initial clock speed */
Jerry Huang0caea1a2010-11-25 17:06:07 +0000658 mmc_set_clock(mmc, 400000);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500659
660 /* Disable the BRR and BWR bits in IRQSTAT */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100661 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500662
663 /* Put the PROCTL reg back to the default */
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100664 esdhc_write32(&regs->proctl, PROCTL_INIT);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500665
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100666 /* Set timout to the maximum value */
667 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500668
Otavio Salvador12b2a872015-02-17 10:42:44 -0200669#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
670 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
671#endif
672
Thierry Reding8cee4c982012-01-02 01:15:38 +0000673 return 0;
674}
675
676static int esdhc_getcd(struct mmc *mmc)
677{
Peng Fana4d36f72016-03-25 14:16:56 +0800678 struct fsl_esdhc_priv *priv = mmc->priv;
679 struct fsl_esdhc *regs = priv->esdhc_regs;
Thierry Reding8cee4c982012-01-02 01:15:38 +0000680 int timeout = 1000;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500681
Haijun.Zhang05f58542014-01-10 13:52:17 +0800682#ifdef CONFIG_ESDHC_DETECT_QUIRK
683 if (CONFIG_ESDHC_DETECT_QUIRK)
684 return 1;
685#endif
Peng Fana4d36f72016-03-25 14:16:56 +0800686
687#ifdef CONFIG_DM_MMC
688 if (priv->non_removable)
689 return 1;
690
691 if (dm_gpio_is_valid(&priv->cd_gpio))
692 return dm_gpio_get_value(&priv->cd_gpio);
693#endif
694
Thierry Reding8cee4c982012-01-02 01:15:38 +0000695 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
696 udelay(1000);
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100697
Thierry Reding8cee4c982012-01-02 01:15:38 +0000698 return timeout > 0;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500699}
700
Jerry Huangb7ef7562010-03-18 15:57:06 -0500701static void esdhc_reset(struct fsl_esdhc *regs)
702{
703 unsigned long timeout = 100; /* wait max 100 ms */
704
705 /* reset the controller */
Dirk Behmedbe67252013-07-15 15:44:29 +0200706 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
Jerry Huangb7ef7562010-03-18 15:57:06 -0500707
708 /* hardware clears the bit when it is done */
709 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
710 udelay(1000);
711 if (!timeout)
712 printf("MMC/SD: Reset never completed.\n");
713}
714
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200715static const struct mmc_ops esdhc_ops = {
716 .send_cmd = esdhc_send_cmd,
717 .set_ios = esdhc_set_ios,
718 .init = esdhc_init,
719 .getcd = esdhc_getcd,
720};
721
Peng Fana4d36f72016-03-25 14:16:56 +0800722static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
723 struct fsl_esdhc_priv *priv)
724{
725 if (!cfg || !priv)
726 return -EINVAL;
727
728 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
729 priv->bus_width = cfg->max_bus_width;
730 priv->sdhc_clk = cfg->sdhc_clk;
Peng Fan01eb1c42016-06-15 10:53:02 +0800731 priv->wp_enable = cfg->wp_enable;
Peng Fana4d36f72016-03-25 14:16:56 +0800732
733 return 0;
734};
735
736static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
Andy Fleminge52ffb82008-10-30 16:47:16 -0500737{
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100738 struct fsl_esdhc *regs;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500739 struct mmc *mmc;
Li Yangd4933f22010-11-25 17:06:09 +0000740 u32 caps, voltage_caps;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500741
Peng Fana4d36f72016-03-25 14:16:56 +0800742 if (!priv)
743 return -EINVAL;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100744
Peng Fana4d36f72016-03-25 14:16:56 +0800745 regs = priv->esdhc_regs;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100746
Jerry Huangb7ef7562010-03-18 15:57:06 -0500747 /* First reset the eSDHC controller */
748 esdhc_reset(regs);
749
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700750#ifndef CONFIG_FSL_USDHC
Jerry Huang4e3bfa02012-05-17 23:57:02 +0000751 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
752 | SYSCTL_IPGEN | SYSCTL_CKEN);
Ye Li5a24f292016-06-15 10:53:01 +0800753#else
754 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
755 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
Eric Nelsonc8e615c2015-12-04 12:32:48 -0700756#endif
Jerry Huang4e3bfa02012-05-17 23:57:02 +0000757
Ye.Li3d46c312014-11-04 15:35:49 +0800758 writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
Peng Fana4d36f72016-03-25 14:16:56 +0800759 memset(&priv->cfg, 0, sizeof(priv->cfg));
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200760
Li Yangd4933f22010-11-25 17:06:09 +0000761 voltage_caps = 0;
Wang Huanc9292132014-09-05 13:52:40 +0800762 caps = esdhc_read32(&regs->hostcapblt);
Roy Zang39356612011-01-07 00:06:47 -0600763
764#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
765 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
766 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
767#endif
Haijun.Zhang8a065e92013-10-31 09:38:19 +0800768
769/* T4240 host controller capabilities register should have VS33 bit */
770#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
771 caps = caps | ESDHC_HOSTCAPBLT_VS33;
772#endif
773
Andy Fleminge52ffb82008-10-30 16:47:16 -0500774 if (caps & ESDHC_HOSTCAPBLT_VS18)
Li Yangd4933f22010-11-25 17:06:09 +0000775 voltage_caps |= MMC_VDD_165_195;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500776 if (caps & ESDHC_HOSTCAPBLT_VS30)
Li Yangd4933f22010-11-25 17:06:09 +0000777 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500778 if (caps & ESDHC_HOSTCAPBLT_VS33)
Li Yangd4933f22010-11-25 17:06:09 +0000779 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
780
Peng Fana4d36f72016-03-25 14:16:56 +0800781 priv->cfg.name = "FSL_SDHC";
782 priv->cfg.ops = &esdhc_ops;
Li Yangd4933f22010-11-25 17:06:09 +0000783#ifdef CONFIG_SYS_SD_VOLTAGE
Peng Fana4d36f72016-03-25 14:16:56 +0800784 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
Li Yangd4933f22010-11-25 17:06:09 +0000785#else
Peng Fana4d36f72016-03-25 14:16:56 +0800786 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
Li Yangd4933f22010-11-25 17:06:09 +0000787#endif
Peng Fana4d36f72016-03-25 14:16:56 +0800788 if ((priv->cfg.voltages & voltage_caps) == 0) {
Li Yangd4933f22010-11-25 17:06:09 +0000789 printf("voltage not supported by controller\n");
790 return -1;
791 }
Andy Fleminge52ffb82008-10-30 16:47:16 -0500792
Peng Fana4d36f72016-03-25 14:16:56 +0800793 if (priv->bus_width == 8)
794 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
795 else if (priv->bus_width == 4)
796 priv->cfg.host_caps = MMC_MODE_4BIT;
797
798 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
Volodymyr Riazantsevd251e112015-01-20 10:16:44 -0500799#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
Peng Fana4d36f72016-03-25 14:16:56 +0800800 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
Volodymyr Riazantsevd251e112015-01-20 10:16:44 -0500801#endif
Andy Fleminge52ffb82008-10-30 16:47:16 -0500802
Peng Fana4d36f72016-03-25 14:16:56 +0800803 if (priv->bus_width > 0) {
804 if (priv->bus_width < 8)
805 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
806 if (priv->bus_width < 4)
807 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
Abbas Razae6bf9772013-03-25 09:13:34 +0000808 }
809
Andy Fleminge52ffb82008-10-30 16:47:16 -0500810 if (caps & ESDHC_HOSTCAPBLT_HSS)
Peng Fana4d36f72016-03-25 14:16:56 +0800811 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500812
Haijun.Zhangf0fe8ad2014-01-10 13:52:18 +0800813#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
814 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
Peng Fana4d36f72016-03-25 14:16:56 +0800815 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
Haijun.Zhangf0fe8ad2014-01-10 13:52:18 +0800816#endif
817
Peng Fana4d36f72016-03-25 14:16:56 +0800818 priv->cfg.f_min = 400000;
819 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500820
Peng Fana4d36f72016-03-25 14:16:56 +0800821 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200822
Peng Fana4d36f72016-03-25 14:16:56 +0800823 mmc = mmc_create(&priv->cfg, priv);
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200824 if (mmc == NULL)
825 return -1;
Andy Fleminge52ffb82008-10-30 16:47:16 -0500826
Peng Fana4d36f72016-03-25 14:16:56 +0800827 priv->mmc = mmc;
828
829 return 0;
830}
831
832int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
833{
834 struct fsl_esdhc_priv *priv;
835 int ret;
836
837 if (!cfg)
838 return -EINVAL;
839
840 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
841 if (!priv)
842 return -ENOMEM;
843
844 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
845 if (ret) {
846 debug("%s xlate failure\n", __func__);
847 free(priv);
848 return ret;
849 }
850
851 ret = fsl_esdhc_init(priv);
852 if (ret) {
853 debug("%s init failure\n", __func__);
854 free(priv);
855 return ret;
856 }
857
Andy Fleminge52ffb82008-10-30 16:47:16 -0500858 return 0;
859}
860
861int fsl_esdhc_mmc_init(bd_t *bis)
862{
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100863 struct fsl_esdhc_cfg *cfg;
864
Fabio Estevam6592a992012-12-27 08:51:08 +0000865 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100866 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
Simon Glass9e247d12012-12-13 20:49:05 +0000867 cfg->sdhc_clk = gd->arch.sdhc_clk;
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100868 return fsl_esdhc_initialize(bis, cfg);
Andy Fleminge52ffb82008-10-30 16:47:16 -0500869}
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400870
Yangbo Lub124f8a2015-04-22 13:57:00 +0800871#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
872void mmc_adapter_card_type_ident(void)
873{
874 u8 card_id;
875 u8 value;
876
877 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
878 gd->arch.sdhc_adapter = card_id;
879
880 switch (card_id) {
881 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
Yangbo Lu81eacd62015-09-17 10:27:12 +0800882 value = QIXIS_READ(brdcfg[5]);
883 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
884 QIXIS_WRITE(brdcfg[5], value);
Yangbo Lub124f8a2015-04-22 13:57:00 +0800885 break;
886 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
Yangbo Luc6799ce2015-09-17 10:27:48 +0800887 value = QIXIS_READ(pwr_ctl[1]);
888 value |= QIXIS_EVDD_BY_SDHC_VS;
889 QIXIS_WRITE(pwr_ctl[1], value);
Yangbo Lub124f8a2015-04-22 13:57:00 +0800890 break;
891 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
892 value = QIXIS_READ(brdcfg[5]);
893 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
894 QIXIS_WRITE(brdcfg[5], value);
895 break;
896 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
897 break;
898 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
899 break;
900 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
901 break;
902 case QIXIS_ESDHC_NO_ADAPTER:
903 break;
904 default:
905 break;
906 }
907}
908#endif
909
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100910#ifdef CONFIG_OF_LIBFDT
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400911void fdt_fixup_esdhc(void *blob, bd_t *bd)
912{
913 const char *compat = "fsl,esdhc";
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400914
Chenhui Zhao025eab02011-01-04 17:23:05 +0800915#ifdef CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400916 if (!hwconfig("esdhc")) {
Chenhui Zhao025eab02011-01-04 17:23:05 +0800917 do_fixup_by_compat(blob, compat, "status", "disabled",
918 8 + 1, 1);
919 return;
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400920 }
Chenhui Zhao025eab02011-01-04 17:23:05 +0800921#endif
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400922
Yangbo Lu163beec2015-04-22 13:57:40 +0800923#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
924 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
925 gd->arch.sdhc_clk, 1);
926#else
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400927 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
Simon Glass9e247d12012-12-13 20:49:05 +0000928 gd->arch.sdhc_clk, 1);
Yangbo Lu163beec2015-04-22 13:57:40 +0800929#endif
Yangbo Lub124f8a2015-04-22 13:57:00 +0800930#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
931 do_fixup_by_compat_u32(blob, compat, "adapter-type",
932 (u32)(gd->arch.sdhc_adapter), 1);
933#endif
Chenhui Zhao025eab02011-01-04 17:23:05 +0800934 do_fixup_by_compat(blob, compat, "status", "okay",
935 4 + 1, 1);
Anton Vorontsovf751a3c2009-06-10 00:25:29 +0400936}
Stefano Babicff7a5ca2010-02-05 15:11:27 +0100937#endif
Peng Fana4d36f72016-03-25 14:16:56 +0800938
939#ifdef CONFIG_DM_MMC
940#include <asm/arch/clock.h>
941static int fsl_esdhc_probe(struct udevice *dev)
942{
943 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
944 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
945 const void *fdt = gd->fdt_blob;
946 int node = dev->of_offset;
947 fdt_addr_t addr;
948 unsigned int val;
949 int ret;
950
951 addr = dev_get_addr(dev);
952 if (addr == FDT_ADDR_T_NONE)
953 return -EINVAL;
954
955 priv->esdhc_regs = (struct fsl_esdhc *)addr;
956 priv->dev = dev;
957
958 val = fdtdec_get_int(fdt, node, "bus-width", -1);
959 if (val == 8)
960 priv->bus_width = 8;
961 else if (val == 4)
962 priv->bus_width = 4;
963 else
964 priv->bus_width = 1;
965
966 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
967 priv->non_removable = 1;
968 } else {
969 priv->non_removable = 0;
970 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
971 &priv->cd_gpio, GPIOD_IS_IN);
972 }
973
Peng Fan01eb1c42016-06-15 10:53:02 +0800974 priv->wp_enable = 1;
975
976 ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0,
977 &priv->wp_gpio, GPIOD_IS_IN);
978 if (ret)
979 priv->wp_enable = 0;
980
Peng Fana4d36f72016-03-25 14:16:56 +0800981 /*
982 * TODO:
983 * Because lack of clk driver, if SDHC clk is not enabled,
984 * need to enable it first before this driver is invoked.
985 *
986 * we use MXC_ESDHC_CLK to get clk freq.
987 * If one would like to make this function work,
988 * the aliases should be provided in dts as this:
989 *
990 * aliases {
991 * mmc0 = &usdhc1;
992 * mmc1 = &usdhc2;
993 * mmc2 = &usdhc3;
994 * mmc3 = &usdhc4;
995 * };
996 * Then if your board only supports mmc2 and mmc3, but we can
997 * correctly get the seq as 2 and 3, then let mxc_get_clock
998 * work as expected.
999 */
1000 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1001 if (priv->sdhc_clk <= 0) {
1002 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1003 return -EINVAL;
1004 }
1005
1006 ret = fsl_esdhc_init(priv);
1007 if (ret) {
1008 dev_err(dev, "fsl_esdhc_init failure\n");
1009 return ret;
1010 }
1011
1012 upriv->mmc = priv->mmc;
1013
1014 return 0;
1015}
1016
1017static const struct udevice_id fsl_esdhc_ids[] = {
1018 { .compatible = "fsl,imx6ul-usdhc", },
1019 { .compatible = "fsl,imx6sx-usdhc", },
1020 { .compatible = "fsl,imx6sl-usdhc", },
1021 { .compatible = "fsl,imx6q-usdhc", },
1022 { .compatible = "fsl,imx7d-usdhc", },
1023 { /* sentinel */ }
1024};
1025
1026U_BOOT_DRIVER(fsl_esdhc) = {
1027 .name = "fsl-esdhc-mmc",
1028 .id = UCLASS_MMC,
1029 .of_match = fsl_esdhc_ids,
1030 .probe = fsl_esdhc_probe,
1031 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1032};
1033#endif