blob: 65cd3218a051576ae3cff44732cc8ab32856aa07 [file] [log] [blame]
Gabor Juhos02c754a2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 *
Tom Rinifba23012013-07-24 09:34:30 -04004 * SPDX-License-Identifier: GPL-2.0
Gabor Juhos02c754a2013-05-22 03:57:37 +00005 */
6
Paul Burton10a74b52013-11-09 10:22:08 +00007#ifndef _MALTA_CONFIG_H
8#define _MALTA_CONFIG_H
Gabor Juhos02c754a2013-05-22 03:57:37 +00009
Gabor Juhos02c754a2013-05-22 03:57:37 +000010/*
11 * System configuration
12 */
Paul Burton10a74b52013-11-09 10:22:08 +000013#define CONFIG_MALTA
Paul Burtonc2150342014-04-07 10:11:23 +010014#define CONFIG_BOARD_EARLY_INIT_F
Gabor Juhos02c754a2013-05-22 03:57:37 +000015
Gabor Juhos5e195152013-10-24 14:32:00 +020016#define CONFIG_MEMSIZE_IN_BYTES
17
Gabor Juhos652ccee2013-05-22 03:57:42 +000018#define CONFIG_PCI_GT64120
Paul Burton234882c2013-11-08 11:18:50 +000019#define CONFIG_PCI_MSC01
Gabor Juhos439c50c2013-05-22 03:57:44 +000020#define CONFIG_PCNET
Paul Burtonf38eea62013-11-08 11:18:52 +000021#define CONFIG_PCNET_79C973
22#define PCNET_HAS_PROM
Gabor Juhos652ccee2013-05-22 03:57:42 +000023
Paul Burtonc028f9b2013-11-08 11:18:55 +000024#define CONFIG_MISC_INIT_R
25#define CONFIG_RTC_MC146818
26#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
27
Gabor Juhos02c754a2013-05-22 03:57:37 +000028/*
29 * CPU Configuration
30 */
31#define CONFIG_SYS_MHZ 250 /* arbitrary value */
32#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Gabor Juhos02c754a2013-05-22 03:57:37 +000033
Gabor Juhos02c754a2013-05-22 03:57:37 +000034/*
35 * Memory map
36 */
Gabor Juhosc1df3702013-11-12 16:47:32 +010037#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Gabor Juhos02c754a2013-05-22 03:57:37 +000038
Paul Burton825cfbd2016-05-26 14:49:36 +010039#ifdef CONFIG_64BIT
40# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
41#else
42# define CONFIG_SYS_SDRAM_BASE 0x80000000
43#endif
Gabor Juhos02c754a2013-05-22 03:57:37 +000044#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
45
46#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
47
Paul Burton825cfbd2016-05-26 14:49:36 +010048#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000)
49#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
50#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000)
Gabor Juhos02c754a2013-05-22 03:57:37 +000051
52#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
53#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
Paul Burton657b9352013-11-26 17:45:28 +000054#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
Gabor Juhos02c754a2013-05-22 03:57:37 +000055
Gabor Juhos02c754a2013-05-22 03:57:37 +000056#define CONFIG_SYS_CBSIZE 256
57#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
58 sizeof(CONFIG_SYS_PROMPT) + 16)
59#define CONFIG_SYS_MAXARGS 16
60
61#define CONFIG_AUTO_COMPLETE
62#define CONFIG_CMDLINE_EDITING
63
64/*
65 * Serial driver
66 */
67#define CONFIG_BAUDRATE 115200
Paul Burton58ce2cc2016-05-17 07:43:27 +010068#define CONFIG_SYS_NS16550_PORT_MAPPED
Gabor Juhos02c754a2013-05-22 03:57:37 +000069
70/*
Gabor Juhos02c754a2013-05-22 03:57:37 +000071 * Flash configuration
72 */
Paul Burton825cfbd2016-05-26 14:49:36 +010073#ifdef CONFIG_64BIT
74# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000
75#else
76# define CONFIG_SYS_FLASH_BASE 0xbe000000
77#endif
Gabor Juhos2c434772013-05-22 03:57:39 +000078#define CONFIG_SYS_MAX_FLASH_BANKS 1
79#define CONFIG_SYS_MAX_FLASH_SECT 128
80#define CONFIG_SYS_FLASH_CFI
81#define CONFIG_FLASH_CFI_DRIVER
82#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Gabor Juhos02c754a2013-05-22 03:57:37 +000083
84/*
Paul Burton60465222013-11-08 11:18:56 +000085 * Environment
86 */
87#define CONFIG_ENV_IS_IN_FLASH
88#define CONFIG_ENV_SECT_SIZE 0x20000
89#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
90#define CONFIG_ENV_ADDR \
91 (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
92
93/*
Paul Burtonc6c38532015-01-29 10:38:20 +000094 * IDE/ATA
95 */
96#define CONFIG_SYS_IDE_MAXBUS 1
97#define CONFIG_SYS_IDE_MAXDEVICE 2
98#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
99#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
100#define CONFIG_SYS_ATA_DATA_OFFSET 0
101#define CONFIG_SYS_ATA_REG_OFFSET 0
102
103/*
Gabor Juhos02c754a2013-05-22 03:57:37 +0000104 * Commands
105 */
Paul Burtonc028f9b2013-11-08 11:18:55 +0000106#define CONFIG_CMD_DATE
Paul Burtonc6c38532015-01-29 10:38:20 +0000107#define CONFIG_CMD_IDE
Gabor Juhos652ccee2013-05-22 03:57:42 +0000108#define CONFIG_CMD_PCI
109
Gabor Juhos02c754a2013-05-22 03:57:37 +0000110#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
111
Paul Burton10a74b52013-11-09 10:22:08 +0000112#endif /* _MALTA_CONFIG_H */