blob: 25663a99464d67583b501947fda79f79910cd8ed [file] [log] [blame]
Patrick Delaunay85b53972018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
Patrick Delaunay4c5821d2020-07-24 11:13:31 +02004 select SPL_BOARD_INIT
Patrick Delaunay85b53972018-03-12 10:46:10 +01005 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Simon Glass284cb9c2021-07-10 21:14:31 -06008 select SPL_DRIVERS_MISC
Patrick Delaunay85b53972018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
Simon Glass035939e2021-07-10 21:14:30 -060010 select SPL_GPIO
Patrick Delaunay85b53972018-03-12 10:46:10 +010011 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tan9caf7122018-06-14 18:45:19 +080017 select SPL_DM_RESET
Simon Glassf4d60392021-08-08 12:20:12 -060018 select SPL_SERIAL
Patrick Delaunay85b53972018-03-12 10:46:10 +010019 select SPL_SYSCON
Simon Glass1ba1d4e2021-07-10 21:14:28 -060020 select SPL_WATCHDOG if WATCHDOG
Patrick Delaunayf8600202019-04-18 17:32:47 +020021 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
22 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunayaa4e6852019-02-27 17:01:14 +010023 imply SPL_DISPLAY_PRINT
Patrick Delaunay85b53972018-03-12 10:46:10 +010024 imply SPL_LIBDISK_SUPPORT
Simon Glassa5820472021-08-08 12:20:14 -060025 imply SPL_SPI_LOAD if SPL_SPI
Patrick Delaunay85b53972018-03-12 10:46:10 +010026
27config SYS_SOC
28 default "stm32mp"
29
Patrick Delaunay7e517c62019-04-18 17:32:36 +020030config SYS_MALLOC_LEN
31 default 0x2000000
32
Patrick Delaunay088b6762019-04-18 17:32:37 +020033config ENV_SIZE
Patrice Chotardd83bba42019-05-07 18:40:47 +020034 default 0x2000
Patrick Delaunay088b6762019-04-18 17:32:37 +020035
Patrick Delaunay55cf4772022-05-20 18:24:43 +020036choice
37 prompt "Select STMicroelectronics STM32MPxxx Soc"
Patrick Delaunay4c6fcbc2024-01-15 15:05:57 +010038 default STM32MP15X
Patrick Delaunay55cf4772022-05-20 18:24:43 +020039
Patrick Delaunay990e0572024-01-15 15:05:56 +010040config STM32MP13X
Patrick Delaunay123687c2022-05-20 18:24:46 +020041 bool "Support STMicroelectronics STM32MP13x Soc"
Patrick Delaunaye880ea62024-10-11 17:31:49 +020042 select ARCH_EARLY_INIT_R
Patrick Delaunay123687c2022-05-20 18:24:46 +020043 select ARM_SMCCC
44 select CPU_V7A
45 select CPU_V7_HAS_NONSEC
46 select CPU_V7_HAS_VIRT
47 select OF_BOARD
48 select OF_BOARD_SETUP
49 select PINCTRL_STM32
50 select STM32_RCC
51 select STM32_RESET
52 select STM32_SERIAL
53 select SYS_ARCH_TIMER
54 imply CMD_NVEDIT_INFO
55 help
56 support of STMicroelectronics SOC STM32MP13x family
57 STMicroelectronics MPU with core ARMv7
58
Patrick Delaunay4c6fcbc2024-01-15 15:05:57 +010059config STM32MP15X
Patrick Delaunay310aa8a2020-01-13 15:17:42 +010060 bool "Support STMicroelectronics STM32MP15x Soc"
Patrick Delaunaye880ea62024-10-11 17:31:49 +020061 select ARCH_EARLY_INIT_R
Patrick Delaunay196b7db2021-10-11 09:52:49 +020062 select ARCH_SUPPORT_PSCI
Patrick Delaunay1e2a9b72021-10-13 15:11:18 +020063 select BINMAN
Lokesh Vutla81b1a672018-04-26 18:21:26 +053064 select CPU_V7A
Patrick Delaunay196b7db2021-10-11 09:52:49 +020065 select CPU_V7_HAS_NONSEC
Patrick Delaunaye0207372018-04-16 10:13:24 +020066 select CPU_V7_HAS_VIRT
Patrice Chotarddf290812022-01-20 08:19:15 +010067 select OF_BOARD if TFABOOT
Patrick Delaunayde98cbf2019-07-02 13:26:07 +020068 select OF_BOARD_SETUP
Patrick Delaunay85b53972018-03-12 10:46:10 +010069 select PINCTRL_STM32
Patrick Delaunayb139a5b2018-07-09 15:17:20 +020070 select STM32_RCC
Patrick Delaunay85b53972018-03-12 10:46:10 +010071 select STM32_RESET
Patrick Delaunay4368e562019-07-30 19:16:25 +020072 select STM32_SERIAL
Patrick Delaunayefd00f32022-05-20 18:24:40 +020073 select SUPPORT_SPL
Andre Przywara7b169252018-04-12 04:24:46 +030074 select SYS_ARCH_TIMER
Patrick Delaunay59d0da12020-07-02 17:43:45 +020075 imply CMD_NVEDIT_INFO
Patrick Delaunay310aa8a2020-01-13 15:17:42 +010076 help
77 support of STMicroelectronics SOC STM32MP15x family
78 STM32MP157, STM32MP153 or STM32MP151
79 STMicroelectronics MPU with core ARMv7
80 dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrice Chotardd29531c2023-10-27 16:43:04 +020081
82config STM32MP25X
83 bool "Support STMicroelectronics STM32MP25x Soc"
84 select ARM64
85 select CLK_STM32MP25
86 select OF_BOARD
87 select PINCTRL_STM32
88 select STM32_RCC
89 select STM32_RESET
90 select STM32_SERIAL
91 select SYS_ARCH_TIMER
92 select TFABOOT
93 imply CLK_SCMI
94 imply CMD_NVEDIT_INFO
95 imply DM_REGULATOR
96 imply DM_REGULATOR_SCMI
97 imply OPTEE
98 imply RESET_SCMI
99 imply SYSRESET_PSCI
100 imply TEE
101 imply VERSION_VARIABLE
102 help
103 Support of STMicroelectronics SOC STM32MP25x family
104 STMicroelectronics MPU with 2 * A53 core and 1 M33 core
Patrick Delaunay55cf4772022-05-20 18:24:43 +0200105endchoice
106
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +0100107config NR_DRAM_BANKS
108 default 1
109
Patrick Delaunayab7d6442020-09-04 12:55:19 +0200110config DDR_CACHEABLE_SIZE
111 hex "Size of the DDR marked cacheable in pre-reloc stage"
Patrick Delaunayab7d6442020-09-04 12:55:19 +0200112 default 0x40000000
113 help
114 Define the size of the DDR marked as cacheable in U-Boot
115 pre-reloc stage.
116 This option can be useful to avoid speculatif access
117 to secured area of DDR used by TF-A or OP-TEE before U-Boot
118 initialization.
119 The areas marked "no-map" in device tree should be located
120 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
121
Patrick Delaunayfc69c682018-03-20 10:54:54 +0100122config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
123 hex "Partition on MMC2 to use to load U-Boot from"
124 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
125 default 1
126 help
127 Partition on the second MMC to load U-Boot from when the MMC is being
128 used in raw mode
129
Patrick Delaunay43f214c2019-07-05 17:20:15 +0200130config STM32_ETZPC
131 bool "STM32 Extended TrustZone Protection"
Patrick Delaunay4c6fcbc2024-01-15 15:05:57 +0100132 depends on STM32MP15X || STM32MP13X
Patrick Delaunay43f214c2019-07-05 17:20:15 +0200133 default y
Simon Glass1c383742021-12-18 11:27:51 -0700134 imply BOOTP_SERVERIP
Patrick Delaunay43f214c2019-07-05 17:20:15 +0200135 help
136 Say y to enable STM32 Extended TrustZone Protection
137
Alexandru Gagniuc31aa6972021-07-29 11:47:17 -0500138config STM32_ECDSA_VERIFY
139 bool "STM32 ECDSA verification via the ROM API"
140 depends on SPL_ECDSA_VERIFY
141 default y
142 help
143 Say y to enable the uclass driver for ECDSA verification using the
144 ROM API provided on STM32MP.
145 The ROM API is only available during SPL for now.
146
Patrick Delaunay109d13f2019-07-05 17:20:17 +0200147config CMD_STM32KEY
148 bool "command stm32key to fuse public key hash"
Patrick Delaunayc4e18792024-01-15 14:30:54 +0100149 depends on CMDLINE
Patrick Delaunay109d13f2019-07-05 17:20:17 +0200150 help
151 fuse public key hash in corresponding fuse used to authenticate
152 binary.
Patrick Delaunayd6c098a2021-06-28 14:55:57 +0200153 This command is used to evaluate the secure boot on stm32mp SOC,
154 it is deactivated by default in real products.
Patrick Delaunay109d13f2019-07-05 17:20:17 +0200155
Patrick Delaunay123687c2022-05-20 18:24:46 +0200156source "arch/arm/mach-stm32mp/Kconfig.13x"
Patrick Delaunayff45fca2022-05-20 18:24:44 +0200157source "arch/arm/mach-stm32mp/Kconfig.15x"
Patrice Chotardd29531c2023-10-27 16:43:04 +0200158source "arch/arm/mach-stm32mp/Kconfig.25x"
Patrick Delaunay0440d862021-02-25 13:37:00 +0100159source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
Marek Vasut86a02ee2024-03-19 03:45:08 +0100160
161config STM32MP15_PWR
162 bool "Enable driver for STM32MP15x PWR"
163 depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X)
164 default y if STM32MP15X
165 help
166 This config enables implementation of driver-model pmic and
167 regulator uclass features for access to STM32MP15x PWR.
168
169config SPL_STM32MP15_PWR
170 bool "Enable driver for STM32MP15x PWR in SPL"
171 depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X)
172 default y if STM32MP15X
173 help
174 This config enables implementation of driver-model pmic and
175 regulator uclass features for access to STM32MP15x PWR in SPL.
176
Patrick Delaunay85b53972018-03-12 10:46:10 +0100177endif