Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 1 | if ARCH_STM32MP |
| 2 | |
| 3 | config SPL |
Patrick Delaunay | 4c5821d | 2020-07-24 11:13:31 +0200 | [diff] [blame] | 4 | select SPL_BOARD_INIT |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 5 | select SPL_CLK |
| 6 | select SPL_DM |
| 7 | select SPL_DM_SEQ_ALIAS |
Simon Glass | 284cb9c | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 8 | select SPL_DRIVERS_MISC |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 9 | select SPL_FRAMEWORK |
Simon Glass | 035939e | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 10 | select SPL_GPIO |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 11 | select SPL_LIBCOMMON_SUPPORT |
| 12 | select SPL_LIBGENERIC_SUPPORT |
| 13 | select SPL_OF_CONTROL |
| 14 | select SPL_OF_TRANSLATE |
| 15 | select SPL_PINCTRL |
| 16 | select SPL_REGMAP |
Ley Foon Tan | 9caf712 | 2018-06-14 18:45:19 +0800 | [diff] [blame] | 17 | select SPL_DM_RESET |
Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 18 | select SPL_SERIAL |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 19 | select SPL_SYSCON |
Simon Glass | 1ba1d4e | 2021-07-10 21:14:28 -0600 | [diff] [blame] | 20 | select SPL_WATCHDOG if WATCHDOG |
Patrick Delaunay | f860020 | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 21 | imply BOOTSTAGE_STASH if SPL_BOOTSTAGE |
| 22 | imply SPL_BOOTSTAGE if BOOTSTAGE |
Patrick Delaunay | aa4e685 | 2019-02-27 17:01:14 +0100 | [diff] [blame] | 23 | imply SPL_DISPLAY_PRINT |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 24 | imply SPL_LIBDISK_SUPPORT |
Simon Glass | a582047 | 2021-08-08 12:20:14 -0600 | [diff] [blame] | 25 | imply SPL_SPI_LOAD if SPL_SPI |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 26 | |
| 27 | config SYS_SOC |
| 28 | default "stm32mp" |
| 29 | |
Patrick Delaunay | 7e517c6 | 2019-04-18 17:32:36 +0200 | [diff] [blame] | 30 | config SYS_MALLOC_LEN |
| 31 | default 0x2000000 |
| 32 | |
Patrick Delaunay | 088b676 | 2019-04-18 17:32:37 +0200 | [diff] [blame] | 33 | config ENV_SIZE |
Patrice Chotard | d83bba4 | 2019-05-07 18:40:47 +0200 | [diff] [blame] | 34 | default 0x2000 |
Patrick Delaunay | 088b676 | 2019-04-18 17:32:37 +0200 | [diff] [blame] | 35 | |
Patrick Delaunay | 55cf477 | 2022-05-20 18:24:43 +0200 | [diff] [blame] | 36 | choice |
| 37 | prompt "Select STMicroelectronics STM32MPxxx Soc" |
Patrick Delaunay | 4c6fcbc | 2024-01-15 15:05:57 +0100 | [diff] [blame] | 38 | default STM32MP15X |
Patrick Delaunay | 55cf477 | 2022-05-20 18:24:43 +0200 | [diff] [blame] | 39 | |
Patrick Delaunay | 990e057 | 2024-01-15 15:05:56 +0100 | [diff] [blame] | 40 | config STM32MP13X |
Patrick Delaunay | 123687c | 2022-05-20 18:24:46 +0200 | [diff] [blame] | 41 | bool "Support STMicroelectronics STM32MP13x Soc" |
Patrick Delaunay | e880ea6 | 2024-10-11 17:31:49 +0200 | [diff] [blame] | 42 | select ARCH_EARLY_INIT_R |
Patrick Delaunay | 123687c | 2022-05-20 18:24:46 +0200 | [diff] [blame] | 43 | select ARM_SMCCC |
| 44 | select CPU_V7A |
| 45 | select CPU_V7_HAS_NONSEC |
| 46 | select CPU_V7_HAS_VIRT |
| 47 | select OF_BOARD |
| 48 | select OF_BOARD_SETUP |
| 49 | select PINCTRL_STM32 |
| 50 | select STM32_RCC |
| 51 | select STM32_RESET |
| 52 | select STM32_SERIAL |
| 53 | select SYS_ARCH_TIMER |
| 54 | imply CMD_NVEDIT_INFO |
| 55 | help |
| 56 | support of STMicroelectronics SOC STM32MP13x family |
| 57 | STMicroelectronics MPU with core ARMv7 |
| 58 | |
Patrick Delaunay | 4c6fcbc | 2024-01-15 15:05:57 +0100 | [diff] [blame] | 59 | config STM32MP15X |
Patrick Delaunay | 310aa8a | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 60 | bool "Support STMicroelectronics STM32MP15x Soc" |
Patrick Delaunay | e880ea6 | 2024-10-11 17:31:49 +0200 | [diff] [blame] | 61 | select ARCH_EARLY_INIT_R |
Patrick Delaunay | 196b7db | 2021-10-11 09:52:49 +0200 | [diff] [blame] | 62 | select ARCH_SUPPORT_PSCI |
Patrick Delaunay | 1e2a9b7 | 2021-10-13 15:11:18 +0200 | [diff] [blame] | 63 | select BINMAN |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 64 | select CPU_V7A |
Patrick Delaunay | 196b7db | 2021-10-11 09:52:49 +0200 | [diff] [blame] | 65 | select CPU_V7_HAS_NONSEC |
Patrick Delaunay | e020737 | 2018-04-16 10:13:24 +0200 | [diff] [blame] | 66 | select CPU_V7_HAS_VIRT |
Patrice Chotard | df29081 | 2022-01-20 08:19:15 +0100 | [diff] [blame] | 67 | select OF_BOARD if TFABOOT |
Patrick Delaunay | de98cbf | 2019-07-02 13:26:07 +0200 | [diff] [blame] | 68 | select OF_BOARD_SETUP |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 69 | select PINCTRL_STM32 |
Patrick Delaunay | b139a5b | 2018-07-09 15:17:20 +0200 | [diff] [blame] | 70 | select STM32_RCC |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 71 | select STM32_RESET |
Patrick Delaunay | 4368e56 | 2019-07-30 19:16:25 +0200 | [diff] [blame] | 72 | select STM32_SERIAL |
Patrick Delaunay | efd00f3 | 2022-05-20 18:24:40 +0200 | [diff] [blame] | 73 | select SUPPORT_SPL |
Andre Przywara | 7b16925 | 2018-04-12 04:24:46 +0300 | [diff] [blame] | 74 | select SYS_ARCH_TIMER |
Patrick Delaunay | 59d0da1 | 2020-07-02 17:43:45 +0200 | [diff] [blame] | 75 | imply CMD_NVEDIT_INFO |
Patrick Delaunay | 310aa8a | 2020-01-13 15:17:42 +0100 | [diff] [blame] | 76 | help |
| 77 | support of STMicroelectronics SOC STM32MP15x family |
| 78 | STM32MP157, STM32MP153 or STM32MP151 |
| 79 | STMicroelectronics MPU with core ARMv7 |
| 80 | dual core A7 for STM32MP157/3, monocore for STM32MP151 |
Patrice Chotard | d29531c | 2023-10-27 16:43:04 +0200 | [diff] [blame] | 81 | |
| 82 | config STM32MP25X |
| 83 | bool "Support STMicroelectronics STM32MP25x Soc" |
| 84 | select ARM64 |
| 85 | select CLK_STM32MP25 |
| 86 | select OF_BOARD |
| 87 | select PINCTRL_STM32 |
| 88 | select STM32_RCC |
| 89 | select STM32_RESET |
| 90 | select STM32_SERIAL |
| 91 | select SYS_ARCH_TIMER |
| 92 | select TFABOOT |
| 93 | imply CLK_SCMI |
| 94 | imply CMD_NVEDIT_INFO |
| 95 | imply DM_REGULATOR |
| 96 | imply DM_REGULATOR_SCMI |
| 97 | imply OPTEE |
| 98 | imply RESET_SCMI |
| 99 | imply SYSRESET_PSCI |
| 100 | imply TEE |
| 101 | imply VERSION_VARIABLE |
| 102 | help |
| 103 | Support of STMicroelectronics SOC STM32MP25x family |
| 104 | STMicroelectronics MPU with 2 * A53 core and 1 M33 core |
Patrick Delaunay | 55cf477 | 2022-05-20 18:24:43 +0200 | [diff] [blame] | 105 | endchoice |
| 106 | |
Patrick Delaunay | 6d3cbf3 | 2019-02-27 17:01:15 +0100 | [diff] [blame] | 107 | config NR_DRAM_BANKS |
| 108 | default 1 |
| 109 | |
Patrick Delaunay | ab7d644 | 2020-09-04 12:55:19 +0200 | [diff] [blame] | 110 | config DDR_CACHEABLE_SIZE |
| 111 | hex "Size of the DDR marked cacheable in pre-reloc stage" |
Patrick Delaunay | ab7d644 | 2020-09-04 12:55:19 +0200 | [diff] [blame] | 112 | default 0x40000000 |
| 113 | help |
| 114 | Define the size of the DDR marked as cacheable in U-Boot |
| 115 | pre-reloc stage. |
| 116 | This option can be useful to avoid speculatif access |
| 117 | to secured area of DDR used by TF-A or OP-TEE before U-Boot |
| 118 | initialization. |
| 119 | The areas marked "no-map" in device tree should be located |
| 120 | before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. |
| 121 | |
Patrick Delaunay | fc69c68 | 2018-03-20 10:54:54 +0100 | [diff] [blame] | 122 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 |
| 123 | hex "Partition on MMC2 to use to load U-Boot from" |
| 124 | depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION |
| 125 | default 1 |
| 126 | help |
| 127 | Partition on the second MMC to load U-Boot from when the MMC is being |
| 128 | used in raw mode |
| 129 | |
Patrick Delaunay | 43f214c | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 130 | config STM32_ETZPC |
| 131 | bool "STM32 Extended TrustZone Protection" |
Patrick Delaunay | 4c6fcbc | 2024-01-15 15:05:57 +0100 | [diff] [blame] | 132 | depends on STM32MP15X || STM32MP13X |
Patrick Delaunay | 43f214c | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 133 | default y |
Simon Glass | 1c38374 | 2021-12-18 11:27:51 -0700 | [diff] [blame] | 134 | imply BOOTP_SERVERIP |
Patrick Delaunay | 43f214c | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 135 | help |
| 136 | Say y to enable STM32 Extended TrustZone Protection |
| 137 | |
Alexandru Gagniuc | 31aa697 | 2021-07-29 11:47:17 -0500 | [diff] [blame] | 138 | config STM32_ECDSA_VERIFY |
| 139 | bool "STM32 ECDSA verification via the ROM API" |
| 140 | depends on SPL_ECDSA_VERIFY |
| 141 | default y |
| 142 | help |
| 143 | Say y to enable the uclass driver for ECDSA verification using the |
| 144 | ROM API provided on STM32MP. |
| 145 | The ROM API is only available during SPL for now. |
| 146 | |
Patrick Delaunay | 109d13f | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 147 | config CMD_STM32KEY |
| 148 | bool "command stm32key to fuse public key hash" |
Patrick Delaunay | c4e1879 | 2024-01-15 14:30:54 +0100 | [diff] [blame] | 149 | depends on CMDLINE |
Patrick Delaunay | 109d13f | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 150 | help |
| 151 | fuse public key hash in corresponding fuse used to authenticate |
| 152 | binary. |
Patrick Delaunay | d6c098a | 2021-06-28 14:55:57 +0200 | [diff] [blame] | 153 | This command is used to evaluate the secure boot on stm32mp SOC, |
| 154 | it is deactivated by default in real products. |
Patrick Delaunay | 109d13f | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 155 | |
Patrick Delaunay | 123687c | 2022-05-20 18:24:46 +0200 | [diff] [blame] | 156 | source "arch/arm/mach-stm32mp/Kconfig.13x" |
Patrick Delaunay | ff45fca | 2022-05-20 18:24:44 +0200 | [diff] [blame] | 157 | source "arch/arm/mach-stm32mp/Kconfig.15x" |
Patrice Chotard | d29531c | 2023-10-27 16:43:04 +0200 | [diff] [blame] | 158 | source "arch/arm/mach-stm32mp/Kconfig.25x" |
Patrick Delaunay | 0440d86 | 2021-02-25 13:37:00 +0100 | [diff] [blame] | 159 | source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" |
Marek Vasut | 86a02ee | 2024-03-19 03:45:08 +0100 | [diff] [blame] | 160 | |
| 161 | config STM32MP15_PWR |
| 162 | bool "Enable driver for STM32MP15x PWR" |
| 163 | depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X) |
| 164 | default y if STM32MP15X |
| 165 | help |
| 166 | This config enables implementation of driver-model pmic and |
| 167 | regulator uclass features for access to STM32MP15x PWR. |
| 168 | |
| 169 | config SPL_STM32MP15_PWR |
| 170 | bool "Enable driver for STM32MP15x PWR in SPL" |
| 171 | depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X) |
| 172 | default y if STM32MP15X |
| 173 | help |
| 174 | This config enables implementation of driver-model pmic and |
| 175 | regulator uclass features for access to STM32MP15x PWR in SPL. |
| 176 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 177 | endif |